Nonlinearities of Multisampled Phase-Shifted PWM in Unbalanced Multicell Converters

This article reveals, analyzes, and proposes the method to mitigate nonlinear effects of multisampled multiupdate (MSMU) digital pulsewidth modulation (PS-DPWM) that appear in unbalanced multicell voltage-source converters (MC-VSCs). For balanced MC-VSCs, the harmonic cancellation of PS-DPWM allows for an increase in the sampling frequency, ensuring that the average current is acquired at the peaks, valleys, and intersections of all the triangular carriers. For unbalanced operation, which is typically encountered in practice, e.g., due to cell voltage mismatch in multilevel MC-VSCs and inductance mismatch in interleaved MC-VSCs, harmonic cancellation of PS-DPWM is compromised and, thus, the increased sampling frequency brings switching ripple in the feedback signal. Since in MSMU control the modulating signal is also updated at peaks, valleys, and intersections of all the carriers, this may cause vertical intersections between the modulating signal and the carriers, resulting in specific nonlinear effects. The nonlinearities are shown to introduce limit-cycle oscillations (LCOs) and output waveform distortion. A method to prevent such detrimental impact of MSMU-PS-PWM is also proposed. A simple analytical procedure is proposed to quantify the analyzed nonlinear effects, revealing that they are more emphasized for higher levels of imbalance and control bandwidth. Moreover, the modulator nonlinearity is shown to decrease as the number of cells increases. The analyses are verified in simulations and experiments, using laboratory prototypes of three- and four-level MC-VSCs.

Since in MSMU the modulating signal is updated at the peaks, valleys, and intersections of all the carriers, vertical intersections between the modulating signal and the carriers may occur around certain operating points [19], [26], [27].
In MSMU two-level VSCs, vertical intersections occur even in steady-state conditions as the switching ripple is always introduced into the feedback loop.On the other hand, in balanced MSMU MC-VSCs, vertical intersections are not possible in steady-state conditions.Nevertheless, ideally balanced operation is rarely achieved in practice due to tolerances of passive components, timing mismatches in gate-driving circuits, transients, different nature of the sources/loads connected to each cell's dc link, etc. [1], [5], [9], [22], [23], [24], [25], [28], [29], [30], [31], [32].Imbalance deteriorates frequency multiplication and causes the switching ripple to appear in the feedback.This may also happen under balanced conditions, if center-pulse (synchronous) sampling [33] is impaired, e.g., due to delays in driver circuits, deadtimes, and delays in sensing circuits.As a consequence, in its sampled variant, the modulating signal features jump discontinuities [27], which pose a risk for vertical intersections.Though their impact on two-level VSCs with MSMU-DPWM is well-investigated [27], the behavior of MSMU-PS-DPWM in unbalanced MC-VSCs has not been addressed in the literature so far.
To fill in the gaps of previous research, this article analyses the discontinuity-related nonlinear effects of MSMU-PS-DPWM that appear in unbalanced MC-VSCs.For accurate modeling of PS-DPWM behavior, a static transcharacteristic is defined for each phase-shifted carrier separately.Then, it is shown that similar to MSMU two-level VSCs, depending on the sign of the modulating signal discontinuity, vertical intersections cause reduced-gain, zero-gain, and infinite-gain (jitter) zones in the transcharacteristics [26], [27], [34].In contrast to MSMU two-level VSCs, it is demonstrated that vertical intersections in MSMU MC-VSCs always cause limit-cycle oscillations (LCOs).For MC-VSCs with a dc operating point, this prevents steady-state operation to be achieved, whereas in case of ac operating point, the output current is strongly distorted.Thus, in industrial applications where a certain degree of imbalance is most often encountered, a widely used MSMU-PS-DPWM may bring a detrimental impact, which is for the first time analyzed in this article and demonstrated using laboratory prototypes of three-and four-level MC-VSCs.The extent of discontinuity-related nonlinear effects in unbalanced MC-VSCs with MSMU-PS-DPWM is shown to be proportional to the relative imbalance magnitude and relative crossover frequency of the current control loop.As the number of cells increases, the modulating waveform discontinuities are reduced, causing therefore nonlinearity of MSMU-PS-DPWM to diminish.Still, to prevent the detrimental impact of modulator nonlinearity that is pronounced in unbalanced multilevel and interleaved converters with lower number of cells, some provision has to be taken in practical applications.As one such a method, this article proposes digital feedback filtering which removes the switching ripple from the sampled current without impairing control loop's small-signal dynamic performance.Although reported before for two-level VSCs with MSMU-DPWM [35], [36], the use of RRRs in MC-VSCs with MSMU-PS-DPWM has not been considered before, as ripple-induced nonlinearities were neglected.
This article is organized as follows.In Section II, MSMU-PS-DPWM control of MC-VSCs is introduced, and the basic types of intersections between the modulating signal and the carriers are outlined, along with an explanation of the jittering mechanism.The impact of mismatched dc link voltages in multilevel MC-VSCs and mismatched inductances in interleaved MC-VSCs on the appearance of the switching ripple component in the modulating signal is illustrated in Section III.The resulting nonlinear effects are quantitatively analyzed in Section IV and their adverse effect on converter's input and output waveforms is illustrated.In Section V, the experimental measurements of modulator transcharacteristics are shown to be in excellent agreement with the simulations and analytics.The detrimental impact of LCOs on the performance of dc-dc and dc-ac MC-VSCs is also experimentally verified as illustrated in Section V in the time domain.Section VI concludes the article.As an addendum, suppression of the reported nonlinear effects of MSMU-PS-DPWM is addressed in Appendix.

A. System Description
In this article, digital current-controlled MC-VSCs with MSMU-PS-DPWM are considered.As examples of multilevel and interleaved MC-VSCs, single-phase converters consisting of N series-and parallel-stacked half-bridge or full-bridge cells, shown in Fig. 1, are used.Nevertheless, the presented methodology can be applied to other single-or multiphase multicell topologies with MSMU-PS-DPWM.
In Fig. 1(a), each cell is supplied from a separate dc source, E i .The output voltages of all the cells, v s1 , . . ., v s N , are summed to form the output voltage of the MC-VSC, v s .The difference between v s and load voltage v o is applied to an inductive filter, L. In Fig. 1(b), all the cells are supplied from the same dc source, E. The output voltage of each cell, v si , is applied to an inductor, L i , and the currents of all the inductors, i 1 , . . ., i N , are summed to form the output current, i L , of the MC-VSC.
A block diagram of the considered current-controlled system is shown in Fig. 2.An analog-to-digital converter (ADC) performs the transition from continuous to digital domain.The sampling of i L is performed at the center of the applied voltage pulses, ensuring the center-pulse (synchronous) sampling [33], with the rate f s equal to the total number of edges that can be modulated.Under balanced conditions, this ensures removal of the switching ripple from i L .Assuming half-bridge cells and PS-DPWM with (360 • /N ) phase shift1 between the adjacent triangular2 carriers [10], this yields f s = 2N f pwm = N ms f pwm , where f pwm is the switching (carrier) frequency and N ms is the multisampling factor.In the case of full-bridge cells with bipolar PS-DPWM, nothing changes compared with halfbridge cells.The analysis is also easily extendable to unipolar PS-DPWM.
If the application of interest requires digital feedback filtering, the sampled current i s can be processed by G f b (z), resulting in i f . 3By subtracting i f from the reference i r , the error signal e is obtained and used as the input to the current controller G c .The controller output update is delayed by d sampling periods T s = (1/ f s ), due to the finite execution time [33].The voltage reference generated by the current controller is scaled by K to the range [0, 1], resulting in the digital modulating signal m s .For half-bridge cells K = E , where E = N E n for multilevel and E = E n for interleaved converters, and E n is the cell's nominal input dc voltage.For full-bridge cells K = 2E , and an additional offset has to be added, which is not shown in Fig. 2 as it does not affect the proposed analysis.The entire digital system runs at the rate determined by the sampling frequency f s .
The PS-DPWM serves as an interface between digital and continuous domains.This article considers symmetric PS-DPWM, where the same signal m s is used to modulate each cell.Its inherent ZOH function transforms m s to m and compares it with the carrier w i , belonging to DPWM i .In this way, the switching signal x i is obtained, which is a square waveform with duty cycle D i . 4It is used to control the power switches within the ith cell of the MC-VSC.

B. Intersections Between Modulating Signal and Carriers
In multisampled single-and double-update PS-DPWM, the modulating signal for each cell is updated at the peaks and/or valleys of the carrier corresponding to that cell [16], [18].This results in only horizontal intersections between the modulating signal and the carrier.In MSMU-PS-DPWM, the modulating signal, which is the same for all cells, is updated at every sampling instant, i.e., at the peaks, valleys, and intersections of all the carriers, which is more than twice per carrier period, T pwm = (1/ f pwm ).Thus, due to the discontinuity of m, vertical intersections between m and w i are now possible [19], [20], [27].Fig. 3. Different intersections between m and w i for MSMU-PS-DPWM with N = 2.For DPWM 1 , corresponding to w 1 , a counter-phase vertical and a horizontal intersection occur during negative and positive slopes of w 1 , respectively.For DPWM 2 , corresponding to w 2 , an in-phase "vertical" and a horizontal intersection occur during positive and negative slopes of w 2 , respectively.To prevent multiple commutations, the switching action of DPWM i is defined by the first intersection between m and w i , which turns in-phase "vertical" into horizontal intersections.
Due to the imposed synchronization between the update of m and the carriers, vertical intersections may occur only around certain operating points, which are determined by N ms [27].These operating points are defined as the critical duty cycles where 1 ≤ k < N and k is an integer.
To analyze the modulator nonlinearities induced by vertical intersections, it is important to differentiate between in-phase and counter-phase operation, determined by the relationship between the slope of m and the slope of w i [27].When, at the update instant closest to the intersection with w i , the slope of m has the same sign as the slope of w i , the intersection and the operation of DPWM i are referred to as in-phase [27].On the other hand, when the slopes have opposite signs, the intersection and the operation of DPWM i are referred to as counter-phase [27].An interesting property of MSMU-PS-DPWM is that an in-phase operation for one carrier is a counter-phase operation for another carrier, which is illustrated in Fig. 3 for MSMU-PS-DPWM with N = 2 (to make the illustration clear, but the same holds also for higher N ).This is because the modulating signal is updated at instants when exactly two carriers intersect.As shown in Sections IV and V, this has a detrimental impact on the nonlinear phenomena that appear in MC-VSCs.

C. Jitter Amplification Phenomenon
In [27] and [34], it is shown that for two-level converters in-phase operation and the modulating signal discontinuity result in jitter amplification phenomenon.Since in case of MC-VSCs, as previously explained, at least one of the phase-shifted carriers always features in-phase operation, vertical intersections always result in jitter amplification phenomenon, which is for the first time analyzed in this article.The mechanism Fig. 4. Example of an operating regime that may cause jitter amplification for MSMU-PS-DPWM with N = 2. In-phase operation that is present for w 1 , together with the modulating signal discontinuity, poses a risk for limit cycling (duty cycle jittering).
behind it is illustrated in Fig. 4 and briefly explained below, using MSMU-PS-DPWM with N = 2 as an example, but the conclusions remain the same also for other values of N . 5n the example shown in Fig. 4, an in-phase operation is present for w 1 .Consider an initial operating point, where the falling edge of x 1 is determined by the intersection between w 1 and the modulating segment m 1off,1 , resulting in the duty cycle D 1,1 .In case the closed-loop control yields a small change in the controller's output, such that a higher duty cycle is required, the modulating signal is incremented by a certain amount d⟨m⟩.As illustrated in Fig. 4, a very small positive d⟨m⟩ causes the falling edge of x 1 to be determined by the following segment m 1off,2 , which changes the duty cycle from D 1,1 to D 1,2 .As the applied duty cycle is higher than the required one, the controller will respond by decreasing the value of m, which, in the subsequent switching period, may again cause the segment m 1off,1 to intersect with w 1 .Thus, x 1 is determined by the modulating signal discontinuity m 1cu , rather than d⟨m⟩.This results in limit cycling (duty cycle jittering) that has detrimental impact on system performance, as illustrated by the time-domain waveforms from simulations and experiments for MC-VSCs with dc and ac operating point.The incapability of MSMU-PS-DPWM to achieve desired duty cycle is manifested as "increased-gain" regions in the modulator static transcharacteristics corresponding to the carriers that feature an in-phase operation, as explained in Section IV-A.

D. Enabling Mechanism Behind Vertical Intersections
For vertical intersections to occur, some disturbance is required when the operating point is close to D c .For example, a change in m can be caused by reacting to transient variations or, under steady-state conditions, by the switching ripple component.In this article, the effects due to the latter are addressed.
For balanced MC-VSCs with MSMU-PS-DPWM, the ripple frequency is increased to N f pwm , which allows for sampling the average current with the rate f s = 2N f pwm .Therefore, considering the ideal choice of sampling instants, switching ripple of i L is not introduced in the feedback signal and m does not contain any switching ripple component.However, with imbalance, the frequency multiplication is lost and the switching ripple appears in m.
Mismatched values of the cells' dc link voltages, in case of multilevel MC-VSCs, and of the inductances, in case of interleaved MC-VSCs, are used in this article as illustrative examples of the imbalance.To analyze the nonlinearity of MSMU-PS-DPWM with such an imbalance, it is of interest to gain insight into the shape of the switching ripple waveform at D c , as addressed in Section III.

A. Output Current Ripple in Multilevel MC-VSCs With Mismatched DC Links
The current ripple waveform in unbalanced multilevel MC-VSCs depends, in a general case, on the dc link voltages of all the cells.Thus, general statements about its shape require complicated spectral analyses [10], [40], which lack a clear insight, especially for higher N .To illustrate core principles without using complex mathematical procedures, for the subsequent analyses, we introduce some assumptions regarding the distribution of imbalance among the cells.Nevertheless, it is important to emphasize that as verified in the simulations and experiments, the resulting nonlinear effects only quantitatively change in the most general case with an arbitrary imbalance distribution.
At first, it is assumed that N i=1 E i = N E n .For N = 2, this yields two possible imbalance distributions: where E > 0 is referred to as the magnitude of the voltage imbalance.As an example, waveforms of interest at D c = (1/2) are shown in Fig. 5(a), for a multilevel MC-VSC with two half-bridge cells, As seen, the output current ripple at D c = (1/2) is triangular with the fundamental frequency component at f pwm and the peak-peak value where ).There are cases, also for N > 2, where the output current ripple at D c is a triangular waveform with the fundamental frequency component at f pwm and the peak-peak value defined by (2).One such example is the following distribution of imbalance: Relevant waveforms with such imbalance for a multilevel MC-VSC with three half-bridge cells are shown in Fig. 5(b), Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.at D c = (1/3).It is easy to show that for some imbalance distributions, the ripple is not triangular.For example, in Fig. 5(c) an illustration is given for Nonetheless, it can be shown that for an arbitrary imbalance distribution, the peak-peak value of the current ripple at D c and I , is proportional to the joined imbalance magnitude, E D c , determined at each D c as described below.Namely, due to PS-DPWM, the voltage across the inductor, v L (t), is a piecewise constant waveform, which, in a general case, at D c features N different values V Lh within one T pwm , where h = (1, . . ., N ) denotes the index of the segment, starting from w 1 = 0, during which v L (t) = V Lh .Each V Lh causes i L to change for I h within the time period (T pwm /N ), i.e., I h = (V Lh /N f pwm L).By finding the array of subsequent voltages applied to the inductor that features the highest sum , the peak-peak value of the inductor current ripple at D c , in case of an arbitrary imbalance distribution, is determined Note that for balanced operation where E D c = 0, at D c I = 0, which is a known property of PS-DPWM.Due to this property, the operating points defined by (1) are sometimes called nominal conversion ratios [5].

B. Output Current Ripple in Interleaved MC-VSCs With Mismatched Inductances
To illustrate the influence of mismatched inductances on the shape of the output current ripple at D c in interleaved MC-VSCs, the waveforms of interest are shown in Fig. 5(d) for an interleaved MC-VSC with two half-bridge cells, L 1 = L n − L and L 2 = L n + L, where L n is the nominal inductance and L > 0 is the magnitude of the inductance imbalance.As seen from Fig. 5(d), the current ripple exhibits the same waveform as the one in Fig. 5(a), with the peak-peak value given by It can be shown that also in interleaved MC-VSCs with N > 2, the influence of the imbalance on the shape of the output current ripple at D c is similar to the one in multilevel MC-VSCs.Thus, without loss of generality, the subsequent analyses are performed for multilevel MC-VSCs, but the conclusions are easily applied also to interleaved MC-VSCs.This was verified by running simulations also for interleaved MC-VSCs converters, but the results are not included due to space limitations.

C. Modulating Signal Ripple
For regulating the output current of the MC-VSCs, proportional-integral or proportional-resonant controllers are widely used [1], [2], [13], [14].They are designed so that the impact of the integral or the resonant action is bandlimited well below the crossover frequency f c .Consequently, at high frequencies, their frequency response converges to the one determined by the proportional gain.Thus, for these, highfrequency proportional-dominant controllers, the peak-peak value of the switching ripple component of the modulating signal, m pp , can be very closely approximated as proportional to the relative crossover frequency f cr of the current loop [26].Moreover, since at D c , I ∝ E, m pp at D c is proportional to the relative imbalance magnitude, E r where k p = 2π f c L is the proportional gain of the current controller.Thus, the nonlinear effects of MSMU-PS-DPWM in unbalanced MC-VSCs, caused by the ripple in m, can be analyzed in a relative manner, by changing only E r and f cr .
Note that in addition to E r and f cr , the time delay present in the propagation path of switching and feedback signals also impacts the modulator nonlinearities.Namely, by shifting the position of the modulating signal ripple with respect to the carriers, delay affects the types of intersections between m and w i [27].

IV. ANALYSIS OF MSMU-PS-DPWM NONLINEARITIES IN UNBALANCED MULTICELL CONVERTERS A. Modulator Transcharacterization
One way to describe the behavior of the modulator is a static transcharacteristic [27], which, in case of PS-DPWM, has to be Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 6.
Types of zones that may appear in transcharacteristic of DPWM i (a) linear behavior obtained with double horizontal intersections, (b) reduced-gain zone obtained with a single counter-phase vertical intersection, (c) zero-gain (dead-band) zone obtained with double counter-phase vertical intersections, and (d) infinite-gain (jitter) zone obtained with in-phase "vertical" intersection.defined for each carrier separately.The transcharacteristic of DPWM i provides the value of D i , as a function of the average value of the modulating signal over one switching period, ⟨m⟩, calculated as an average of N ms values of m s within one T pwm .In Fig. 3, this corresponds to ((m s1 + m s2 + m s3 + m s4 )/4).
The transcharacteristic of DPWM i is a piecewise linear function, with different gains k i = (d D i /(d⟨m⟩)) of each linear segment, determined by different types of intersections between m and w i .In this article, k i is referred to as the gain of DPWM i .In case of horizontal intersections between m and w i , D i is determined by a unique modulating signal and both the edges of x i are equally modulated by applying a small perturbation of the modulating signal, d⟨m⟩.Thus, linear behavior of DPWM i is achieved and k i ≈ 1, as shown in Fig. 6(a).Note that in the presence of an imbalance, k i is not exactly equal to 1 due to the ripple modulation effect [26].Vertical intersections between m and w i cause the gain of DPWM i to deviate from k i ≈ 1 [27].Counter-phase vertical intersections can occur for one or both the slopes of w i , preventing thereby the modulation of one or both the edges of x i .This results in reduced-or zero-gain (dead-band) zones [26] in the transcharacteristic of DPWM i , which, as shown in Fig. 6(b) and (c), feature k i ≈ (1/2) and k i = 0.The logic that prevents multiple commutations turns the in-phase "vertical" intersections into horizontal ones, which brings another nonlinear phenomenon.Namely, as explained in Section II-C, a small perturbation d⟨m⟩ causes the response of one or both the edges of x i to be determined by the modulating signal discontinuity, instead of d⟨m⟩, resulting in increased gain of DPWM i .The in-phase "vertical" intersections can appear for both the slopes of w i , or in combination with a horizontal or counter-phase vertical intersection.With in-phase operation, there is a range of duty cycles for which the steady-state cannot be achieved, and thus, the transcharacteristics are not defined [34].However, to indicate their impact, the corresponding nonlinearity zones are represented by vertical lines (k i → ∞), as shown in Fig. 6(d).These zones are referred to as infinite-gain (jitter) zones [27], because they result in LCOs, which have an adverse effect in MC-VSCs with either dc or ac operating point, as demonstrated in simulations and experiments.

B. Discontinuities of Critical Modulating Segments
Since the vertical intersections occur to an extent determined by the discontinuity of m [27], to quantify the actuator (modulator) nonlinearity induced by them, it is of interest to define the critical modulating segments and their discontinuities.
Similar to the definitions in [27] and [34], the critical modulating segments of DPWM i are defined as the two subsequent segments of m before and after the update instant closest to the intersection between m and w i .For each DPWM i , two pairs of critical modulating segments exist, each corresponding to one of the slopes of w i .
The discontinuities of DPWM i 's critical modulating segments for positive ( m icu ) and negative ( m icd ) slopes of w i are then defined as in [27] where ϵ is an infinitely small positive number, and T icu and T icd are the modulating signal update instants closest to the intersection with w i .Equation ( 8) is defined such that positive values of m icu,d correspond to in-phase operation.
The size of m icu,d is correlated with the extension of nonlinear zones that appear in DPWM i 's transcharacteristics around D c .The in-phase discontinuities of each slope of w i contribute to its respective jitter zone heights as δ i∞u,d = ( m icu,d /2) [27].As verified in Sections IV-D and IV-E, when the in-phase operation occurs for both the slopes of w i , the joined height of the jitter zones can be estimated as Thus, it is of interest to provide a simple analytical procedure which would, for each DPWM i , predict whether an in-phase or counter-phase operation occurs, as well as the size of m icu,d around D c .

C. Analytical Calculation of the Discontinuities
To calculate m icu,d , it is necessary to find m(t).The exact analytical calculation of m(t) requires an iterative procedure, whose steps for two-level VSCs are described in [26] and [27].Since its extension to MC-VSCs brings additional complexity, in this article, an approximate procedure is used, which is based on the naturally sampled equivalent of the modulating signal, m ns (t) [27].As shown in [27], the use of the approximate procedure is justified for predicting m icu,d , since, for the high-frequency proportional-dominant controllers, its results negligibly deviate from those of the exact procedure.To obtain m ns (t), the analog equivalent of the modulating signal ripple, m r d (t), has to be found.The procedure relies on an assumption that all the control blocks can be represented in the s-domain.
For the assumed imbalance distribution (3) and the operating point (1), the converter circuit is solved for all the topological states, considering only the average value of the modulating signal (as in Fig. 5).The resulting triangular ripple of the inductor current i rip (t) is then found.Next, i rip (t) is used to solve a set of controller-related equations, which, after scaling by K , yields m r (t).Finally, an arbitrary amount of time delay Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 7. Illustration of the procedure used to obtain modulating signal ripple component, m r d (t), naturally sampled equivalent of the modulating signal m ns (t) and its resampled variant.Illustration is given at D c = (1/2), for an MC-VSC with N = 2 and the imbalance from (3).A purely proportional current controller is assumed and the relative delay is equal to τ D .t = τ D T pwm is added to obtain m r d (t).This time delay 6 can be due to the algorithm execution time, feedback filters, delays in the sensing and driver circuits, etc.
Based on m r d (t) and the operating point considered, the naturally sampled modulating signal m ns (t) is calculated relative to the first carrier [26].This waveform is then used to find an approximate version of m(t), obtained by resampling m ns (t) at assumed sampling instants.This approximation only slightly shifts the switching instants with respect to the exact calculation.The procedure described above is illustrated in Fig. 7 for an MC-VSC with N = 2, the imbalance from (3), and the purely proportional current controller.The resampled version of m ns (t) is used to calculate m icu,d , as in (8).More details about the analytical calculation of the modulating signal discontinuities can be found in [26], [27], [41], and [35], and in the MATLAB script discont_calculation.m that is submitted with this article, as supplementary material.

D. Discontinuity Graphs
This section presents discontinuity graphs that provide the value of m icu,d as a function of τ D .Note that with the above-described procedure for analytical calculation of the modulating signal discontinuities, it is sufficient to obtain the discontinuity graph only for the first carrier.Namely, by simply shifting it for the value equal to the phase shift of the considered carrier, the discontinuity graphs for all the other carriers can be obtained.The MATLAB script discont_graphs.mused to obtain the discontinuity graphs is uploaded as active content with the article, to provide more insight.
The discontinuity graphs are given for τ D ∈ [0,1], which is sufficient due to the periodicity of the switching ripple.The impact of E r on m icu,d is also illustrated.As predicted by (7), the influence of f cr is verified to be the same as that of E r .For the presentation conciseness, the results below are obtained for fixed f cr = 0.1.
Although vertical intersections also appear in the vicinity of D c , the discontinuity graphs are plotted only at D c , since, as shown below, this is sufficient to predict properties of MSMU-PS-DPWM transcharacteristics around D c .Note that with the imbalance distribution from (3), the discontinuity graphs at D c for the positive slope of w i are the same as the graphs at 1 − D c for the negative slope of w i .
In Fig. 8, the discontinuity graphs for N = 2 and D c = (1/2) are shown for various imbalances.Since for D c = (1/2) and D c = 1 − D c , the discontinuity graphs for the positive and negative slopes of w i are the same.The presented discontinuity graphs are proportional to E r , as implied by (7).Under balanced conditions, i.e., for E r = 0, the calculated discontinuities are zero, and thus, the vertical intersections are not possible in the steady-state.In addition, it is seen from Fig. 8 that the borders between the in-phase and counterphase regimes are almost independent of E r .The same is verified for f cr .Based on this, it can be inferred that for the fixed imbalance distribution, τ D defines whether the in-phase or counter-phase regime occurs, whereas the extent of the discontinuities is determined by E r and f cr .Moreover, for the value of τ D corresponding to the above-mentioned border, almost linear behavior of the modulator is achieved, regardless of E r and f cr .Another important remark from Fig. 8 is that the discontinuity graphs of DPWM 1 are equal to the inverted graphs of DPWM 2 .This is due to PS-DPWM, which causes the discontinuity graphs of adjacent carriers to feature the same shape, with the τ D -axis shifted by the imposed phase shift, i.e., (1/N ).
In Fig. 9, the discontinuity graphs for N = 3 and D c = (1/3) and the imbalance distribution from (3) are shown.For the sake of presentation, only the results for E r = 0.2 are plotted, but it is verified that as for N = 2, the values of the discontinuities are proportional to E r and f cr , while the boundaries between the in-phase and counter-phase regimes remain located at nearly constant values of τ D .From Fig. 9, it can be seen that the sum of maximum discontinuities for the positive and negative slopes of w i is the same for all the DPWMs and reduced, compared with N = 2.This is an important remark, which underlines that as N increases, the discontinuity-related nonlinear effects of MSMU-PS-DPWM in unbalanced MC-VSCs are reduced.Note that this was also verified for N > 3, but the results are not included due to space limitations.In addition, given that the discontinuity related modulator nonlinearity is more pronounced for lower values of N , the results in this article are presented for such values of N .For a very high number of cells, i.e., multisampling factors, the discontinuities and, consequently, the nonlinear effects caused by them, are almost completely suppressed, as the sampled feedback closely resembles the continuous analog signal [27].

E. Simulated Transcharacteristics
To verify the predictions of the discontinuity graphs, simulations are performed to obtain the transcharacteristics of MSMU-PS-DPWM around D c .For this purpose, MC-VSCs with the parameters from Table I are   In Fig. 10, the simulated transcharacteristics around D c = (1/2) are shown for N = 2, τ D = 0, and f cr = 0.1, considering E 1 > E 2 and E 1 < E 2 , both with E r = 0.2.The results for E r = 0 are also included to verify that MSMU-PS-DPWM is linear under balanced conditions.As predicted by the discontinuity graphs in Fig. 8, for E 1 > E 2 , the transcharacteristics of DPWM 1 and DPWM 2 exhibit reduced-gain and jitter zones, respectively, while vice versa is observed for E 1 < E 2 .Under unbalanced conditions, jittering of the detected duty cycle, caused by the LCOs, is clearly observable.In addition, the transcharacteristics of DPWM 1 and DPWM 2 , obtained for E 1 < E 2 , are, respectively, equal to those of DPWM 2 and DPWM 1 , obtained for E 1 > E 2 .Furthermore, the heights of the joined jitter zones in Fig. 10, D 3), and E r = 0.2.As predicted by the discontinuity graphs in Fig. 9, the transcharacteristics of DPWM 1 and DPWM 2 exhibit reduced-gain and jitter zones, respectively, whereas for DPWM 3 both the reduced-gain and jitter zones are present.Note that in addition to the LCOs observed around the jitter zones in the transcharacteristic of the DPWM i that features an in-phase operation, some smaller amplitude LCOs are also visible in the transcharacteristics of all other DPWMs.This is because LCOs, caused by the in-phase operation of DPWM i , are present in the system and thus also impact the operation of other DPWMs.This is an important remark that demonstrates that the in-phase operation for one carrier is sufficient to cause jittering in the overall system.Moreover, since, as mentioned in Section II-B, a counter-phase operation for one carrier is at the same time an in-phase operation for another carrier, vertical intersections in unbalanced MC-VSCs with MSMU-PS-DPWM always cause jittering.This conclusion is valid regardless of the imbalance distribution, and, as shown in Section V, the jittering effect is more pronounced for higher τ D and f cr .
To further elaborate on this, in Fig. 12 , and E 3 = 0.91E n .As expected, under balanced conditions, linear behavior of MSMU-PS-DPWM is achieved.However, in the presence of an arbitrarily chosen imbalance, the nonlinear effects are clearly visible, which shows that the nonlinearity of MSMU-PS-DPWM is present regardless of the imbalance distribution.To illustrate its detrimental impact on the performance of the MC-VSC, the reference step change is imposed, which in the presence of imbalance moves the operating point from the linear to jitter zone (as marked in Fig. 12).The time-domain input and output converter waveforms in response to this reference change are shown in Fig. 13 under balanced (E 1 = E 2 = E 3 = E n ) and in Fig. 14 under unbalanced conditions (E   waveforms obtained after removing the switching ripple (using a moving average filter over T pwm ) are also shown, for a better visualization.After the step reference change, under balanced conditions (Fig. 13), the steady-state is achieved and the responses are as expected.However, in the presence of imbalance (Fig. 14), the steady-state cannot be achieved and the LCOs, caused by the nonlinearity of MSMU-PS-DPWM, are clearly visible in the converter waveforms, which is in accordance with the corresponding transcharacteristics from Fig. 12(b).

V. EXPERIMENTAL VALIDATION
This section provides experimental validation of the previously discussed nonlinear phenomena observed in unbalanced MC-VSCs with MSMU-PS-DPWM and illustrates their influence in typical application scenarios.For dc-dc converters, the impact on the transient response and the occurrence of LCOs is examined.For dc-ac converters, the impact on the output waveform distortion is analyzed.

A. Test Setup
For the experimental measurements, a single-phase currentcontrolled laboratory prototype of the MC-VSC from Fig. 2 is realized, with the hardware and control loop parameters from Table I.The block diagram and the picture of the test setup are shown in Figs. 15 and 16.The setup consists of three main parts, denoted by three different colors in Fig. 15.Red part represents the tested MC-VSC, realized using the SiC half-bridge modules from Imperix.An inductive filter is used and a resistive load is connected in parallel with the output capacitor.Inductor current is sensed by an external sensor from Imperix, which is based on LAH 50-P from LEM.The control system, denoted by blue color in Fig. 15, is implemented on Imperix B-Box Embedded Control Module, using both the DSP and FPGA that are available on the board.The ADC and the current control are implemented on DSP.Due to the algorithm computation time, the modulating signal update is delayed by one sampling period, T s .An additional delay is added in some tests, to examine the impact of delay on the modulator nonlinearities, as analyzed in Section IV.The digital modulating signal, m s , is forwarded to the FPGA via Imperix sandbox, which serves as an interface between   Test setup used for experimental validation. 1) Power supply TDK/Lambda GEN300-17 used for the dc-dc tests, 2) SiC half-bridge modules from Imperix, 3) boom box controller, 4) laptop, 5) power supplies GW GPC-3030 used for the dc-ac tests, 6) filter inductor, output capacitor, and sensing circuits, 7) resistive load, 8) oscilloscope; power supplies, 9) EA-PSI 9750-20TDK, and 10) Keysight RP7962A used for the dc-dc tests.
12.5 MS/s rate, using the Tektronix TCP202 current probe and MS056 oscilloscope.

B. Impact of Nonlinearities in DC-DC Converters
As examples of dc-dc converters, multilevel MC-VSCs with two and three half-bridge cells are formed.The dc link of each cell is realized using one of the following power supplies: Keysight RP7962A, TDK/Lambda GEN300-17, and EA-PSI 9750-20.The nominal dc link voltage is set to E n = 120 V.The proportional-integral current controller is used where k p and k i are the proportional and integral gain, respectively.In Fig. 17 According to the presented results, an excellent match between the simulations and experiments is achieved.Moreover, the types of zones and the joined jitter zone heights that appear in Fig. 17   In the presented simulated and experimentally measured transcharacteristics, the impact of LCOs on system inability to achieve steady-state operation is seen, around the operating points where nonlinearity zones exist.This causes a stochastic jittering of the duty cycle.The degree of this jittering depends on the LCOs' magnitude and frequency and should not be misinterpreted with the height of the jitter zone, which quantifies the extent of the actuator (modulator) nonlinearity.Note that it is also experimentally verified that under balanced conditions, i.e., for E r = 0, linear transcharacteristics are obtained, but the results are not included due to space limitations.
In Figs.E r = 0.2 and E r = 0.1, respectively.An excellent match between the simulations and experiments is achieved.Moreover, the extent of the observed nonlinear effects is again scaled with E r .In Fig. 19, the effect of jittering and LCOs is illustrated in the time domain.A step reference change is imposed, so that, for E r ̸ = 0, the operating point changes from the linear to jitter zone, as marked in Fig. 18(a) and (b).The tracking errors, relative to the maximum peak-peak current ripple present under balanced conditions, are shown in Fig. 19(a) for E r ∈ {0, 0.1, 0.2}.For a better visualization, switching ripple is removed from the plotted data using a moving average filter over T pwm .As expected, with unbalanced dc links, the steady-state cannot be achieved after the step reference change and the LCOs, caused by the modulator nonlinearity, are clearly visible in the presented waveforms.On the contrary, balanced dc links yield a linear operation.This is further illustrated in Fig. 19(b)-(d) where the inductor current in response to the same reference step change is shown for E r ∈ {0, 0.1, 0.2}.In addition to the raw, unprocessed, data that are acquired by the oscilloscope and shown in gray color in Fig. 19(b)-(d), the waveforms obtained after removing the switching ripple are also shown, for a better visualization.

C. Impact of Nonlinearities in DC-AC Converters
As an example of dc-ac converter, a multilevel MC-VSC with two full-bridge cells is formed.The linear power supplies GW GPC-3030 are used as the cells' dc inputs, to avoid stability problems of the switched power supplies that were noted under unbalanced dc links and ac operation.The nominal dc link voltage is set to E n = 50 V, which was the maximum possible due to hardware limitations of the power supplies.
To investigate the impact of the previously discussed phenomena on the output waveform distortion, a sinusoidal ac reference is imposed and the proportional-resonant current controller is used where f 1 = 50 Hz is the fundamental frequency.Due to R LC load, at f 1 , the output voltage lags the inductor current for 21 • .Note that the simulations were performed with an    as in Fig. 17(a), which is expected to cause distortion in ac operation.On the other hand, since MSMU-PS-DPWM yields linear operation under balanced conditions, the deadtime is expected to be the only source of distortion in ac operation with E r = 0. To verify this, the time-domain waveforms of the inductor current and their spectra are compared in Fig. 20 for E r = 0.2 and E r = 0.For a better visualization, in Fig. 20(b) the switching ripple is removed from plotted data using an MAF over T pwm .As expected, a considerable distortion around the voltage zero crossings occurs for E r = 0.2, which is not present for E r = 0. Note that the similar effects were observed in simulations with zero deadtime, which verifies that the origin of the distortion for E r = 0.2 is the modulator nonlinearity.

VI. CONCLUSION
In this article, the discontinuity-related nonlinear effects of MSMU-PS-DPWM that arise in unbalanced MC-VSCs are analyzed.A simple analytical procedure is proposed to predict the nonlinear zones that appear in the transcharacteristic of each carrier.Their extension is verified to be proportional to the relative value of imbalance magnitude and crossover frequency, and inversely proportional to the number of cells.It is shown that due to PS-DPWM, vertical intersections in MSMU unbalanced MC-VSCs always cause LCOs.This phenomenon, which is more pronounced for higher control loop delays and bandwidths, deteriorates the performance of dc-dc and dc-ac MC-VSCs.Experimental measurements, performed on single-phase laboratory prototypes of the threeand four-level MC-VSCs, are in excellent agreement with the simulations and analytical predictions.

APPENDIX
To avoid detrimental impact of discontinuity-related nonlinear effects of MSMU-PS-DPWM that appear in unbalanced MC-VSCs, some provision has to be taken in practical applications.Since the modulator nonlinearity arises due to the switching ripple that gets sampled in presence of an imbalance between the cells, digital feedback filtering aimed at removing the ripple from the acquired feedback signal seems like a promising candidate.Though moving average filter over T pwm is known to be effective in removing the switching ripple in multisampled applications, it compromises dynamic performance improvements that increased sampling frequency offers [17], [35], [41].As an alternative, this article proposes repetitive ripple removal filter (RRR) from [36].Its z-domain transfer function is where R defines the settling time and the phase lag of the RRR [36].In this article, R = 0.125 is used, such that RRR's settling time is approximately 10T pwm and that its impact on control loop's small-signal dynamics of interest is negligible [36].
To demonstrate the effectiveness of RRR in mitigating the nonlinear effects discussed in this article, simulations were run for MC-VSC with N = 2, f cr = 0.1, τ D = (1/N ), imbalance from (3), and E r = 0.2.Simulations were organized in the same way and with the same parameters as outlined at the beginning of Section IV-E.In Fig. 21(a), modulator transcharacteristics are compared for the case without any filters in feedback (G f b (z) = 1) and with RRR (G f b (z) = G RRR (z)).As seen, RRR successfully eliminates nonlinear zones that are present when no filters are used, resulting in a completely linear behavior of MSMU-PS-DPWM, even in the presence of an imbalance.To further elaborate on this, a step reference change is imposed, so that, in the case without any filters, the operating point moves from the linear to jitter zone, as marked in Fig. 21(a).Inductor current waveforms in response to this reference change are shown in Fig. 21(b) and (c), in the case without any filters and with RRR in feedback.LCOs that are clearly observable in Fig. 21(b) are successfully eliminated by RRR, as seen in Fig. 21(c).This illustrates the effectiveness of RRR in mitigating the discontinuity-related nonlinear effects of MSMU-PS-DPWM and, consequently, in preventing their detrimental impact on the performance of unbalanced MC-VSCs.

Fig. 1 .
Fig. 1.Single-phase MC-VSC (a) multilevel and (b) interleaved topology.Each cell can be realized as a half-or full-bridge.
implemented in MATLAB/Simulink.The transcharacteristics are obtained by imposing a slow current reference sweep while saving the values of the modulating signal m s and the detected duty cycles D 1,...,N .The Simulink model sim_trch.slxand the postprocessing script plot_trch.mused to obtain simulated transcharacteristics are submitted with this article, as active content.

Fig. 13 .
Fig. 13.Simulation results for an MC-VSC with N = 3, τ D = (1/N ), f cr = 0.1, and balanced dc links: E 1 = E 2 = E 3 = E n .Input and output converter waveforms in response to the reference step change from i lin r to i jitt r (marked in Fig. 12), which in the presence of imbalance moves the operating point from the linear to jitter zone (a) cell's input voltages (b) output current (c) output (load) voltage, and (d)-(f) cell's input currents.For a better visualization, in addition to the raw waveforms [shown in gray color in (b)-(d)], the waveforms after removing switching ripple are also shown.

Fig. 14 .
Fig. 14.Simulation results for an MC-VSC with N = 3, τ D = (1/N ), f cr = 0.1, and an arbitrarily chosen imbalance distribution: E 1 = 1.23E n , E 2 = 0.86E n , and E 3 = 0.91E n .Input and output converter waveforms in response to the reference step change from i lin r to i jitt r , which moves the operating point from linear to jitter zone, as marked in Fig. 12(a) (a) cell's input voltages, (b) output current, (c) output (load) voltage, and (d)-(f) cell's input currents.For a better visualization, in addition to the raw waveforms [shown in gray color in (b)-(d)], the waveforms after removing switching ripple are also shown.
DSP and FPGA and ensures a proper synchronization.The MSMU-PS-DPWM is coded in VHDL and implemented on the FPGA, with the DPWM clock that runs at f clk = 125 MHz.The switching signals, x 1,...,N , are sent back to DSP where deadtime is realized.To obtain modulator transcharacteristics, the duty cycles D 1,...,N are detected on the FPGA, forwarded to DSP, and exported together with m s , using Imperix Cockpit.Postprocessing, denoted by yellow color in Fig. 15, is performed in MATLAB.For examining transient response and waveform distortion, the inductor current is acquired with Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

Fig. 15 .
Fig. 15.Block diagram of the test setup used to experimentally validate nonlinear effects of MSMU-PS-DPWM in unbalanced MC-VSCs.
, the transcharacteristics, obtained by imposing current reference sweep in experiments and simulations, are shown around D c = (1/2), for the MC-VSC with N = 2, imbalance distribution from (3) and different τ D , f cr , and E r .
(a), (b), and (d) correspond to those predicted by the discontinuity graphs in Fig.8.Compared with Fig.17 (a), the extensions of the nonlinear zones in Fig.17 (c) and (d) are halved, which is in agreement with(7).
18 and 19, the experimental results are shown for the MC-VSC with N = 3, f cr = 0.1, τ D = (1/N ), imbalance distribution from (4), and different E r .Comparison between the simulated and experimentally measured transcharacteristics around D c = (1/3) is shown in Fig. 18(a) and (b) for

Fig. 19 .
Fig. 19.Experimental results for the MC-VSC with N = 3, f cr = 0.1, τ D = (1/N ), imbalance distribution from (4), and E r ∈ {0, 0.1, 0.2}.(a) Relative tracking errors of the reference step change from i lin r to i jit r , which for E r ̸ = 0 moves the operating point from the linear to jitter zone, as marked in Fig. 18(a) and (b).The switching ripple is filtered out for a better visualization.The tracking errors are given relative to the maximum peak-peak current ripple present under balanced conditions.(b)-(d) Inductor current in response to the same reference step change.

Fig. 21 .
Fig. 21.Comparison of the simulation results for MC-VSC with N = 2, f cr = 0.1, τ D = (1/N ), imbalance from (3), and E r = 0.2, in case without any filters in feedback and with RRR (a) modulator transcharacteristics around D c = (1/2) and (b) inductor current in response to the reference step change for the case (b) without any filters in feedback and (c) with RRR in feedback.In case without any filters, the imposed reference step change moves the operating point from linear to jitter zone, as indicated in (a).

TABLE I HARDWARE
AND CONTROL PARAMETERS OF THE TESTED MC-VSCS distribution from (