Power-Hardware Design and Topologies of Converter-Based Grid Emulators for Wind Turbines

Power-electronic-based grid emulators (GEs) emerge as a favorable method for testing grid-code compliances of wind turbines (WTs), thanks to their full controllability and improved efficiency. To accommodate the increasing power and voltage levels of WTs, scalability becomes a critical requirement for the topologies of converter-based GEs. This article identifies first the power rating of future GEs based on the system architecture and the evolution of WTs, followed by evaluating converter topologies of GEs for high scalability. Design considerations of power semiconductor devices, step-up transformers, dc chopper, and dc capacitors are also discussed for existing and prospective GEs.


I. INTRODUCTION
W IND turbines (WTs) are undergoing a continuous increase in power rating, from a few megawatts (MWs) to 16 MW today [1].For efficient power transmission, the voltage level of the collector system in wind power plants has also risen to 66 kV and may even reach 132 kV in the future [2], [3].Driven by the rising power and voltage levels of WTs, a highly scalable grid emulator (GE) is demanded for testing grid-code compliances of WTs [2].
Generally, a power-electronic-based GE employs a backto-back (BTB) power conversion structure, which consists of an active-front-end (AFE) converter and a controlled voltage generator (CVG) [2], [4].The AFE converter and CVG are configured with multiple parallel-/series-connected power converters for scalability.A common choice is to interleave multiparalleled neutral point clamped (NPC) converters with a multiwinding transformer [5], [6], [7], where the power rating of GE is increased with the number of NPC converters.Another option is to use the single-phase transformers with a custom-built configuration [8], [9], [10], instead of the multiwinding transformer, leading to a cascaded NPC-based GE.The scalability of the NPC-based GEs is limited by the power efficiency and manufacturing process of transformers [11].
Alternatively, multilevel converters, such as the cascaded H-bridge (CHB) converter [12], [13], [14], [15], [16] and the modular multilevel converter (MMC) [17], [18], [19], [20], [21], are also used with GEs, where a standard threephase step-up transformer is adopted to further scale up the output voltage of CVG [12], [13], [17].The CHB-based CVG does not have a common dc link, and instead, the H-bridge converters are individually fed by three-phase AFE converters, which are then typically connected to the power grid through multiwinding transformers [15].However, the number of secondary windings of multiwinding transformers limits the scalability of the H-bridge cells.The BTB-MMCbased GE, on the other hand, can employ dozens of floating submodules (SMs) per arm to increase the output voltage and reduce total harmonic distortion (THD) without adding ac filters [20], [22].
The selection of power semiconductor devices and design of passive power components in these GEs exhibit unique challenges with fulfilling the testing capability requirements.During fault ride-through (FRT) tests, the GE must be able to handle fault currents, i.e., 2 p.u. fault current for type-IV WTs and 7 p.u. fault current for type-III WTs [23], [24], which necessitates oversized current ratings for power semiconductor devices.In particular, interleaved NPC-and MMC-based GEs have circulating current flows [7], [19], due to the interleaved modulation and the lack of separated dc power supply of NPC and SMs, which complicates the oversized design of power semiconductor devices.Additional transformer taps and antisaturation design of the CVG-side transformer are necessary for a GE to reproduce voltage sags and swells within 1 ms at a range of 0%-160% of the rated voltage [25], [26].This may further exacerbate the complexities of manufacturing multiwinding and custom-built single-phase transformers.
This work is licensed under a Creative Commons Attribution 4.0 License.For more information, see https://creativecommons.org/licenses/by/4.0/Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 1.Overall system diagram of power-electronic-based grid-code compliance testing system for WTs [2], [21].
The design of neutral-point (NP)/cell/SM capacitance and dc chopper is also important to avoid the over-and undervoltage of dc-link capacitors when emulating multiple consecutive grid faults [27].
This article, thus, gives a review on topologies and hardware design aspects of power components for converter-based GEs.It begins by identifying the power rating requirements for future GEs according to the architecture of grid emulation system and the evolution of WTs.Then, the GEs based on the interleaved NPC, the cascaded NPC, the CHB, and the MMC are systematically compared.The design considerations of power components to meet the testing capability requirements of GEs are discussed.Finally, insights on the hardware design aspects of prospective GEs driven by emerging trends are shared.

II. SYSTEM ARCHITECTURE AND POWER RATING
Fig. 1 depicts the overall architecture of power-electronicbased testing system for WTs [2], [21].Besides the GE, the testing system comprises a WT nacelle and a wind torque emulator, which together simulate the electrical and mechanical behavior of the WT system.The WT nacelle is equipped with a BTB converter and a generator with/without a gearbox, while the wind torque emulator consists of a motor-drive system and a shaft to reproduce the behavior of a WT rotor.This section elaborates, first, the short-circuit current capability and power levels of WTs and then outlines the power rating of future GEs and the system architecture.

A. Short-Circuit Current and Power Levels of WTs
Two types of generators are commonly used for WTs, i.e., the permanent magnet synchronous generator (PMSG) and the doubly fed induction generator (DFIG) [28], [29].The PMSG-based WTs typically have a maximum short-circuit current capacity of 2 p.u., while the DFIG-based WTs can handle an overcurrent up to 7 p.u. [23], [24], [30].
Fig. 2 depicts the power levels of typically installed and planned WTs [1], [31], [32], [33], [34].Currently, the maximum power rating of DFIG-based WTs is 7 MW, while the PMSG-based WTs with a power capacity up to 16 MW have been deployed in offshore wind power plants.The development of a 20 MW WT is also expected in the near future [28], [29].

B. Power Rating of Future GEs
IEEE 1547-2018 specifies that WTs should be capable of injecting reactive power up to 44% of their nameplate apparent power rating S rated [35], even when the steady-state active power output is at the rated level.For a WT with a rated active power of P rated , S rated must satisfy Thus, S rated should not be less than 22.3 MVA for a WT with P rated = 20 MW.A GE should have a continuous power rating of at least 20 MW/22.3MVA to accommodate the increasing power level of WTs in normal operation [19], [36].However, during FRT tests, the CVG must cover a broad range of under-and overvoltage, i.e., 0%-160% of rated voltage [26].The transient fault current at the point of common coupling (PCC) depends on the current reference and control of a WT specified by WT manufacturers, in addition to the intermediate impedance between WT and GE.Consequently, the worst scenario assumes that the WT delivers the maximum current to ride through the 160% of rated voltage [37], [38].Subsequently, the maximum power responses of PMSG-and DFIG-based WTs can be simply derived as Hence, taking the power loss into account, the short-term power capacity of a future GE should be at least 80 MVA [39].

C. Wind Torque Emulator and Power Circulation
To reproduce the low-speed dynamics of WTs, the motor-drive system should be able to generate the active power at least 20 MW at an output frequency of 2-10 Hz [6].
For energy-saving purpose, the wind torque emulator can be configured in two ways to cycle active power, i.e., dc power circulation and ac power circulation, as depicted in Fig. 1.The dc power circulation is attained through a shared dc link between the motor-drive system and the CVG of GE [40].However, for GEs without a common dc link, the ac power circulation may be used instead [12], which requires an additional AFE converter and transformer to power the motordrive system, potentially increasing the system volume and footprint.It is worth noting that the converters used within the turbine torque emulator follow the same topologies as that of GE for the scalability requirement [2], [6].
III. TOPOLOGIES OF POWER-ELECTRONIC-BASED GES Fig. 3 illustrates the categorization of topologies of powerelectronic-based GEs into three types: parallel, serial, and series-parallel.The evaluation criteria of these types of GEs are discussed, which are the multilevel output, the placement of ac filter, the complexities of manufacturing transformers, the scalability, and the voltage/current stress of power semiconductor devices to compare four types of GEs (see Table I).The actual applications for each GE are also discussed.

A. Multilevel Output and THD of PCC Voltage
Generally, GEs should follow the testing requirements on the harmonic voltage limits at the PCC, i.e., the THD (from 2nd to 50th harmonics) of the line-to-neutral PCC voltage must be below 5% [41].Currently, a more stringent requirement is posed by IEEE 1547.1-2020,i.e., the THD of PCC voltage (line-to-neutral) should be lower than 3% [42].
1) Interleaved NPC-Based GE: To enhance the power scalability with a reduced THD of the PCC voltage, using the interleaved NPC inverters based on the phase-shifted-carrier (PSC) pulsewidth modulation (PWM) is a common solution for the CVG in commercial GEs [5], [6], [7], [43].
Fig. 4(a) depicts a general single-phase CVG circuit of the interleaved NPC-based GE in Fig. 3, where V dc , V 1 ∼V Nnpc , and L f represent the dc-link voltage, ac terminal voltages, and L filter of these paralleled inverters, respectively.TR_S 1 ∼TR_S Nnpc , TR_P, and N tr denote the secondary windings, primary winding, and step-up ratio of the multiwinding CVG-side transformer, respectively.V pcc is the magnitude of line-to-neutral PCC voltage.Fig. 4(b) illustrates a single-phase equivalent Thevenin circuit of interleaved NPC inverters, where N npc and θ c1 ∼θ cNnpc are the number and phase angles of carrier signals for these inverters.Z in is the equivalent intermediate impedance between the inverter and PCC, which can be expressed as [7], [43] where Z tr is the impedance of multiwinding transformer including the winding resistance and leakage reactance.f 1 is the fundamental frequency.In Fig. 4(b), i cir is the circulating current caused by the terminal voltage difference of paralleled inverters across Z in [7], [43].According to Kirchhoff's current law (KCL), without the connected WTs, the sum of output current of each inverter should satisfy Therefore, the PCC voltage and i ciri (i = 1, 2, . . ., N npc ) flowing in each NPC inverter are given by The interleaved NPC inverters can be modeled as a controlled voltage source with the rated voltage V pcc in series with an impedance Z in /N npc [44].When terminal voltages V 1 to V npc are same, V pcc still exhibits original three-level voltage and i cir is zero.To achieve a multilevel output, it is necessary to regulate different θ c1 ∼θ cNnpc at the same instant, thus making nonzero i cir inevitable.
Fig. 4(c) and Table II show an example of PCC voltage generation and all operating states of a GE using two NPC inverters [45].As shown in highlighted area, shifting a time delay ( t) between V 1 and V 2 can create additional number of output voltage levels.Therefore, the number of line-to-neutral voltage levels N ln at the PCC can be expressed as [44] N ln = 2N npc + 1. ( Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE II OPERATING STATES OF A GE USING TWO INTERLEAVED NPC INVERTERS
According to (6), when only one V dc /2 exists among V 1 ∼V Nnpc and the rest are zero, the i ciri attains its maximum value, as follows: To achieve best harmonic voltage cancellation and minimize the THD at the PCC, the θ c1 ∼θ cNnpc of carrier signals of interleaved NPC inverters are generally shifted by 2π/N npc radians incrementally [43], [46].However, the switching frequency, i.e., the carrier frequency, of an NPC inverter is typically lower than 1 kHz and N npc is usually smaller than 4 in MW-interleaved NPC-based GEs [7], [40].This often causes the THD of the line-to-neutral PCC voltage greater than 10% [43].Although using more parallel NPC inverters is a simple solution in theory to reduce THD, it requires multiple secondary windings of the CVG-side transformer.Besides, according to (4), the parameter differences in L f and secondary windings can change the voltage levels of V pcc , which may further affect its THD.
2) Cascaded NPC-Based GE: Fig. 5 illustrates the operation principle of the cascaded NPC-based GE [8], [9], [10], [11].In the single-phase circuit, V T 1 ∼V T Nnpc/2 and θ 1 ∼θ Nnpc represent the output voltage of each single-phase transformers and the initial phase angles of output voltages for these NPC inverters, respectively.The single-phase transformers are custom-built, with each primary winding of the transformer functioning as a subtractor for output voltages of two NPC inverters, and the series-connected secondary windings summing up all inverter voltages.To create additional number of output voltage levels for V T 1 ∼V T Nnpc/2 and V pcc , it is important to regulate different θ 1 ∼θ Nnpc for each NPC inverter.To achieve this, the carrier-based phase-disposition (PD) PWM is widely used in the cascaded NPC-based GEs [8], [11].
Fig. 5(b) and Table III depict an example of single-phase output voltage generation and all operating states of a GE utilizing two cascaded NPC inverters.m_NPC1 and m_NPC2 denote the modulation references for the two NPC inverters.C1_NPC1 and C2_NPC1 are the carriers for the first NPC inverter, while C1_NPC2 and C2_NPC2 are the carriers for the second NPC inverter.Taking NPC1 as an example, the driving

TABLE III OPERATING STATES OF A GE USING TWO CASCADED NPC INVERTERS
signal S a1 in Fig. 5(a) is generated by the comparison between m_NPC1 and C1_NPC1, while S a2 is produced by comparing m_NPC1 with C2_NPC1 [45].Consequently, a five-level lineto-neutral voltage at the PCC can be achieved by combining two three-level output voltages of NPC inverters.In general, the number of line-to-neutral voltage levels N ln at the PCC of the cascaded NPC-based GE is 2N npc + 1 [8], where N npc should be an even value, i.e., 2, 4, etc.
The PD-PWM and custom-built transformers can certainly cancel the switching harmonics and reduce the THD of PCC voltage [11].In [8], it has been demonstrated that without ac filters at the CVG side, the THD of line-to-line voltage at the PCC can be reduced to 3.06% for N npc = 4 even if the switching frequency of semiconductors is below 500 Hz.This is because the number of line-to-line voltage levels N ll (i.e., N ll = 2N ln −1) can be as high as 17 [47].However, since N ln is only 9, the THD of the line-to-neutral voltage at the PCC may exceed the required limitation of 3%.Increasing the number of NPC inverters can create a higher N ln , but this may pose a challenge to the quality of PCC voltage owing to different stray parameters of multiple single-phase transformers.
3) CHB-Based GE: Fig. 6 depicts the H-bridge cell of CVG and the regenerative AFE converter for the CHB-based GE.The AFE converters are connected to the power grid via a multiwinding AFE-side transformer, as shown in Fig. 3.For the CVG, the PSC-PWM is a practical approach for achieving the multilevel output and reduce the THD of the PCC voltage [13], [14], [17], [18].In this case, N ln can be given by [45] where N H is the number of H-bridge converters per phase, which is one-third of the total number of secondary windings in the AFE-side transformer.A single commercial multiwinding transformer typically has 3-15 secondary windings [13], [14], which can offer a maximum N ln up to 11.
To reduce the THD of the PCC voltage, the phase angles of the carriers in H-bridge cells are commonly shifted by π/N H radians incrementally [48].Yet, even with an N ln up to 11, [48] has demonstrated that the THD of the line-to-neutral PCC voltage may still not meet the requirement.To achieve lower THD by increasing N ln , the CHB-based GE needs to employ multiple multiwinding transformers for integrating with more H-bridge cells [16], which can result in a large volume and footprint.
4) MMC-Based GE: Fig. 7 illustrates a medium-voltage BTB MMC-based GE [20].The half-bridge SM (HBSM) [49] and full-bridge SM (FBSM) [22], [50] are two typical SMs in commercial MMCs.The PSC-PWM is a mature modulation method for HBSM-and FBSM-based MMCs to create the multilevel output, where their N ln can be, respectively, expressed as [48], [51] N ln_HB = 2N HB + 1 (10) where N HB and N FB are the number of SMs per arm for the HBSM-and FBSM-based MMC, respectively.To reduce harmonic voltages at the PCC, the phase angles of the carriers in each arm need to be shifted by 2π/N HB [51] and π/N FB [48] for the two types of MMCs, respectively.In particular, when N HB and N FB are even, the displacement angle of carriers between the upper arm and lower arm should be set to π/N HB [52] and π/(2N FB ) [51] for HBSM-and FBSM-based MMC, respectively, to minimize the THD of PCC voltage.Nevertheless, in the absence of ac filters, the THD of lineto-neutral PCC voltage may still exceed 3% in MMC-based GEs when using fewer HBSMs (e.g., ≤6) [43], [48] or FBSMs (e.g., ≤3) [22].
5) Comparison: According to Table I, when N npc = N H = N HB = N FB /2, the interleaved/cascaded NPC-, CHB-, and MMC-based GEs can produce similar multilevel output voltage and THD of PCC voltage.However, increasing N npc to meet the required THD in the NPC-based GEs is limited by the manufacturing process of the CVG-side transformers.The maximum achievable N H in the CHB-based GE with a single AFE-side transformer is constrained by its secondary windings.In contrast, the CHB-based GE with multiple AFE-side transformers and the MMC-based GE can offer more flexibility to achieve higher number of output voltage levels and to minimize THD.

B. AC Filter and Transformer at CVG Side 1) Interleaved NPC-Based GE:
To fulfill the THD requirement, the ac filter is necessary, which may be installed either at the output side of each NPC inverter or at the medium-voltage PCC side.However, both approaches can cause a bulky volume and large footprint.To address this issue, the RC filter is typically installed in the tertiary winding with a lower voltage rating of the multiwinding transformer for interleaved NPCbased GEs, as shown in Fig. 3 [6], [7], [53].Thanks to the leakage inductance of the transformer, an equivalent RLC filter Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
is formed at the PCC, where the damping R is used to attenuate the LC resonance peak [7].
2) Cascaded NPC-Based GE: Even if N npc > 4, the ac filter would still be necessary to mitigate the impact of differences of single-phase transformers on the THD of PCC voltage [39].To avoid a bulky filter bank in cabinets of NPC inverters, the ac filter can be installed at the PCC side [10], [54].In this case, the leakage inductance of single-phase transformers is equivalent as an L filter, while the ac filter generally uses the RC filter [54].
3) CHB-Based GE: The standard step-up transformer can be utilized at the CVG side of the CHB-based GE [12], [13].
In cases of a single multiwinding transformer at the AFE side, an LC [13] or RLC filter [55] is usually used at the primary (lower-voltage) side of the step-up transformer.Additionally, considering the leakage inductance of the transformer, an equivalent LCL filter or LCL filter with damping R can be seen from the PCC.For the GE using multiple AFE-side transformers, increasing the H-bridge cells may achieve the THD requirement without an ac filter.
4) MMC-Based GE: The arm inductors of MMC are equivalent as the L filters at the ac side.Thus, differing from the CHB-based GE, the C or RC filter should be placed at the primary side of the standard two-winding transformer for the MMC-based GE with fewer SMs [17], [43].
Besides, increasing the number of SMs can remove the additional ac filter, which is able to scale up the inverter output voltage, reducing the ratio and power loss of the CVG-side transformer.

5) Comparison:
The ac filter in the cascaded NPC-based GE experiences a higher terminal voltage as the PCC voltage increases, resulting in a larger volume and footprint compared to the other three GEs.Using ac filters in the CHB-and MMC-based GEs can facilitate their scalability, as the filterless option requires a minimum number of the output voltage levels, and consequently, H-bridge cells and SMs.
Besides, compared to the multiwinding transformer, the custom-built single-phase transformer can achieve the same PCC voltage using a lower step-up ratio N tr .However, the multiwinding and custom-built single-phase transformers bring more manufacturing complexities than the standard transformer.For instance, multiple secondary or primary windings along the core limbs may drive a highly unequal stray inductance for different connected converters [14].Consequently, the interleaved NPC-based GE is commonly used to test WTs lower than 33 kV [6], while the cascaded NPC-and CHB-based GEs can be employed in 33-66 kV applications [13], [39].The MMC-based GE shows more advantages at higher voltages, i.e., 66-132 kV [19].

C. Number, Voltage Stress, and Current Stress of Power
Semiconductor Devices 1) Interleaved NPC-Based GE: It is assumed that the antiparallel diodes are integrated into the power switches in Fig. 4(a).Considering the NP diodes in each phase, the interleaved NPC-based CVG consists of 3 × 6N npc power semiconductor devices that must withstand V dc /2.According to (8) and Fig. 4(a), the magnitude of current I sw flowing through these power semiconductor devices can be given by where I pcc is the magnitude of phase current flowing in the PCC.
2) Cascaded NPC-Based GE: Figs. 3 and 5 show that the cascaded NPC-based CVG has 3 × 6N npc power semiconductor devices with the voltage stress of V dc /2.The separate design of the custom-built single-phase transformer eliminates the circulating current between NPC inverters [11].Consequently, I sw is expressed as 3) CHB-Based GE: Fig. 6 shows that there are 3 × 4N H and 3 × 6N H semiconductor devices in the CVG and AFE, respectively.Their voltage stress is the cell capacitor voltage V cell [13], [14].Each AFE converter is equivalent to a controlled dc voltage source, which can eliminate the circulating current flowing between the H-bridge arms [13].Thus, I sw is also I pcc N tr .
4) MMC-Based GE: Fig. 7(b) shows that a CVG/AFE of the HBSM-and FBSM-based MMCs consists of 6 × 2N HB and 6 × 4N FB power semiconductor devices, respectively.For both HBSM and FBSM, the semiconductors must be able to withstand the voltage V sm of SM capacitors.Besides, the upper and lower arm currents of MMC can be expressed as [20] i u j = i cir j + i pcc j N tr 2 (14) where i u j and i l j are upper and lower arm currents per phase (j = a, b, c).i pcc j represents the ac current flowing in the PCC.i cir j is the circulating current, including dc and ac components.The dc circulating current i cirdc is used for the active power transmission, while the ac circulating current i cirac (i.e., even order) is introduced by the voltage fluctuations of floating SM capacitors [56].Thus, the current stress of the semiconductors in MMC is expressed as where I cir is magnitude of the circulating current.Particularly, i cirdc is one-third of the dc-link current, and i cirac can be suppressed by the internal control of MMC during normal steady-state operation [17], [20].In this case, I sw can be simplified as

5) Comparison:
The number and voltage stress of power semiconductor devices of the cascaded NPC-based GE are the same as those in the interleaved NPC-based GE.However, it is important to design the intermediate impedance Z in , which includes L f and the leakage impedance of the multiwinding transformer, to mitigate circulating current in the interleaved Fig. 8. Commercial applications of interleaved NPC-based GEs.(a) GE installed at RWTH Aachen University (Aachen), Germany [6], [7], [57].(b) GE installed at Lindø Offshore Renewables Center (LORC), Denmark [53].
NPC-based GE [7].Otherwise, its I sw may be higher than that of the cascaded NPC-based GE, causing more power loss.
Additionally, the voltage stress of power semiconductor devices is similar in the CHB-and MMC-based GE [13], [22], [43].However, to achieve the same multilevel output, the CHB-based GE will require more power semiconductor devices, as shown in Table I.Generally, V dc is greater than V pcc /N tr in (17), indicating that the steady-state I sw in the MMC-based GE is lower than that in the CHB-based GE [48].

D. Actual Applications
Table IV lists the actual applications of different converter topologies for GEs, along with their system specifications.Figs.8-14 depict the circuit diagrams of existing converterbased GEs.
Fig. 8 shows two interleaved NPC-based GEs in practice [5], [6], [7], [53].In addition to increasing the number of paralleled NPCs, employing NPCs with larger current ratings can also enhance the short-term power capacity of GEs.
Fig. 9 depicts two commercial cascaded NPC-based GEs [8], [9], [10], [11].To be able to test WTs with higher active power capacity, increasing the number of NPC inverters in the AFE is a practical solution.To accommodate the increasing power and voltage levels of WTs, Fig. 10 illustrates a GE rating at 20 MVA with a short-term power of 80 MVA, which is under development [39].It utilizes three single-phase custom-built transformers to sum up the output voltages of eight inverters, resulting in a PCC voltage up to 66 kV.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.MVA CHB-based GE currently developed by École Polytechnique Fédérale de Lausanne (EPFL), Switzerland [14].

TABLE IV ACTUAL APPLICATIONS OF MEDIUM-VOLTAGE MEGAWATT GES
Fig. 14 shows a multiparalleled CHB-based GE for a higher power rating up to 15 MVA [12].It contains two groups of power conversion modules, each consisting of four paralleled CHBs and two transformers.Fig. 14(b) depicts the single CHB topology, which employs four multiwinding transformers and 12 H-bridge cells.Consequently, increasing the number of power conversion modules is flexible to upscale the power rating of GE.
A. Power Semiconductor Devices of CVG 1) Selecting Current Ratings: The power semiconductor devices of CVG should be able to withstand the continuous overcurrent injected by WTs during each FRT test.Typically, the continuous fault current for the PMSG-based WT is commonly limited within 1.5 p.u. [59].By contrast, the fault current of the DFIG-based WT depends on the current limitation of BTB converters and the reactance of the DFIG.It can reach up to 7 p.u. and usually recover to 1-3 p.u. within 100 ms [23].Thus, the maximum root-mean-square (rms) For the cascaded NPC-and CHB-based GEs, there is no circurrent, and the power semiconductor devices should be rated for at least fc N tr .Additionally, the circulating current flows the interleaved NPC-based GE, which is dependent on the intermediate impedance Z in and the fluctuations of dc-link voltage during FRT tests.Thus, the minimum current rating I cr of power semiconductor devices for interleaved NPCs should be given by With respect to the MMC-based GE, the circulating current mainly contains the dc component during the continuous fault process, which represents the active power transmission [20].Since the WT is required to inject the reactive current during emulated voltage sags and swells, the active current and circulating current will be lower than their normal values.According to (17), the power semiconductor devices should be rated at least 2) Types of Power Semiconductor Devices and Overcurrent Capability: The duration of the maximum transient fault current injected by the PMSG-/DFIG-based WTs, i.e., 2 p.u./7 p.u., is less than 20 ms in a single fault [23].However, during the emulation of 15 consecutive faults, the GE is required to reproduce six severe faults with voltage magnitude less than 50% [27], [60].As a result, the GE should be capable of continuously operating at the maximum PCC current I fm within 120 ms.I fm is given by Besides the NP diodes of NPC-based GEs, Table V illustrates three types of switching power semiconductor devices widely used in MW GEs, such as the press-pack insulated gate bipolar transistor (IGBT) [6], [40], [61], the press-pack integrated gate commutated thyristor (IGCT) [8], [11], [62], and the common IGBT [12], [13].
Owing to the high reliability of press-pack technology, the commercial NPC-based GEs based on press-pack IGBT and IGCT can continuously operate at I fm for 200 ms [7], [61] and even for 2 s [63], respectively.However, when the current flowing through the devices exceeds their current rating, the maximum duration for common IGBTs is much shorter, e.g., 1 ms [43].Thus, extra attention should be given to the oversized design for CHB-and MMC-based GEs, indicating changing power semiconductor devices or increasing current ratings.
In particular, for the MMC-based GE, a fundamentalfrequency circulating current is commonly required to be injected to balance the SM capacitor voltage between upper and lower arms during the emulation of transient faults [18], [20].This further increases the current flowing through the IGBTs and highlights the importance of oversized design.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.3) Design Examples: Similar to the design target of the GE at the National Renewable Energy Laboratory (NREL) in the United States, it is assumed that four types of GEs need to test a 6.15-MW DFIG-based WT and a 6.15-MW PMSGbased WT at the same line-to-line PCC voltage V pccll , e.g., 13.2 kV [63].I fc in (18) and I fm in (21) can be, respectively, rewritten as Regarding the cascaded NPC-based GE with N npc = 4, the output line-to-line voltage of each NPC inverter is typically 3.3 kV, which leads to the turns ratio N tr = 1 for the custombuilt single-phase transformers.Consequently, the current rating I cr and maximum current I mc of power semiconductor devices in the CVG-side NPC inverters must be larger than I fc and I fm , respectively.Besides, the power rating of the AFE-side NPC inverter should exceed 6.15 MW.To ensure high scalability of the GE, the NPC inverters on both AFE and CVG sides are typically identical, and I cr should satisfy In the commercial ACS6000-series setups, ACS 6107 using IGCT devices with I cr = 1300 A and I mc = 2700 A can be selected for the cascaded NPC-based GE [62], which is actually implemented in the GE at NREL [8].However, the current largest 7-MW PMSG-based WTs cannot be tested by this setup, which is currently under upgrading at NREL.
With respect to the interleaved NPC-based GE, the circulating current is generally mitigated below half of normal operating current through designing Z in to prevent high current stress for the power semiconductor devices [7], [53], [57].According to (19), I cr and I mc should, respectively, satisfy The commercial MV7000-series setups, featuring presspack IGBTs, are commonly used for the interleaved NPC-based GEs [40], [57].When the NPC inverter is rating at 3.3 kV output, the turns ratio of the multiwinding step-up transformer is N tr = 4 to realize V pccll = 13.8 kV.Considering the limitation of windings of the step-up transformer, if N npc = 3, MV7308 with I cr = 2100 A and I mc = 4200 A [61] can be selected to meet the requirements in (25) and (26).
For the CHB-based GE, the current rating I cr and maximum current I mc of power semiconductor devices must be greater than I fc N tr and I fm N tr , respectively.Typically, I mc is twice of I cr in common IGBTs, and their maximum operating time at I mc is 1 ms [64].Due to I fm /I fc > 2, the selection of common IGBTs for the CHB-based GE relies on the maximum current I mc .Consequently, an oversized design of a common IGBT is recommended, such as I mc = (1.5∼2)Ifm N tr and I cr = 0.5I mc [65].
Regarding the MMC-based GE, I mc is dependent on both the transient circulating current and the maximum PCC current I fm .In general, the maximum circulating current can be up to two times the normal value I cir during transient events [21], [66].If common IGBTs are used in the MMCbased GE, according to (20), I mc should be expressed as B. CVG-Side Transformer 1) Additional Taps for Overvoltage Emulation: A practical method for emulating the grid overvoltage is to use additional tap changers in the secondary windings of the CVG-side transformer [11], [12].For instance, the cascaded NPC-based GE implemented at the Fraunhofer Institute for Wind Energy Systems (IWES) in Germany employs custom-built singlephase transformers with additional three taps.These taps are rated at 13, 26, and 46.8 kV, allowing the system to achieve a voltage level up to 30% higher than the rated voltage [11], [67].To prevent transformer saturation during tap changes, the taps should be switched while the transformer is deenergized [9], [12].Subsequently, the emulation of voltage swells can be achieved by regulating the modulation index of the converter-based GE.
2) Antisaturation of Transformer: Fig. 16 illustrates the mechanism of transformer saturation, where v 1 , i 1 , R 1 , L 1 , v 2 , i 2 , R 2 , and L 2 are the terminal voltage, winding current, leakage resistance, and leakage inductance at the primary and secondary sides, respectively.R m , L m , i m , and λ m denote the core-loss resistance, magnetizing inductance, magnetiz-ing current, and magnetizing flux, respectively.According to Kirchhoff's voltage law (KVL), without connecting WTs, the primary side of transformer should satisfy where V 1 , ω 1 , and α are the magnitude, angular frequency, and initial phase angle of primary-side voltage.
It is assumed that the residual flux is λ r before the startup of the GE, by solving (28), λ m after the transformer energization can be derived as [68] When α = 0 and t = π/ω 1 , λ m has a maximum magnitude λ p = 2λ rated + λ r .Since the saturation flux λ s of transformer is typically in the range of (1.15∼1.4)λrated [69], λ m > λ s can lead to the inrush current around two to ten times of the rated current [70], which may trip the GE or even damage the power components.Depending on the ratio of R 1 /(L 1 + L m ), the natural decaying response of the dc flux and inrush current may take 20-90 s [71].To prevent the transformer saturation during the startup process, selecting a proper α (e.g., α = π/2) along with a slow ramp of the primary-side voltage is a common approach for GEs [8], [72].
When emulating a voltage sag with a rapid recovery within the required 1 ms [8], [25], the uncertain α and a high rate of change of voltage recovery (i.e., dv/dt) may cause transformer saturation [73], [74].In this case, considering that leakage flux, the total flux λ j (j = a, b, c) at the primary side of transformer can be expressed as [73] λ j (t) = λ j (0) where λ j (0), λ j,ac , and λ j,dc are the initial value, ac component, and dc component of λ j , respectively.v j and v j , sag are the primary-side voltage of transformer during normal operation and voltage sag, respectively.t sag and t rec are the time instants of emulated voltage sag and fault recovery.
Consequently, the dc deviation of magnetizing flux λ j,dc may lead to transformer saturation, which depends on the types of voltage sags, sag depth, sag instant, and fault recovery instant.To alleviate the saturation effect from the power hardware perspective, the magnetic cores and coil windings of the GE transformer should be intentionally designed.According to (29), one simple solution is to increase the leakage inductance in the magnetic core, thereby reducing λ rated .This can be accomplished by introducing a larger realistic air gap or a virtual air gap through an auxiliary dc source [75].However, this approach may lead to increased power loss or a larger volume of the transformer, which may be impractical.Another straightforward solution is to increase λ s for a higher flux boundary of transformer saturation.The expression for λ s can be given by [76] where µ 0 is the permeability of air and µ r max is the maximum permeability of magnetic materials.K T is a coefficient related to the temperature of magnetic core.N 1 and I 1 are the number of turns and current of primary winding, respectively.l e is the height of the coil winding, while A e is the cross-sectional area of the primary winding.
A e is directly proportional to the area of magnetic core and is highly dependent on the coil winding distribution [77].Although selecting a higher N 1 with a larger magnetic core and reducing l e can increase λ s , it inevitably increases the volume, footprint, and cost of transformer.Alternatively, altering the distribution of coil windings to maximize A e is suggested in [76] and [77].For example, in the CHB-based GE system at Clemson University, by selecting the limb configuration and the cross-sectional area of primary windings, a bank of three single-phase step-up transformers with λ s = 1.45λ rated has been employed [12], [65].

C. DC-Link Chopper and NP/Cell/SM Capacitors
During severe voltage sags and swells in the power grid, the WT is required to inject maximum reactive current within 20 ms [78].Absorbing such current tends to cause the over-/undervoltage of the dc link and NP/cell/SM capacitors of GEs, especially when emulating multiple consecutive grid faults [9], [14], [20].To address these issues, adding a dc chopper and deliberately designing NP/cell/SM capacitance are needed.
1) Types of DC-Link Choppers: Fig. 17 depicts a commonly used dc chopper in a cascaded NPC-based GE at NREL, which consists of IGCTs, resistors, and capacitors [9].Fig. 18 shows a modularly designed dc-link chopper that comprises series-connected SMs, which provides a viable option for the MMC-based GE [79].For the CHB-based GE, there is lack of a common dc link.Installing a chopper in each converter cell can increase its volume and footprint.
2) Designing NP/Cell/SM Capacitance: Besides the voltage-ripple and energy storage requirements [80], [81], the transient over-/undervoltage in the GE should be also  considered in the design of NP/SM/cell capacitance.Fig. 19 shows a controller-hardware-in-the-loop (CHIL) experimental result of the MMC-based GE with four FBSMs per arm during an LVRT test [20].V cu_av and V cl_av represent the averaged upper-and lower-arm SM capacitor voltages, respectively.i o_WT is the output current of a WT.Due to the fault current injected by WT, the large ripple and transient variation simultaneously occur in V cu_av and V cl_av .
In [20], an average SM capacitor model for the MMC-based GE with FBSMs has been established when emulating the three-phase balanced faults.The relationship between SM capacitance and the maximum/minimum transient capacitor voltage can be expressed as where V c and C sm are the rated voltage and capacitance of SM capacitor.I omax is the maximum current injected by the WT.
The required operating range of SM capacitor voltage is commonly 60%-120% of V c [20].Thus, the SM capacitance can be derived as Transient variations of the NP/cell capacitor voltages also occur in the NPC-/CHB-based GEs during FRT tests [9], [14].However, the analytical maximum and minimum capacitor voltages have not yet been reported in NPC-/CHB-based GEs.

D. Switchgear
Fig. 20 illustrates a switchgear configuration of a GE system, which is used to interconnect with the GE, power grid, and WT system.The switchgear is used to switch the system between operating scenarios, which are: 1) the WT is directly connected to the power grid and 2) the WT is connected to the power grid via the GE.
When the output voltage of GE differs from the power grid, switchgear should be able to separate two different voltage levels [82].Thus, the highlighted breakers and contactors of Fig. 20 should exhibit double insulation behavior [53], [82].One common approach to achieve this is by increasing the current rating of the single busbar in GE installations.For instance, at the Lindø Offshore Renewables Center (LORC) in Denmark, a breaker and contactor with a rating of 1250 A/40.5 kV is utilized to separate the public grid from the GE output, whereas other regular breakers and contactors are rated at 630 A/33 kV [53].
V. EMERGING TRENDS Following the comparisons of converter topologies and the power-hardware design considerations of current GEs, this section explores two emerging trends of hardware design aspects for the future converter-based GEs.

A. High-Voltage Grid Emulation
As the power rating of single offshore WT increases, the use of transmission cables with larger wire diameter becomes necessary to accommodate the current PCC voltage of 66 kV.However, this poses challenges for the array design of offshore wind farms [2].Consequently, the PCC voltage of next-generation WTs tends to be higher, potentially reaching 132 kV [3].
Fig. 21 shows a potential GE based on multiparalleled MMCs for testing future WTs [83].Using the standard two-winding transformer with each MMC is important to prevent the circulating current between the paralleled MMCs and to ensure the isolation between GE and WTs.A commercial medium-voltage MMC typically uses 5-20 floating SMs per arm to achieve a 3.3-13.8kV output voltage [49], [50].Increasing the number of SMs and using power semiconductor devices with higher current rating in a single MMC can realize its power rating up to 70 MVA [49].

B. Three-Phase Four-Wire System With Single-Phase
Step-Up Transformers Recently, the power grid has been experiencing a growing penetration of renewable energy resources, energy storage systems, power-to-x systems, etc.However, when this hybrid energy system is integrated into a single PCC, their dynamic interactions may lead to system instability, despite each individual system meeting the grid-code requirements [63].It is therefore important for a GE to perform the dynamic interaction test of the hybrid energy system.
The FGW TR3 specifies that the zero-sequence voltage emulation of a GE is unnecessary for the WT testing, owing to the typical use of delta ( )-star (Y) transformer with WTs [30], [58].However, for a hybrid energy system testing, a GE should employ the three-phase four-wire connection at the PCC to provide a path for zero-sequence components [15].In addition, the CVG-side transformer of the GE must be able to transmit the zero-sequence components while maintaining normal magnetizing current.As a result, it is common practice to employ three single-phase transformers in commercial GEs [9], [12].

VI. CONCLUSION
This article provides a comprehensive review on the power hardware design of MW power-electronic-based grid emulation system, with a special attention to power converter topologies and design considerations for power components.Three categories of GEs in terms of system configurations are discussed, which point out that the GE technology is evolving toward high scalability and filter-less design for versatile testing of WTs.The interleaved/cascaded NPC-, CHB-, and MMC-based GEs have been compared, and the MMC-based GE is identified as a promising solution for future 15+ MW WTs.Design considerations of power components in GEs have also been presented, such as the oversized design of power Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
semiconductor devices, the choice of dc-link choppers, the antisaturation design of transformers, and the double insulation of switchgear.Finally, design aspects of power hardware are discussed for two prospective GEs, i.e., the multiparallel MMC-based GE and the three-phase four-wire GE.

Fig. 4 .
Fig. 4. Operating principle of interleaved NPC inverters.(a) Single-phase interleaved NPC inverter.(b) Single-phase equivalent circuit.(c) Example of single-phase PCC voltage generation of a GE using two NPC inverters.

Fig. 5 .
Fig. 5. Operation principle of the cascaded NPC-based GE.(a) Single-phase cascaded NPC inverter.(b) Example of single-phase PCC voltage generation of the GE using two NPC inverters.

Fig. 20 .
Fig.20.Grid emulation system with a switchgear for the separation between emulated grid and power grid[53].

TABLE I COMPARISON
OF MEDIUM-VOLTAGE MEGAWATT GES

TABLE V SWITCHING
POWER SEMICONDUCTOR DEVICES FOR MEGAWATT GES