A 99.74% Efficient Capacitor-Charging Converter Using Partial Power Processing for Electrocalorics

This work combines a 99.2% efficient gallium nitride (GaN)-based low-voltage fast-switching half-bridge converter with an Si-based high-voltage slow-switching and almost lossless switched capacitor multiplexer using a partial power processing approach to a six-level prototype with 99.74% efficiency. A loss breakdown shows how the ideal partial power processing efficiency is theoretically increased to 99.84% by using four additional voltage levels but then reduced to the measured efficiency by the additional static and dynamic losses of the multiplexer. For electrocaloric heat pumps, an emerging technology for cooling and heating applications with zero global warming potential, such high charging efficiencies enable a high heat-pump system coefficient of performance (COP). Based on available data of electrocaloric lead magnesium niobate (PMN)-based samples and a first-principle and best-case analysis for Carnot-like cycles, it is predicted that the 99.74% electrical charging efficiency in combination with the electrocaloric material data enables to surpass 50% of the thermal Carnot limit (for cooling with a heat pump). Ultrahigh efficiency of power converters, thus, paves the way toward future electrocaloric heat pumps of competitive system performance.

. Simplified illustration of electrocaloric heat-pump system components with efficient power electronics as charging circuit. The electrical input power (EL) is used to pump thermal power (TH). The different colors of the electrocaloric dielectric are a simplified visualization of the phases of thermodynamic cycles, whereas, in fact, the entire dielectric has a uniform but time-varying temperature. The heat source and sink are thermally connected to the electrocaloric material separately in two phases of the thermal cycle by external thermal switches (not shown, see Fig. 2). same time. The electrocaloric effect [2], [3] is an almost fully reversible temperature change in electrocaloric materials [4], [5], often low-loss dielectric as part of ceramic multilayer capacitors [6], [7], [8], [9], caused by the change of electrical field. Electrocaloric heat pumps are an emerging power electronics application since high capacitor charging efficiencies are required to achieve high heat pump performance. The achievable material efficiency could theoretically even outperform the limited coefficient of performance (COP) of today's vapor compression heat pumps [10], which still is well below the Carnot limit [11].
Research and development of such solid-state heat pumps are actions toward the sustainable development goals (SDGs) defined by the United States in 2015 [12], including "SDG 7-Affordable and Clean Energy." According to a recent report on the future of heat pumps by the International Energy Agency (IEA), more research on nontraditional solid-state heat-pump technologies is needed for more efficient and cost-effective heating [13] (and cooling).
As described in [10], conventional heat pumps are a mature technology but require an electrically driven mechanical compressor, which leads to acoustic noise, and also require refrigerant fluids, which often are very harmful to the environment. Furthermore, the COP is still well below the theoretical limit, which increases the energy consumption and, thus, cost from increased electrical energy consumption. Electrocaloric heat pumps, on the other hand, are a promising alternative solidstate technology since they can be realized in a silent system  During one phase, heat is absorbed from the cold side, while the capacitor is discharged. During another phase, heat is dumped to the hot side, while the capacitor is charged. without mechanical parts (requiring no compressor, an electrical field in dielectrics is the driving force), without harmful refrigerants (the electrocaloric material itself can be used for heat transfer), and even with higher performance (since some known electrocaloric materials have a material performance limit well above that of conventional refrigerants). Fig. 1 shows the key components of a simplified electrocaloric heat pump: The electrocaloric material is the dielectric of a capacitor with electrodes such that an externally supplied voltage changes the electric field in the dielectric, which then causes the electrocaloric effect. Continuous charging and discharging of the capacitor change the temperature of the material almost fully reversible. This dc-ac operation has an alternating output voltage component (ac) with superimposed dc component such that the load/output voltage is typically unipolar, in contrast to, for example, motor drive inverters where the ac component is bipolar. Additional thermal switches (not shown) alternately connect the electrocaloric component with a cold and hot side, synchronized to the electrical voltage, such that a heat-pump system is formed. Fig. 2 shows one electrocaloric multilayer capacitor in two exemplary isothermal phases of a thermodynamic cycle. A more detailed analysis is found, for example, in [15] and an actual electrocaloric heat-pump demonstration using a dc-dc power converter approach in [29]. During one phase, heat is absorbed from the cold side through a thermal connection to the electrocaloric capacitor, while the voltage (field) is decreased. During another phase, heat is dumped to the hot side through a different thermal connection, while the voltage (field) is increased. Typical electrocaloric ceramics have a very low dissipation factor but high permittivity. In this work, lead magnesium niobate (PMN), an electrocaloric ceramic, is an exemplary considered material since it is a known promising high-performance material for electrocaloric applications [14] and has low electrical losses (dissipation factor DF well below 0.1%). A PMN sample was prepared and characterized by Moench et al. [15], and available material data are used later in this work. Other known electrocaloric materials, such as polymers [16], [17], [18], are out of the scope of this article but will also benefit from this work's high charging efficiency in heat-pump systems.
The recoverable part of the stored energy in the electrocaloric capacitor can be recycled by an external charge recovery circuit [14], [15], [19], [20], [21] such that almost all stored energy is reused for cyclic charging and discharging operation. High electrocaloric materials' energy efficiency has also been demonstrated in lead scandium tantalate (PST) [22] and achieved already a 13 K high-temperature span using an electrocaloric regenerator [23]. In addition to heat-pump cooling and heating applications, chip-scale cooling has been demonstrated [24], cooling of batteries, seats other parts of electric vehicles discussed in [25], and electrocaloric energy harvesting was demonstrated [26]. Electrocalorics might be combined with other field effects, such as in multicaloric materials [27].
However, even though electrocaloric materials with high material performance exist today, the (heat pump) system performance in published demonstrators is significantly lower because ultraefficient charging circuits have not yet been presented. To provide the alternating voltage, an external power conversion circuit is required, which adds additional electrical system losses. State-of-the-art charging circuits for electrocaloric capacitive loads were previously demonstrated with up to 80% efficiency using resonant circuits [19], [20] and recently significantly improved by the authors to around 99.2% by a switched mode power converter approach [15], [28], which then was also applied to an electrocaloric heatpump prototype [29]. However, the associated 0.8% loss still dominated the material dissipation factor, which is below 0.1% for the PMN material. Due to this high additional external charging loss, the achievable relative heat-pump system COP (COP R,SYS = 28.6% estimated in [15] for a Carnot-like cycle without temperature regeneration) stayed significantly below the theoretically very high material limit (87.4%) when considering only the material losses but assuming an ideal lossless charging circuit. Fig. 3 shows the previously presented 99.2% efficient charging circuit [15], and typical switching and charging/discharging waveforms using a hysteretic current controller from [28] to realize constant positive and negative average charging currents. As indicated in Fig. 3, an offset voltage V C,0 for the load is externally provided, which allows limiting the dc-link input voltage of the converter to a minimum value V dc = V . This optional offset voltage was not shown in the simplified Fig. 1 for more clarity. The operation with nonzero positive offset is useful to improve the COP of electrocaloric materials, as described in [15] and [19], to avoid the high-permittivity region around low capacitor voltages. By changing the polarity of the offset voltage, it is also possible to realize bipolar load voltage operation, for example, between ±( V MAX /2), which might be useful for other capacitive load applications. Furthermore, unsymmetrical operation with reverse offset voltage is also possible, which allows to enhance the electrocaloric effect by a recently discovered polarization rotation [30]. Alternatively, the dc-link voltage of the converter could be increased by V C,0 and the offset voltage provided by the converter itself; then, the effective efficiency is reduced since part of the input voltage range would be unused. This circuit topology previously used to drive electrocaloric loads was a conventional half-bridge topology with two N = 2 voltage levels.

A. Problem
Achieving over 50% of the Carnot limit with an electrocaloric heat-pump system is a milestone currently being worked toward in research since it would imply a cooling performance competitive with today's vapor compression systems [31]. To achieve such high thermal performance, the external electrical charging loss has to be minimized. For example, for the PMN material used in this work, a charging efficiency over 99.71% is required for Carnot-like cycles without temperature regeneration [15].
Previously published electrocaloric capacitor-charging circuits, thus, have still too low efficiencies. Compared to the 99.2% efficient converter from [15], the required 99.71% charging efficiency means a further need for a 2.8× loss reduction, which seems technically challenging based on the simple two-level half-bridge circuit with today's available power semiconductor technologies.

B. Approach
This work enhances the efficiency of an already highly efficient (99.2%) gallium nitride (GaN)-based power converter (as in [15]) by a partial power processing approach using a silicon (Si)-based slow-switching switched capacitor multiplexer to increase the output voltage range, which effectively allows a significant efficiency improvement. The topology increases the conventional two-level half-bridge to a multilevel (here, six-level, N = 6) GaN/Si-hybrid converter.
Measurements demonstrate 99.74% capacitive-load charging efficiency, which paves the way toward 50% best-case system COP of electrocaloric heat pumps based on existing electrocaloric PMN material.
This work's approach should be considered a general approach to improve a given power converter efficiency on the system level for cyclic capacitor charging/discharging (including electrocaloric heat-pump applications) by partial power processing. It should be mentioned that the target application of this work is with a capacitive (electrocaloric) load, where it might be easier to realize a partial power processing topology compared to resistive load applications. This work uses switched and self-biased buffer capacitors in series to the load, which might be unfeasible to directly adapt to resistive (or inductive-resistive) load applications.
In the literature, peak efficiencies of around 99.7% [32], close to the fundamental efficiency limit of half-bridge power converters [33], were also achieved in multi-kW high-voltage converters using conventional half-bridges; however, these results are not directly comparable and applicable to this work's application since, on the one hand, this work requires a much lower power class (charging power of several watts for small prototypes instead of multi-kW). On the other hand, high efficiencies with half-bridges are often presented either in power-factor-correction (PFC) circuits or for relaxed input-tooutput voltage conversion ratios. In [34], ultrahigh-efficiency converters are discussed, and efficiencies beyond 99.8% are reported in the best case, namely, if the output voltage is close to the input voltage. For reduced output voltages (half or below half of the input voltage), the reported efficiency in [34] dropped below 99.7% for a ratio of 0.5. The peak efficiency of 99.8% in [32] is reported at an output-to-input voltage ratio of 0.75 and dropped below 99.7% for ratios below 0.67. Thus, for comparison of ultrahigh-efficiency converters, a comparable input-to-output voltage should be used. In [35], it was, for example, shown that the absolute measured power loss of a half-bridge for constant output current stayed almost constant, whereas the output power increases linearly from zero (at zero output voltage) to a maximum (if the output voltage is close to the input voltage). Thus, the efficiency, which is one minus the ratio of power loss to the output power, significantly depends on the input-to-output voltage ratio. For nonisolated power converters, an output voltage to an input voltage ratio of 0.5 is a typical representative condition. The cyclic capacitor charging application in this work is the worst case for the converter since the average input-to-output voltage ratio of the converter is 50% (in contrast to up to 71% for PFCs or even higher in the case of static dc-dc conversion with relaxed step-down ratios where the static output voltage is selected close to the input voltage to maximize the absolute power transfer, which increases the efficiency). Another approach known from the literature is based on a flying capacitor multilevel inverter [36]; however, as the name suggests, the buffer capacitors are not referenced to a common potential, and also in the flying capacitor multilevel inverter, all switches are partly used in fast-switching operation. This work's approach requires only buffer capacitors referenced to a common potential (ground) and, furthermore, only two fast-switching transistors (one half-bridge), simplifying the circuit and control. This work's approach separates the fast and slow-switching circuit parts such that the fast-switching part can be implemented with highly efficient wide bandgap devices, and the slow-switching part can be implemented as an almost lossless multiplexer circuit with Si devices of very low conduction loss.

C. Structure of the Work
Section II presents the proposed converter topology, which is based on a two-level GaN-based half-bridge converter and multilevel Si-based multiplexer to add additional capacitor-buffered voltage levels. Both parts are combined, and an efficiency analysis is carried out.
Section III presents experimental results. After the description of the prototype implementation and efficiency measurement setup, the 99.74% efficiency measurement result is shown and discussed.
Section IV discusses the application of the proposed converter to electrocaloric heat pump working in different thermodynamic cycles and estimates the achievable best-case heat-pump system COP.
Section V concludes that the low charging loss of the proposed converter allows to significantly improve the achievable relative system COP of electrocaloric heat pumps, possibly exceeding 50% (for Carnot-like cycles) or 75% (for Ericsson cycles with temperature regeneration) of the Carnot limit. This paves the way toward future solid-state, emission-free, and highly efficient heat-pump systems.
II. SIX-LEVEL GAN/SI-HYBRID TOPOLOGY Fig. 4 shows the proposed topology and typical switching waveforms for ultraefficient charging and discharging of electrocaloric capacitive loads. The proposed topology is based on a partial power processing principle, which theoretically (for a lossless multiplexer) allows a reduction of the converter losses by a factor of (N −1). How close a real implementation reaches this ideal loss reduction factor is first analytically investigated. Then, a six-level prototype is built and operated to verify the efficiency improvement of the approach. Fig. 5 shows typical waveforms of the prototype discussed later in this work. Within the signal blocks of the switch node voltage and inductor current and low-side gate voltage, the GaN half-bridge operates with a fast-switching hysteretic current control. The measured step-wise triangular output voltage is as expected the difference between the positive load voltage V C+ and switched multiplexer voltage V C− (see and compare to Fig. 4).

A. GaN-Based Converter Part
The efficiency of the GaN-based half-bridge η dc is the average of continuous cyclic charging and discharging of a capacitive load by the low voltage V , as shown in Fig. 3. This work's GaN converter has a full power processing (FPP) efficiency (1) Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. At V = 70 V, I ≈ 0.13 A (average rectified charging current) for a C EC = 10 µF load. A measured η dc value is used because it combines all losses (switching, conduction, inductor, buffer capacitors, and so on), which otherwise were difficult to model precisely.
The efficiency of this converter is also decisive for the later discussed advanced topology. Any improvement in the efficiency of this converter, as part of the complete topology discussed next, will further improve the system efficiency. The 99.2% efficiency of the GaN half-bridge converter might be, for example, improved by using different GaN transistors or optimized power inductors or other optimization of control parameters. For the sake of simplicity in this article, however, the 99.2% converter efficiency is used as a constant value in the following.
The GaN-based half-bridge converter has two levels, N = 2, where N is the number of voltage levels. An external offset voltage V C,0 , if present, is not counted as an additional level since it is statically (not switched) superimposes to the circuit but has no fundamental effect on the analysis in this work.
This work uses a hysteretic current control with constant inductor current ripple I L (constant peak and valley current set-points) such that the switching frequency (2) is variable, depending on the converter voltage V C+ , but limited by a maximum switching frequency f SW,MAX at V C+ = (1/2)V dc . Assuming complete voltage transitions (from 0 to V dc during charging and V dc to 0 during discharging), zero standby times between the voltage transitions, and a constant load capacitance C EC , then the average switching frequency is calculated as   Typical switching waveforms of the hysteretic current control. Reprinted from [28] with permission, © 2021 VDE VERLAG GMBH.
transistors [37] are used, as discussed later) is provided by the gate driver supplies, but, since it is small compared to the power stage losses, it is neglected in this work. The GaN transistors used in this work are operated below their typical voltage and current ratings. Increasing the charging current would increase the average charging power, but the gate drive losses would stay almost constant. Thus, with increased utilization of the GaN transistors, the gate drive losses would be even smaller compared to the power stage losses. For the target application, the availability of electrocaloric capacitors is limited to few manually fabricated samples such that, in this work also, a reduced power rating of the converter is investigated.
The GaN half-bridge converter is the same as in [28], and the hysteretic current control parameters were optimized to achieve high efficiencies. For example, Fig. 6 shows the effect of the hysteretic peak and valley (ZVS) current setpoints on the efficiency, and Fig. 7 shows the effect of the input voltage on efficiency. Typical switching waveforms of the hysteretic current control are shown in Fig. 8 (the dc voltage in that figure is higher than what is used later in this work). Further details on the current control and the effect of additional parameters (dead times and cycle frequency) on efficiency are discussed in [28]. As will be discussed, the overall efficiency of the advanced converter topology presented in this work depends on the high efficiency of the GaN-based converter part.

B. Si-Based Multiplexer Part
The two-level GaN converter is extended by a high voltage Si-based multiplexer to an N -level (multilevel [38]) switched capacitor circuit with N > 2. This increases the maximum load voltage change to V MAX = (N − 1) V > V while maintaining a low-voltage operation of only V in the GaN part. This topology, thus, uses a partial power processing [39], [40] approach, similar to differential power processing [41] approaches, to increase the total efficiency. The multiplexer consists of (N − 1) branches with slow-switching switches that connect one of (N − 1) buffer capacitors to one terminal of the capacitive load. The two branches with the highest and lowest levels are realized with just one unidirectional blocking Si MOSFET, whereas the middle levels require bidirectional blocking switches, which are realized by two series-connected Si MOSFETs in common-source configuration with a combined gate driver. One branch (V 0 ) is used as externally provided and adjustable offset voltage input V 0 = −V C,0 , which has the same function as the offset input of the conventional topology (see V C,0 in Fig. 3). One by one, the consecutive branches are connected in an upcounting way and then a down-counting way, while the time period during each level is at least as long as it takes to charge the capacitive load by V . After a self-balancing and self-biased startup sequence, the branches settle to a steadystate condition where the difference between two consecutive branches reaches up to V . The self-balancing mechanism was observed experimentally and also in simplified circuit simulations. The self-balancing mechanism results in equally spaced voltage levels, separated by ≈ V between consecutive levels. The self-balancing and biasing characteristic of the converter was analyzed and verified. However, since this work focuses on the efficiency in steady-state operation (after the startup, balancing and offset biasing are finished), the detailed analysis is discussed in Appendix A. The GaN part allows a continuous voltage control (node V C+ ) within a range of V and the Si part additional discrete voltage steps of up to V , with a total additional voltage as high as (N − 2) V (node V C− ), which combined allows a continuous voltage control (V C = V C+ − V C− ) of the capacitive load in a range of V C,0 . . . V C,0 + V MAX , with V MAX = (N − 1) V and arbitrary offset voltage V C,0 . In the implemented prototype, this value will be not fully reached since the buffer capacitors (C BUF ) are not sufficiently large compared to the load capacitor (C), which forms a capacitive voltage divider and reduces the load voltage change below the theoretically possible value. This reduction by the capacitor ratio is also addressed in Appendix A.
The multilevel circuit (Si-based part) is similar to the extended basic unit of the basic topology for known submultilevel converters [38] or multilevel inverters [42]. The principle of operation might also be achieved with cascaded converters [43], [44]. The implementation with bidirectional blocking transistors and grounded capacitors is one possible implementation for efficient multilevel voltage generation, which is also previously used in photovoltaic topologies [45], and can be replaced by other basic switching cells [46], topologies [47], [48], or other arrangements of the capacitors. The proposed implementation is a kind of reduced switchcount topology [49]; the same functionality might be achieved also with topology derivations [50].

C. Efficiency Analysis
The GaN-based converter processes only a part of the capacitor's charging power. For a lossless multiplexer (η MUX = 1), the ideal achievable partial power processing efficiency of the complete N level topology is theoretically improved to the ideal (lossless multiplexer switches) partial power processing efficiency which is a theoretical reduction of the loss on the system level to the fraction 1/(N − 1). Of course, the absolute loss of the GaN-based converter stays constant and is not reduced. However, on the system level, the voltage range that the load capacitor sees is significantly increased compared to the lower voltage of the half-bridge converter. Consequently, the (average) charging power which the capacitive load sees is significantly increased, whereas the power loss of the system is still kept constant in the low-voltage circuit part. The sixlevel implementation in this work, thus, allows a theoretical reduction of the losses to a fifth, theoretically improving the achievable efficiency to the ideal partial power processing efficiency However, the multiplexer introduces additional static and dynamic losses such that the system efficiency of practical implementations of the topology will be slightly reduced. For an FPP efficiency of the multiplexer η MUX , the total efficiency of the topology follows from the series connection of the GaN and Si-based parts as The multiplexer efficiency η MUX is analyzed and calculated based on a loss breakdown and modeling of the conduction loss P cond , switching loss P sw , leakage current loss P lk , and gate drive loss P charge . The modeling and analysis of these four loss contributions of the Si-based multiplexer are discussed in detail in Appendix B.
The average charging power P charge of the capacitive load is with no factor (1/2) since the stored energy in the capacitor is moved twice (charging and discharging) per cycle ( f −1 SYS ). The multiplexer efficiency follows (based on the calculated contributions from Appendix B) as It is noted that, in this calculation, the (maximum possible) cycle frequency f SYS < I (2C V MAX ) −1 follows from the charging current, voltage change, and capacitance such that the capacitor is continuously charged and discharged without standby times in-between. Operation with standby phases between charging and discharging will slightly further reduce the multiplexer efficiency due to additional leakage losses Fig. 9. Calculated total efficiency η PPP based on a 99.2% converter, which is used for partial power processing in an N -level topology as in Fig. 4. The efficiency of the multiplexer is η MUX , and the ideal (for η MUX = 1) partial power processing efficiency is η PPP,ideal . N = 2 is a conventional two-level converter, as shown in Fig. 3.
(investigated in [29]). For the selected Si MOSFET technology, the leakage loss, however, is negligible compared to the conduction and switching losses such that this simplification has little influence.
The efficiency of the slow-switching high-voltage Si-based multiplexer depends on the operation point and transistor selection. The operation point used in this work is for a charging current I = 0.13 A with a load capacitance of C = 10 µF and a manually selected 600 V-class Si transistor (Infineon IPP60R022S7, ON-resistance R = 22 m , approximated output capacitance C OSS = 10 nF, leakage current I lk = 1 nA measured at room temperature, gate charge Q G = 150 nC, and drive voltage V G = 12 V). For the six-level topology with V = 70 V, the total voltage change across the capacitive load is V MAX = 350 V, and the calculated multiplexer efficiency is For the six-level circuit and previously listed parameters, a cycle frequency f SYS ≈ 19 Hz results. This cycle frequency is also a typical value for caloric heat-pump systems; for example, a magnetocaloric prototype with 20 Hz cycle frequency is realized in [51], which might be modified to an electrocaloric prototype with a similar cycle frequency. Even though the cycle frequency is not a parameter here, on the system level, other cycle frequencies and capacitive load values are possible by scaling the charging current, which means dimensioning the converter for a different power class.
The loss breakdown of the multiplexer into conduction, leakage, switching, and gate loss is 3.1%, 0.003%, 95.5%, and 1.4%, respectively. Thus, the switching losses of the multiplexer dominate. It is noted that the selected Si transistors have a relatively high output capacitance, which is switched under hard-switching conditions in the multiplexer, causing these high losses. It is possible to select an optimal-sized multiplexer switch. Introducing a scaling factor k, which describes the transistor size relative to the selected transistor (reference: k = 1) into the loss equations, scales the switching, leakage, and gate drive losses by k and the conduction loss by 1/k. The numerical solution for the optimal sizing of the transistors is at k = 0.18, which is a 122 m transistor in the same technology, instead of the selected 22 m transistor. Fig. 10. Calculated total efficiency η PPP based on a 99.2% converter, which is used for partial power processing in an N -level topology, as shown in Fig. 4. The efficiency of the multiplexer is η MUX (with optimal sized transistors), and the ideal (for η MUX = 1) partial power processing efficiency is η PPP,ideal .
For the optimal dimensioning, the multiplexer efficiency is further increased to η MUX = 99.971%, and the loss breakdown into conduction, switching, and leakage losses is now well-balanced (50%, 49.3%), mainly between switching and conduction losses. The gate drive losses (0.7%) are negligible due to the slow switching frequencies and, thus, not further considered in the experimental part. The leakage loss also is negligible (0.0015%).
The effect of the number of levels is further analyzed (for the selected 22 m transistor). Based on a 99.2% efficient GaN part, the ideal partial power processing efficiency η PPP,ideal , the calculated multiplexer efficiency (based on the previously derived loss model), and the combined total efficiency η PPP are shown in Fig. 9. A low number of levels (3 or 4), just higher than a conventional two-level circuit, yield already a significant efficiency improvement. For N = 5 levels, the target efficiency of 99.71% is just surpassed. Fig. 9 also shows the later experimentally measured value of 99.74% for a six-level prototype. Fig. 10 shows the same calculation results for optimal-sized transistors, where the calculated multiplexer always reaches an optimal value above 99.97%, such that the efficiency of the complete topology η PPP stays just slightly below the ideal partial power processing efficiency η PPP,ideal .
While this work uses two common-source Si-MOSFETs to realize the required bidirectional blocking switches, it is noted that one monolithic bidirectional switch can replace the two Si MOSFETs. Using GaN-based bidirectional switches with a common (drain) channel [52] instead, the ON-resistance is halved, reducing the conduction loss of (21), and at the same time, the switching loss of (22) is further reduced due to lower output capacitance. Both will increase the achievable multiplexer efficiency beyond the calculated η PPP = 99.811% in this work.

A. Prototype Implementation
Targeting 99.71% efficiency and based on the results from Fig. 9, a five-level circuit seems just sufficient. However, a sixlevel (N = 6) circuit is built since experimentally slightly more losses are expected and unaccounted in the simple loss model, and the noninfinite capacitive voltage divider C BUF ≫ C EC results in less utilization of the circuit than assumed in the analysis. Table I lists the main components and equipment used for the prototype and experiments. The fast-switching half-bridge uses commercial 600-V GaN gate-injection transistors due to their outstanding semiconductor device figure-of-merits [53], such as ON-resistance to gate-charge (R ON · Q G ) and ONresistance to output capacitance (R ON · C OSS ) and low leakage losses. The slow-switching multiplexer uses Si superjunction MOSFETs.
The GaN half-bridge converter is controlled by a closedloop hysteretic current controller, as explained in [28] for a two-level circuit. The controller algorithm is extended by an open-loop up-/down-counter to switch on the branches of the multiplexer. Fig. 11 shows the GaN-based converter and the Si-based multiplexer, realized on separate boards and then connected by wires to realize the complete topology. Fig. 12 shows the fully connected GaN/Si-hybrid converter, which is connected to two power supplies (V dc , V C,0 , not visible), a power analyzer (measuring the two supply powers and the inductor current/load voltage, not visible), and oscilloscope by voltage and current probes. The complete setup is modular and allows replacing and extending the GaN-and Si-based converter parts. It is noted that the shown half-bridge board in Fig. 12 has a slightly different layout (but the same components), as shown in Fig. 11. Furthermore, Fig. 12 shows a five-level topology, which initially missed the efficiency target and, thus, was then extended to the six-level topology by an additional multiplexer branch, plugged into the additionally available sockets of the multiplexer main board in Fig. 12, which theoretically allows to plug in additional branches to realize a further increased number of levels.

B. Efficiency Measurement Setup
The converter has a capacitive (electrocaloric) load as part of the circuit and capacitive buffers at the inputs. Due to the cyclic charging and discharging, a high amount of energy is cycled within the system. This energy is related to a high charging and discharging power, which, however, is maintained mainly within the circuit. Externally, only the power loss has to be provided and, thus, can be measured with high accuracy. The operation mode of the converter is a time multiplexing of charging and discharging phases (see Fig. 4) between the buffer capacitors and the load capacitance. The average of the absolute values of the charging and discharging powers is measured, and the power loss into the system is directly measured. Thus, this kind of measurement is a roundtrip energy efficiency measurement averaged over complete charging and discharging cycles. Since the power loss is directly measured (allowing to set the corresponding power analyzer channel to a range close to the power loss and not the charging power), it is measured with high accuracy. This is much more accurate and different from a typical unidirectional (resistive) load dc-dc converter efficiency measurement setup, where the high processed power is both input and output through the systems, and the power loss is only indirectly calculated from the difference of the input and output powers, which then is less accurate, especially for efficiencies above 99%. Here, a highly accurate and direct power loss measurement is possible. Both input voltages (V dc = V and V C,0 ) are provided through an RC filter (R = 1.1 k , C from the buffer capacitors C BUF = 300 µF) with a corner frequency below the cycle frequency. As a result, the two external sources only have to provide the low power loss (in the 10-100-mW range) such that the power analyzer at the inputs also measures just these losses. The over 100 times higher charging power is measured by a nonintrusive Hall-sensor-based current probe (in addition to a power analyzer voltage probe parallel to the load capacitance). Fig. 13 shows the setup of the power analyzer and circuit for power loss/efficiency measurement.
The gate driver loss is not included in the measurement results since the calculated contribution for the slow switching frequencies is negligible. Furthermore, only the power-stage loss is measured, but the power consumption of the control circuit is not considered. In this work a controller evaluation board and laboratory-type voltage and current measurement equipment are used, resulting in a high loss of the control circuit compared to the power stage power. While this work only considered a relatively small load capacitance, for largescale heat-pump systems, it is expected that a charging circuit in the kilowatt-range will be required such that the static power loss of the control circuit will be small compared to the power stage loss. Furthermore, this work uses a closedloop current control on a controller. Theoretically, for a known load and fixed operation conditions, the switching signals for a complete cycle could also be precalculated and applied to the transistors from a switching waveform memory in openloop operation, which theoretically also allows removing all voltage and current sensors. Even though this approach is not very flexible anymore, it serves to justify why the additional losses from the control system and probes are neglected in the efficiency measurements in this work.

C. Discussion of Efficiency Measurement Accuracy
The setup results in high accuracy of the extracted efficiency since the power loss is directly measured (and not superimposed by the processed power as in a conventional unidirectional dc-dc efficiency measurement setup), especially for efficiencies >99%.
The error of the measured efficiency (reading) compared to the actual efficiency η is analyzed: The efficiency of a conventional unidirectional dc-dc power converter at a stationary operation point is typically measured with the conventional method of measuring both the total input and total output powers of the converter. The (small) power loss is calculated by the difference of these two (large) powers. Consequently, the expected error of the efficiency reading is high. If the accuracy of the input and output power measurement is, for example, ϵ = ϵ IN = ϵ OUT , then the efficiency reading might be within η MIN = η(1 − ϵ/1 + ϵ) and η MAX = η(1 + ϵ/1 − ϵ). This error band of the conventional method is shown in Fig. 14, and it is apparent that, especially at high actual efficiencies, even unphysical readings > 100% can result. For example, for η = 99.74%, the reading might be within 99.54%, . . . , 100.2%. In this work, however, the converter cycles the high charging power between the input buffer capacitors and the load capacitor. Only the power loss has to be provided externally. Now, the power loss can be measured directly with the full accuracy of the power analyzer ϵ IN = ϵ. However, the (average rectified) charging power of the bidirectional load capacitor charging has to be measured. In this work, it is calculated from the measured rectified narrowband charging current and peak-to-peak load voltage change, which is possible here because constant buffer and load capacitors are used (directly linking the charging current to the load voltage by the proportionality to the capacitor voltage change). The effective charging and discharging powers could also be measured by separate measurements of the charging power and discharging power. However, this requires a more complicated triggering of the power analyzer (twice per system cycle). In this work, Hall sensors are used for the charging current measurement (to avoid losses of shunts within the circuit). The accuracy ϵ OUT of this charging power measurement is, thus, below the typical accuracy of a power analyzer. Nevertheless, since the power loss is directly measured, the efficiency reading is now in a much narrower band (more accurate). The efficiency reading is now within the minimum and maximum expected efficiency reading of η MIN = 1 + (η − 1)(1 + ϵ/1 − ϵ OUT ) and η MAX = 1 + (η − 1)(1 − ϵ/1 + ϵ OUT ). The accuracy of the measurement, thus, now only scales with the power loss (1−η), which is much smaller compared to the charging power (related to η). For this proposed method used in this work and for improved accuracies of the charging power measurement (ϵ OUT = 1% and 10%), the error band is also shown in Fig. 14. Since the power loss is directly measured, the error band reduces with increasing efficiencies. For example, for low charging power measurement accuracies of 10% (and 0.1% input power loss measurement), an actual converter efficiency of η = 99.74% now results in more accurate expected readings within 99.711%, . . . , 99.764%. The expected error band of the method used in this work is visible as triangularly tapering and decreasing band in Fig. 14, with significantly more accurate efficiency readings compared to a conventional continuous unidirectional dc-dc power measurement method.
It should be mentioned that the efficiency measurement setup with a capacitive load and cyclic charging and discharging might also be a useful method for efficiency measurement in general for ultraefficient power converters. In the literature, two back-to-back connected converters and the opposition method [54], [55], [56] are often used for highly accurate efficiency measurements. While all those methods achieve similar efficiency accuracy as in this work (since the power loss is also directly measured), this work's method with a capacitive load has the advantage that only one converter is required. The function of the two converters in the back-toback arrangement with unidirectional power flow is realized in this work by time multiplexing, using the same converter for alternating charging and discharging. Different from this work, where the full voltage swing V = V dc is required, an additional voltage control could limit the output voltage to a narrow range around a desired input-to-output voltage ratio. Instead of the capacitor charging power measurement, the measurement of just the load capacitor peak-to-peak voltage change should also be sufficient to calculate the charging power if a reference capacitor with a precisely known value is used.

D. 99.74% Efficiency Measurement Result
Figs. 15 and 16 show the measured voltage and current waveforms aquired from the power analyzer and oscilloscope, respectively, during 99.74% efficient continuous operation. The rectified narrowband inductor current (I Rect,NB,L = 125.86 mA), (peak-to-peak) capacitive voltage change ( V C = 316.99 V), and cycle frequency ( f SYS = 20.002 Hz) are measured with the power analyzer to verify the extracted load capacitance (9.927 µF) with the exemplary C = 10 µF capacitor value. Since the extracted capacitance value is very close to the expected datasheet value, and the extracted capacitance is directly linked to the charging power, it follows that the charging power measurement is much more accurate than the 10% used for the previous calculation of the efficiency reading error band, increasing the accuracy of the efficiency reading. The narrowband (low-pass filtered, corner frequency of around 1 kHz, between the minimum switching frequency and the cycle frequency) inductor current is used Fig. 15.
Capacitive load voltage (316.9-V peak-to-peak) and current waveforms (average rectified narrowband charging current of ≈ 0.13 A) at f = 20 Hz. The shown numbers are approximate values; for efficiency calculations, the actual measured values were taken. Switching waveforms from the oscilloscope. The switch-node voltage and inductor current have a variable and high switching frequency in the 10, . . . , 100-kHz range, resulting from the hysteretic current control.
here since, otherwise, the short periods of time where the inductor current changes signs for ZVS-switching result in an overestimation of the charging current if the wideband current was directly rectified and averaged. From these values, the average charging or discharging power (19.947 W) is extracted. The measured effective input voltage for the GaN converter is V dc = 69.225 V. From the measured and summed wideband active power input to V dc and V C,0 (62.436 mW), the total voltage probe losses (at least 10.5 mW), calculated from the measured effective wideband voltage values directly from the power analyzer, were subtracted, which gives the total power loss (51.854 mW) of the topology including the load, but without the voltage probes (which are only required for the power loss and switching waveform measurements and can be removed in real applications). From the ratio of the directly measured power loss (with high accuracy as described earlier, not superimposed by the large reactive power cycling within the system) to the measured charging power (0.26%), a measured efficiency η PPP,meas = 99.74% (11) follows, close to the calculated value of 99.756%. Even if the worst case error band of the accuracy analysis is included, the target efficiency of 99.71% is still surpassed.

E. Breakdown of Measured Power Loss
The measured power loss is further investigated by the breakdown in Fig. 17. Here, also additional losses from the Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. experimental setup and limitations of the used components and interconnections are considered. The measured 36.4-mW power loss of the 99.2% efficient GaN-based converter in FPP operation (70 V) is assigned to conduction loss of the GaN transistors (140 m ), deadtime loss (≈ 10 ns conduction), C OSS related soft-switching losses (interpolated from [57]), ac and dc losses of the used four series-connected inductors (loss calculator REDEXPERT from the manufacturer), stored energy in the inductor, which is dissipated in the standby phases (see the low-frequency ringing in Fig. 5 between the current bursts), and conduction loss of wires in the experimental setup (350 m , the sum of four-point resistance measurements in the dc−, SW, and dc+ paths of the setup). This resistance could be reduced in future demonstrators by implementing the complete circuit on one PCB and improved, less intrusive measurement equipment. A remaining power loss contribution is unaccounted for. These unaccounted losses include the dissipation factor-related losses of the capacitive load, with an estimated dissipation factor below 0.05%, from the datasheet. As described in Section II-A, it is difficult to completely describe all losses in a dc-dc converter. Thus, in the calculations, the measured efficiency (derived from the measured power loss) was used in the circuit analysis.
For the partial-power-processing (PPP) converter, the measured 51.9 mW power losses are partly assigned to the same losses as in the FPP GaN-based converter part (since this part is reused in the FPP circuit and operated in the same operation point) and partly to additional losses from the Si-based converter part. These additional considered losses are the conduction loss and hard-switching loss from the Si MOSFETs. For the switching losses (see Appendix B), the measured output voltage change (316.9 V) and not the theoretical value of (350 V) is used. The measured loss difference between the FPP and PPP circuit matches the calculated sum of conduction and switching loss of the Si transistors well. From the power loss difference (15.5 mW) divided by the charging power (19.95 W), the measured multiplexer efficiency results as 99.922%, close to the calculated value 99.916% from (8). The measured multiplexer is higher than the calculated value, which can be explained because the measured voltage change per level is lower than the theoretical maximum value, and thus, the switching losses are also lower than in the theoretical calculations. Fig. 17 also shows the measured charging power and the measured efficiency of the FPP (99.2%) and PPP (99.74%) converters. It is visible that the partial-power processing approach allows increasing the charging power to 438%, while the loss only increased to 142%, resulting in an efficiency improvement from 99.2% to 99.74% (since the ratio of power loss to charging power is reduced to 32% (=142%/438%), around a third). This relative loss reduction to around a third is below the ideal improvement to a fifth (according to (3) for a hypothetical loss less multiplexer) for the N = 6 circuit with a partial power processing approach. Nevertheless, the improvement is still a significant improvement on the system level (99.74% charging efficiency), which might be, otherwise, difficult to achieve with just a two-level (GaN) half-bridge topology. Fig. 17.
Loss breakdown of measured losses for low-voltage reference converter with FPP and extended partial PPP.

IV. APPLICATION IN ELECTROCALORIC HEAT PUMPS
Despite a theoretically very high relative material COP, close to the Carnot limit, for example, above 85% using a PMN ceramic [14], [15], there are no commercial electrocaloric heat-pump systems yet, and even prototypes from research institutions (overviews in [10], [58], and [59]) only achieve a low relative system COP. To the best of our knowledge, the highest reported system COP for electrocaloric heat-pump prototypes of 12% (relative to the Carnot limit) is reported by Meng et al. [60] in 2020 (using a resonant circuit as charging circuit and electrocaloric polymers instead of ceramics as in this work). This reported performance still is not competitive with vapor compression systems and is also significantly below 50% of the Carnot limit. One reason for the low system performance is that the external charging losses (from the required charging circuit) significantly deteriorate the system performance, despite low electrocaloric material losses, which could theoretically allow significantly higher high performance. The electrocaloric heat-pump system COP depends significantly on the losses of the external charging circuits [14], [15], [19], [61], which is required to cyclically change the voltage across the electrocaloric capacitors and the thermodynamic cycle [61]. Especially, for very low-loss electrocaloric dielectrics, such as the addressed PMN, with very low dielectric losses, an ultrahigh-efficient charging circuit is required to maintain a high cooling or heating performance also on the heat-pump system level.

A. Carnot Cycle, No Regeneration
A first-principle and best-case (Carnot-like cycle) analysis of the achievable heat-pump COP (heat pump used in cooling operation), as derived in [15], estimates the best-case heatpump system COP for a Carnot cycle without additional temperature regeneration. For an electrocaloric sample based on PMN material fabricated and characterized by the authors, as already Fig. 18. Calculated best-case heat-pump system COP for electrocaloric PMN sample (data from [15], with offset) depending on external charging efficiency η dc for a Carnot cycle.
used in [15], the electrocaloric figure of merit FOM EC = ρc P T 2 AD,MAX /4εT E 2 MAX from (12) is approximately FOM EC = 0.00341 at an optimal operation point (around 7 V/µm with offset fields, at room temperature), and the electrocaloric material's effective time-related dissipation factor is as low as DF = 0.0625%.
The relative system COP is reduced from the ideal Carnot cycle (COP R,SYS = 100%) due to the losses in the electrocaloric capacitor (material dissipation factor DF > 0%) and the external charging efficiency η < 100%. Equation (12) is based on the estimation (see [15], [62]) that, without temperature regeneration, the loss-optimal Carnot-like cooling cycle is such that half of the adiabatic temperature change (1/2) T AD,MAX using half of the maximum voltage or field change (1/2) E MAX is used to overcome the optimal temperature difference between the hot side and the cold side (T H −T C = (1/2) T AD,MAX ) in the adiabatic legs of the cycle. Only the remaining half of the temperature/field change is then available and used for cooling during the isothermal cooling leg of the cycle.
Carnot-like cycles are more efficient than the easier-torealize Brayton cycles typically used in electrocaloric prototypes (e.g., [19]). The feasibility of Carnot-like cycles (with quasi-isothermal heat transfer) was demonstrated by the authors for the first time in an electrocaloric prototype using field variation with a similar, but only two-level, converter in [29]. In general, arbitrary voltage variation is possible also with the advanced topology in this work, using a similar approach as already presented in [28], for example, to realize optimal thermodynamic cycles [63]. Fig. 18 shows the calculated best-case heat-pump system COP for Carnot-like thermodynamic cycles, based on the previously discussed material data, and as a function of external charging efficiency η dc .
For reference, in [15], for Carnot-like cycles with no regeneration, a relative system COP up to 28.6% with a 99.2% efficient two-level converter was predicted, using a conventional two-level half-bridge converter. With this work's 99.74% efficient partial power processing converter, now, for the same PMN material, a relative system COP of 52.5% is predicted. It is noted that this predicts that over 50% Carnot COP for electrocaloric heat pumps is feasible with technologies (electrocaloric PMN material and ultraefficient power converter), which exists already today, and without temperature regeneration.

B. Other Thermal Cycles, With Regeneration
Other thermal cycles can further improve the system's performance. For example, an Ericsson cycle with temperature regeneration allows utilizing the full adiabatic temperature change of the electrocaloric sample in contrast to only half at the optimal operation point with Carnot cycles. Likewise, the heat absorbed or dumped to the cold or hot sides is, thereby, also doubled. This results in an additional factor of four in the second summand of the denominator of (12), which improves COP R,SYS for the same DF and η dc . The calculated best-case COP R,SYS for Ericsson cycles and temperature regeneration by T AD,MAX is improved from 61.6% (η dc = 99.2%) to 81.5% if this work's η dc = 99.74% efficient converter is used with such Ericsson cycles.
The predicted system performance above 50% of the Carnot limit for thermal cycles without temperature regeneration is a milestone worked toward in research on electrocaloric heat pumps since it will enable competitive cooling performance compared to conventional heat pumps. The furthermore predicted performance of around 75% of the Carnot limit for advanced thermal cycles (Ericsson with temperature regeneration) would already outperform most of today's vapor compression heat pumps [31]. Electrical capacitor-charging circuits with ultrahigh electrical efficiencies are key components to achieve future high-performance electrocaloric heat pumps.
This work only focused on improving the electrical charging efficiency for one available electrocaloric PMN material sample, but ongoing material research and improvement, such as increasing the electrocaloric effect or reducing the permittivity for improved FOM EC , or reducing the dissipation factor DF, all parameters in (12) in addition to the electrical charging efficiency η, will further improve the system COP in future.

V. CONCLUSION
The addition of a high-voltage, switched capacitor, and Si-based multiplexer to an already efficient GaN half-bridge two-level converter, as a partial power processing approach, enables a significant improvement of the capacitor charging efficiency to 99.74% based on a 99.2% efficient low-voltage GaN converter. The additional voltage levels of the N -level GaN/Si-hybrid converter increase the maximum realizable voltage change across a capacitive load beyond the low input voltage of just the low-voltage two-level half-bridge converter and, thus, effectively reduce the system losses to a fraction, depending on the number of levels. The demonstrated 99.74% efficient cyclic charging and discharging of capacitors can be used in electrocaloric heat pumps to change the electric field in electrocaloric dielectrics, which causes an almost fully reversible temperature change. Based on electrocaloric PMN material data characterized by the authors, it is projected that the best-case heat-pump system COP, which includes the external charging losses, can surpass 50% of the Carnot COP limit for Carnot-cycles without temperature regeneration. For regenerative Ericsson cycles with ideal temperature regeneration equal to the adiabatic temperature change of the electrocaloric material, it is predicted that even above 75% of the Carnot limit seems feasible in combination with this work's ultrahigh charging efficiency. This paves the way toward emission-free electrocaloric heat pumps, possibly even outperforming today's vapor compression heat pumps.

APPENDIX A SELF-BALANCING AND BIASING ANALYSIS
The self-balancing and biasing characteristics of the circuit are verified here using a first principle analysis. All buffer capacitors are assumed to have the same capacitance C BUF , significantly higher than the load capacitance C EC . The ratio r = C EC /(C BUF + C EC ) is, for example, r ≪ (1/10). The voltage levels of the buffer capacitors (V 0 , V 1 , . . . , V N−2 ), the (constant) dc input voltage V dc , and the positive terminal voltage V C+ (referenced to ground) of the capacitive load C EC , the device under test (DUT), are described by the voltage state vector with an arbitrary initial condition, for example, V = (V dc , 0, . . . , 0) T . The V C− voltage is not included here since it is already defined by the buffer voltages and switching state (for example, V C− = V 0 during the first level). The load voltage difference can be calculated by V C = V C+ − V C− in a similar way for all states but is not of further interest here for the balancing and biasing analysis. A full system cycle (see Fig. 4) is simplified to a series of charging time periods (states S0, . . . , S(N − 2), separated by the low-frequency switching events of the Si MOSFET multiplexer) and discharging time periods (states S (N − 2), . . . , S0, also separated by switching events of multiplexer). During the charging or discharging periods, the hysteretic current control charges or discharges the half-bridge converter output voltage V C+ from its starting voltage to a final voltage of V dc or 0 V, respectively. A complete system cycle is modeled as follows, starting from the lowest state at the beginning of the first charging period (as shown in Fig. 4). First, the circuit is analyzed for the case where all buffer capacitors are left floating (the external offset source is, thus, not used and not connected to V 0 ). Then, it is analyzed how an arbitrary offset voltage can be established by biasing one buffer capacitor externally to a defined offset voltage V C,0 from an external voltage source. Since the effect of the external offset voltage is superimposed, it is analyzed later separately as an extension of the following case.

A. No Externally Provided Offset Voltage
If no external offset voltage is provided, the first buffer capacitor is treated similar to all other buffer capacitors, and the voltage is described as V 0 (instead of V C,0 ). The starting voltage V C+ is increased by the charging operation of the half-bridge converter to V dc . The voltage change at the V C+ node during this charging transition is V dc − V C+ , but the voltage change at the buffer capacitor is only r (V dc − V C+ ) due to the capacitive series divider (C EC and C BUF ). All other disconnected buffer capacitors maintain their voltages. After the first charging phase, the multiplexer switches the load capacitance from the first to the second buffer capacitor. The positive terminal voltage V C+ is, thereby, changed by the difference between the two involved buffer capacitor voltages. This first charging transition is modeled by the matrix C 1 , followed by the switching event from the first to the second buffer capacitor, which is modeled as SC 12 . As a minimal example, the case for three buffer capacitors is described as and can be increased using the same method to a higher number of levels. Matrix multiplication V ′ = SC 12 C 1 V gives the voltage state vector V ′ after the first charging and level switching events. The further charging and switching events are described in a similar way as followed by From this highest state, now, the discharging phases follow. During discharging, the half-bridge converter now discharges the node voltage V C+ from its starting value to 0 V (GND). The first discharging transition and the following switching event are modeled as A complete cycle, thus, is described by the transition matrix M = D 1 S D 21 D 2 S D 32 D 3 C 3 SC 23 C 2 SC 12 C 1 . Now, the time evolution of the buffer capacitor voltages after k full system cycles with the initial condition V can be calculated as As an example, for r = (1/10) and V dc = 1 (normalized), with initially discharged buffer and load capacitors, the time evolution of the voltage state vector values, which includes the buffer capacitor voltages, are plotted in Fig. 19. In the limit of k → ∞, the buffer voltages (V 0 , V 1 , V 2 ) reach ((243/280), (−9/280), (−261/280)) ≈ (0.8679, −0.03214, −0.9321), equally spaced by (9/10), which is (1 − r )V dc . The calculated time evolution shows a stable transition to the final steady-state values. The maximum load voltage change increases during the startup process to V MAX = (1 − r )(N − 1)V dc , which is slightly reduced from the ideal value (N − 1)V dc (which was used in the simplified analysis in Section II-B) by the capacitive divider ratio.
In addition to the previously shown analysis, during the startup of the prototype, the same stable self-balancing and biasing characteristics were also observed. Furthermore, with LTspice simulations of a simplified converter circuit, it was verified that the losses in the circuit components (mainly in the switches), which were ignored in the analysis, do not lead to an unstable operation. In particular, no voltage drift over time was observed; instead, the simulated and measured circuits both converged to stable and well-balanced buffer capacitor voltages. It should be mentioned that this work assumes a constant (voltage-independent) load capacitance C EC . For nonlinear and multiparameter (for example, voltage and temperature) dependent load capacitances C EC (V, T ), the steady-state buffer capacitor voltage levels will not be equally spaced anymore. The converter was also experimentally operated with a nonlinear, electrocaloric, and multi-parameter dependent load C EC , where nonequally spaced state voltages were observed. The magnitude of deviation compared to this work's linear analysis might be limited by further reducing the capacitor divider ratio r or by advanced circuit topology variations or extensions. Despite the nonequal spacing for these special cases, the circuit still showed well-behaved and stable self-biasing and balancing characteristics. The application of this work's converter to nonlinear, multiparameter-dependent, and electrocaloric capacitors should be further investigated in future works.
In this work, the operation principle is a hysteretic current control as inner closed-loop control, with an outer open-loop state machine. The system frequency is selected sufficiently low such that each charging or discharging step completely finishes (V C+ reaching either V dc or 0 and then maintaining that value until the next charging or discharging step). Since, in each step, V C+ reaches a defined value and then maintains that value during the (short) standby time until the start of the next step by the outer open-loop control, the overall system is stable. Even though the inner current control is a closed-loop control, the outer control is an open loop but still ensures stable operation. This stability might be lost if the level state machine switches to the next state while the charging or discharging transitions are not finished yet. In Fig. 5, it is clearly visible how each state ends with a standby period after the charging or discharging to the next level is finished. In Fig. 16, this standby phase is reduced to a minimum. There, any further increase in the system frequency or load capacitance might result in unstable operation. Instead of the open-loop state machine in this work, the load voltage could be measured as a feedback signal such that the controller can ensure that each step is completely finished before switching between the level states.

B. Externally Provided Offset Voltage
For a simplified analysis, it is assumed that one buffer capacitor is connected to an external buffer voltage source through a (highly resistive) resistor to slowly change the average voltages of the buffer capacitors to the desired values. This is the same as in the actual setup, where a resistor is also used for the current measurement from the power analyzer (see Fig. 13). The voltage change of the offset voltage buffer capacitor during one system cycle results from the average charging current I = (V C,0 − V 0 )/R through a biasing resistor between V 0 and V C,0 . The voltage change on the buffer capacitor during one system cycle, thus, is V 0 = (V C,0 − V 0 )/RC BUF f SYS .
The ratio of the system period f −1 SYS to the time constant RC BUF is substituted as b, and the ratio of the desired offset voltage to the dc input voltage is d = V C,0 /V dc such that V 0 = b(V C,0 −V 0 ) = bd V dc −bV 0 . Now, the time evolution of the state voltages is described by the modified (superimposed) matrix Fig. 20 exemplary shows the time evolution for V C,0 = 0 (d = 0) and b = 0.1. The offset buffer voltage is slowly charged to the desired value, and all other buffer voltages follow this change due to the previously described selfbalancing mechanism. This analysis demonstrates that the external biasing of one buffer capacitor allows introducing an arbitrary voltage offset to the circuit. As a result, the triangular voltage over a complete system period can be offset externally by an offset voltage V C,0 while maintaining the same maximum (peak-to-peak) voltage change V MAX = (V C,0 + V MAX ) − V C,0 . The biasing can be used either to realize unipolar load voltage operation between zero and V MAX (without offset) or to realize unipolar load voltage operation between a positive offset V C,0 and a positive voltage V C,0 + V MAX .

APPENDIX B POWER LOSS ANALYSIS OF THE SI-BASED MULTIPLEXER
The average conduction loss of two branches with one transistor and (N − 3) branches with two transistors is with an effective inductor current, which is at least increased to (2/ √ 3) times the average rectified capacitor charging current I for the trapezoidal current waveform from the hysteretic current control, and if the ZVS/valley current is around zero, which is desired to achieve low-loss zero voltage switching. Here, R is the ON-resistance of one multiplexer (Si) transistor. The bipolar blocking branches of the multiplexer are assumed to be implemented by two back-to-back transistors in this work. Equation (21) results in zero resistance for N = 2 (conventional half-bridge, no multiplexer required). For N = 3, the effective resistance of the multiplexer is the resistance of just one multiplexer switch R (since, to extend to a three-level circuit, no bipolar blocking branches are required, only two unipolar blocking switches as in a half-bridge are sufficient). For N → ∞, the circuit theoretically consists mainly of bipolar blocking branches and, thus, an effective resistance of 2R. For the later implemented N = 6 circuit, the effective resistance is 1.6R. The switching losses result from 2(N − 2) zero current but hard switching transitions in each cycle in voltage steps of V . The output capacitances C OSS of (N − 1) multiplexer transistors are paralleled during this switching transitions and cause To realize the same desired maximum load voltage change N ) with an increasing number of levels, the switching loss from (22) of the multiplexer stays constant despite an increasing number of paralleled switches required because the C OSS -related losses scales with the reduced voltage step squared, while the additional number of required paralleled switches only increases the capacitance linearly. The total switching loss of the multiplexer (23) thus does theoretically not increase with an increasing number of levels. However, the output capacitance C OSS of practical transistors is highly nonlinear, and practically, a minimum operating voltage of the main power converter is required to achieve high efficiencies, both limiting the number of levels to a small number. The gate driving losses for (2(N − 1) − 2) Si MOSFETs (gate charge Q G and drive voltage V G ) are The multiplexer is in (N −1) different states during a cycle, and the average leakage loss is estimated by the average of all transistors, with leakage current I lk , which are in the OFF-state which is P lk = 8I lk V for the six-level (N = 6) circuit.

ACKNOWLEDGMENT
The authors thank the reviewers and editors of IEEE Transactions on Power Electronics (TPEL) and IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRON-ICS (JESTPE) for their comments and suggestions that led to this article.