Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

This review paper assesses the main approaches in the electrical characterization of advanced MOSFETs towards their future analog and RF applications. Those approaches are shown to be different from the traditionally used ones for the assessment of the device perspectives for digital applications. Based on the original research realized by our group over the last years, advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as Fully Depleted Silicon-on-Insulator (FDSOI), FinFETs and NanoWires (NW) in a wide temperature range (from cryogenic, 4 K up to 250°C). A wide frequency band characterization (from DC up to hundred GHz range) will be positioned as a key element enabling a fair device assessment towards analog and RF applications. Importance of the “extrinsic” parasitic elements in the advanced devices is enormous, sometimes even dominating the device performance. Therefrom arises the need for a proper separate extraction and discussion of “intrinsic” versus “extrinsic” parameters.


I. INTRODUCTION
Enormous progress of the semiconductor technology during the last decades was mainly driven by the continuous demand for the increase of the operation speed and integration density of the complex digital circuits [1]. Another driver of the continuous progress is a demand for the reduction of the power consumption.
Aggressive device downscaling has requested the introduction of novel materials into the gate stack for its equivalent electrical thickness reduction in order to control short channel effects (SCE) while keeping leakage current low, as well as into the channel to boost carrier mobility (µ) and thus on-current and speed [1]. Hf-based dielectrics with equivalent oxide thickness (EOT) of ∼1 nm [2] are in use but new high-k dielectrics with k > 30 and EOT down to 0.7 nm are required for further scaling [1] with La silicate appearing as a strong candidate [2]. High-µ channels consist of strained Si [3] or use different crystal orientations [4]. For the next decade, radical change to Ge and III-V materials is under discussion for p-and n-type MOSFETs, respectively. For Si CMOS analog/RF applications, other new materials (e.g., low-k for spacers) and configuration solutions (e.g., faceted Source/Drain [5]) have been introduced to lower parasitics and thus boost analog/RF performance. In addition to novel materials, emerging device architectures come into play. Planar bulk Si MOSFET is no longer considered to maintain SCE control in transistors with a gate length shorter than 14 nm [1].
Technological aspects and "digital perspectives" of these novel devices were widely studied under standard conditions (i.e., static/low-frequency, room temperature and nominal voltages). This, however, is not sufficient, particularly for analog/RF applications, because emerging devices present some particular "defective" behaviors that are strongly temperature and frequency dependent, related to the reproducibility, interface quality, thermal effects, parasitic elements/couplings, etc. Fair scientific benchmarking of emerging devices demands an ability to properly assess device "intrinsic" or inner parameters appropriate to different process or architectural options separately from the "extrinsic" parasitic elements related to, e.g., contacts, technical limitations, etc. Appropriate characterization methodologies to assess the inner device parameters independently of any external influence must be employed to properly explore the physical phenomena in a relation to the main Figures of Merit (FoM) for further applications. In-depth characterization linked to the physical understanding of different phenomena becomes crucial for development of reliable models required by technologists for accurate parameter extraction and process optimization, as well as by circuit designers for a fair prediction of circuit operation and performance.
This article does not target to comparatively assess different advanced MOSFETs, but rather review methodological approaches enabling a fair assessment of novel device architectures for their analog and RF performance. Their exploitation will be demonstrated on selected study cases of various advanced devices in wide temperature and frequency ranges, performed in our laboratory over the last years [24]- [78]. In order to be complete, important works of other groups in the domain of device assessment for analog/RF applications are also listed [3], [10], [13], [23], [79]- [94].
The paper is structured as follows: Section II introduces main Analog and RF Figures of Merit (FoM); Section III is devoted to the DC-based characterization techniques; Section IV is about wide frequency band characterization; Section V focuses on the RF characterization, and finally Section VI gives short conclusions. We would like to note that while non-linearity, distortion and noise are also of high importance for the analog/RF applications, their discussion is omitted in this article due to lack of space.

II. ANALOG AND RF FIGURES OF MERIT
Main key-factors of any analog /RF MOSFET are: intrinsic voltage gain (A v0 ), that varies with frequency (as will be discussed in the following sections): and cut-off frequencies f T and f max : where R s , R d are parasitic access source and drain resistances, R g gate resistance, C gd and C gs are gate-to-drain and gate-to-source capacitances.
These key-factors depend on the device Figures of Merit (FoM), such as: transconductance (g m ), drive/drain current (I d ), output conductance (g d ), Early voltage (V EA = I d /g d ), transconductance over drain current ratio (g m /I d ), gate capacitance (C gg ), etc. Apart from the device geometry and layers' thicknesses, the FoM themselves are directly linked to inner device physics via mobility, short channel effects (SCE), body factor, etc. Furthermore, and particularly for the advanced devices, the above should be completed by parasitic resistive and capacitive elements.
If one considers applications at circuit level (e.g., amplifier), gain bandwidth product, GBW, is considered and, in turn, linked to the same device FoM (g m /I d and I d ): where C L is the load capacitance.

III. DC-BASED TECHNIQUES (OR TECHNIQUES BASED ON STATIC MEASUREMENTS) A. G M /I D TECHNIQUE
A very useful characterization approach which allows to have a first global appreciation of the device under study for analog application is plotting g m /I d as a function of normalized drain current I d /(W/L) (where W is gate width and L is gate length) [24], [28]. Such plot provides a complete view of the studied device, which is valid for different applications: from low-frequency or base-band, where high gain normalized to current and/or high precision are key FoMs, favoring device operation in weak/moderate inversion, to high-frequency application where high absolute gain is needed and therefore higher drive current is used, favoring device operation in stronger inversion (Fig. 1). From a practical point of view, it is worth mentioning that calculating g m /I d as d(lnI d )/dV g allows to improve precision and avoid numerical errors, particularly in a range of sharp current change in weak inversion, deep subthreshold regimes. In weak inversion regime, g m /I d is inversely proportional to the subthreshold swing, S. In strong inversion, it is proportional to µ·C ox /n (where µ is mobility, C ox is gate oxide capacitance and n is body factor). Therefore, g m /I d versus I d /(W/L) plot is independent of threshold voltage, V Th , and of its dependence on substrate/back gate (or body) bias, V bg . To the first order, it is also independent of device geometry (L and W) as long as effects of small dimensions are not significant. In addition to a visual comparative appreciation of different devices in a such plot, we can fix a certain g m /I d value (usually = 10 and/or 5 V −1 , which corresponds to mid-and strong inversion, respectively, i.e., gate voltage overdrives of 200 to 400 mV typical in analog/RF circuits) and extract the corresponding I d /(W/L) values as shown in Fig. 1. This allows to link the assessed device performance to the "inner", purely physics-related parameters as µ or body factor, thus providing a fair comparison of devices issued from different technologies, featuring different dimensions and operated at different bias or temperature conditions. Figure 2 provides some examples of the application of this technique to different devices under different conditions. Fig. 2a shows I d /(W/L) variation as a function of back-gate bias in UTBB FDSOI MOSFET [46] taken at a fixed g m /I d of 10 and 5 V −1 . Being extracted in such a way, I d is free from effect of V bg on V Th and it allows us to directly link the observed improvement of I d at positive back-gate biases to the mobility improvement. Indeed, negative V bg pushes the channel towards the top Si interface with high-k gate oxide, whereas positive one attracts it towards the bottom Si interface with a SiO 2 BOX, which is less defective than high-k interface so that higher mobility is obtained [36], [46]. Figure 2b gives the example of NWs, plotting I d /(W/L) extracted at g m /I d of 10 and 5 V −1 as a function of NW width [56]. One can see that while normalized I d is almost constant for "long" NW MOSFET, strong improvement is observed with NW width reduction in the case of "short" device. Being free from geometry and V Th effect, this behavior clearly relates to the improved control of short-channel effects in the narrow NWs. It is worth pointing out that these NWs are almost square/ -like, with sidewall height of 10 nm that is relatively small compared to the NW width (narrowest device is 17 nm-wide only). Therefore, the usually observed [39], [83], [91] I d (and g m ) improvement with increase of NW (or Fin) width, related to the mobility improvement when conduction is dominated by the top-plane w.r.t sidewalls, almost does not appear in these devices featuring a complex 3D conduction. More details can be found in [56]. Fig. 2c shows effect of "strain" introduced into the channel of SOI-based FinFETs on g m /I d versus I d /(W/L) curve [58]. One can see that while effect of strain is beneficial in the strong inversion region (due to targeted µ improvement), some degradation is observed in the weak inversion regime (due to weakened SCE control). Therefore, depending on the target application, either high-frequency/high-current, or baseband (high-precision, gain), one would choose device with strain or without, respectively. Finally, Figure 2d demonstrates effect of temperature down to 4.2 K on g m /I d versus I d /(W/L) plot [62], [64]. Temperature lowering is seen beneficial both in weak inversion (due to subthreshold slope improvement) and in strong inversion (due to mobility improvement), and thus for both base-band and high-frequency applications.
Apart usefulness of g m /I d technique for linking device performance to the physical background, the g m /I d technique has been recently proposed for V Th extraction [41], proving its efficiency and advantages particularly for advanced devices [42]- [44], [75]. This technique extracts V Th as position of extremum of g m /I d derivative with respect to V g , which was shown to coincide with the position of the extremum of the second derivative of the inversion charge (or surface potential) and thus provides the V Th values linked to the device physics. Furthermore, this method was shown to be robust against mobility variation with V g [42]; to be applicable in both linear (low V d ) and saturation (i.e., high V d ) regimes [43]; and to provide consistent physics-related values at different temperatures [44] and for different emerging devices as, e.g., Junction-Less (JL) NW FETs [75].

B. G M -A V ANALOG METRIC
Another useful approach allowing quick visual assessment of advanced devices for analog/RF applications is the g m -A v plot introduced in [46]. In this plot each point represents one device with concrete L and the group of such points for different L forms a trend. For the analog applications one wants both g m and A v be as high as possible, i.e., with the points moving to the right and to the top and with a steep trend-line. g m -A v metric for analog/RF applications can be seen as analogue to the famous I on -I off plot for digital applications. Using g m -A v plot, one can either compare different technologies, or see effect of different biases, temperature conditions, etc.
It is important to note that these plots can be generated either at a bias condition desired for the target applications (and in this case, we assess the suitability of a concrete device/process for concrete application) or at a constant gate voltage overdrive, i.e., V g -V Th (and in this case, have a link to the device physics). In the latter case, a physical and robust technique for V Th extraction, as, e.g., introduced in previous section g m /I d technique [41]- [44], [75], is crucial. Figure 3 gives a couple of concrete examples of g m -A v technique application on advanced MOSFETs. Figure  3a shows effect of NW width with a clear improvement of the device performance both in terms of g m and A v in "narrow" NWs comparing to their wide counterpart [56]. This is because of improved control of the SCE and "volume inversion" (i.e., when the whole Si film is inverted) operation regime in the "narrow" device. This improvement was possible to achieve since degrading effects often appearing with NW narrowing, such as, e.g., increased R s/d , interface quality and µ reduction, were well tolerated [50]. One can also note the loss of control and performance degradation in short-channels of wide-NW devices. Figure 3b demonstrates effect of temperature on g m -A v metric revealing strong device performance improvement with temperature reduction. g m values are strongly improved thanks to mobility enhancement at cryogenic temperatures, particularly in a "long"-channel devices; slight improvement of A v is also observed (more details can be found in [56]). Effect of the back-gate bias in UTBB FDSOI is shown in Fig. 3c. It evidences that depending on the target application, one will choose either "negative" (for the high g m and hence high frequency application) or "positive" (for the high-gain, highprecision applications) back-gate bias [51]. This trade-off derives from competing trends in the g m and A v responses to the V bg , e.g., "negative" V bg attracting the channel to the Si/BOX interface and thus assuring higher mobility (as already mentioned above), drives it away from the control of the top gate and thus worsens control of SCE, which in turn results in degraded V EA and A v . A way to get improvement of both g m and A v in UTBB FDSOI devices is to simultaneously bias and sweep the top and bottom gates, as shown in Fig. 3d, in a so-called Asymmetric Double Gate (ADG) with V g = V bg [48] or Quasi-Double Gate (QDG) [49], [50] with V bg = k × V g (k>1) regimes. In addition to the V Th modulation, improved I on and I off , exploitable for digital applications, these regimes allow for improved g m and I d combined with a lower drain induced barrier lowering (DIBL) and hence higher V EA and A v , thus potentially exploitable for analog applications.
A last example of g m -A v application shows effect of frequency on this metric (Fig. 4) [48]. One can see improvement of g m and degradation of A v with frequency increase. The latter occurs because the increase (i.e., degradation) of g d (see next section) is stronger than that of g m , thus dominating A v . Various non-stationary effects, such as floating body, self-heating, substrate coupling, etc. appear in different frequency ranges introducing frequency response (dependence) in g m , g d and hence A v . Therefore, performance prediction based on the DC data only is clearly insufficient (and can be even misleading) for further analog/RF applications, wherefrom a quest for a detailed wide-frequency band characterization is discussed in next section.

IV. WIDE FREQUENCY BAND CHARACTERIZATION
At the beginning of this section, it is directly worth to emphasize that wide-frequency band characterization as well as RF characterization (discussed in Section V) request the availability of adequate test structures with coplanar waveguide (CPW) RF probe pads. As such characterization techniques open a way not only for performance assessment, but for an in-depth analysis of physical behavior, it is advised to include these specific structures in the layout of test chips, from the very beginning of the technology development.

A. NON-STATIONARY EFFECTS RESPONSE IN A FREQUENCY DOMAIN
The frequency response of the output conductance of the MOSFET can be presented in a following form: Various effects contribute to the g d frequency response: g d,in is an intrinsic term present in any MOSFET, constant with frequency, related to the channel length modulation and DIBL (i.e., corresponds to DC extracted value). g d,FB is the g d variation related to the floating body effect. g d,SH is related to the self-heating (SH) effect; g d,SUB is related to the frequency response of the coupling through the substrate (or SUB). Other effects can be added. It is worth pointing out that g d terms can have both "positive" or "negative" sign, depending on the device and its operation regime. Figure 5 provides an example of g d (f) variation in UTBB FD SOI MOSFET without ground plane (i.e., a highly doped region implemented in the Si substrate just below the BOX to provide a back-gate contact) [47]. In practice, g d is calculated as the real part of Y dd admittance which in turn is extracted from S-parameters measured in a wide-frequency range after de-embedding [54] (see inset in Fig. 4). Floating-body effects can be to the first order neglected in such thin-film FD devices. However, both SH and SUB related transitions clearly appear in the g d frequency response. Frequency response of SH (or dynamic SH) effect is well-known to appear because at a certain frequency, acoustic phonons (and hence lattice temperature) cannot follow a.c. excitation. Less-known frequency response of coupling through the substrate, or so-called "substrate effect", is related to the frequency variation of the substrate capacitance, C sub , when, with a frequency increase, first minority (in tenshundreds Hz range) and then majority carriers (in GHz  range) in the substrate stop to follow the a.c. signal and C sub decreases [27]. This can be represented, to the first order, as two RC networks. Variation of C sub results in a variation of potential at Si/BOX interface which translates in a g d variation (more details can be found in, e.g., [27]). Figure 6 gives a synthetic overview of SH and SUB effects evolution in advanced devices detailing impact of length scaling, Si film thickness and Fin (or NW) width reduction as well as BOX thinning on these effects. One can see that in advanced deeply scaled devices both effects are strongly exacerbated. Moreover, trade-off between SH and SUB effects exist as, e.g., fin width reduction enhances SH but reduces coupling through the substrate and thus depending on the application and bias conditions one or another architectural solution can be preferential. Figure 5 evidences a strong, 2-to-5-fold, degradation of g d over a frequency range, which is an important bottleneck for analog applications and designers. Next to that, it is worth emphasizing that in the thin FDSOI devices with a thin BOX which did not incorporate ground plane, SUB-related transition was as strong as SH one, and at a certain regime (e.g., at lower V g ) even stronger than SH one (Fig. 5) [47]. This is because BOX thinning eases heat evacuation towards Si substrate, whereas it enhances the electrical coupling through the substrate.
From the example given in Fig. 7 one can see that the introduction of a Ground Plane (i.e., highly doped layer in the Si substrate, just underneath the BOX) allows for a strong

FIGURE 8. Normalized intrinsic gain as a function of frequency in UTBB FDSOI MOSFETs [45] and FinFETs [76].
reduction of the SUB-related variation of g d [45], [54]. Thus, SH stays the main reason of analog performance degradation in advanced devices, being in UTBB FDSOI [45] or SOIbased FinFETs [76] (Fig. 8), at high bias voltage and current, i.e., power density and hence Joule heating dissipated in the device. In order to reduce SH effect, beyond using lower biases, different solutions as, e.g., optimization of device geometry, further oxide thinning, use of high thermal conductivity materials, etc. can be envisaged. Furthermore, use of a sink implemented in the back end of line (BEOL) was recently demonstrated to allow for a 20-30% improvement of SH features [74], giving additional freedom for the circuit designer optimization without the need of technological process modification.

B. SELF-HEATING ASSESSMENT
However, SH-related g d variation in a frequency range can be seen not only as a drawback for analog design but also as a tool for extraction of SH features: thermal resistance, R th and temperature rise in a channel, T. Knowing the amplitude of the SH-transition, g d,SH , low-frequency values of g d value and temperature dependence of the drain current (dI d /dT a , where T a is ambient temperature, obtained from complementary measurements), R th can be extracted as: Knowing R th , channel temperature rise is then easily calculated: While basics of this technique were introduced a long time ago [79], its advantages become further pronounced particularly for the advanced devices, with a strongly decreased volume-to-surface ratio. This is because thermal resistance is inversely proportional to the heat evacuation surface, while thermal capacitance C th is proportional to the volume available to store the heat and thus characteristic frequency f th (= 1/(2.π .R th .C th ) is inversely proportional to the volume-to-surface ratio and shifts towards higher frequencies in advanced device architectures. An example given in Fig. 9 shows that the f th can reach the hundreds of MHz range in advanced FDSOI MOSFET. Alternative pulsed I-V technique widely used for the SH extraction (based on the application of the short pulses to avoid device heat) fails in this range of characteristic frequencies (or time constants). Presently, to the best authors knowledge, there is no technical solution allowing on-wafer realization of the pulse technique with well controllable pulses in the ∼ 1 ns range. As indicated in Fig. 9, pulsed I-V technique may strongly underestimate SH in advanced devices [59], [68]. Furthermore, this underestimation or inconsistency will be dependent on the studied device architecture, dimensions, bias and temperature conditions. For example, benchmarking of bulk and FDSOI devices in view of SH features may be wrong even in relative values, because characteristic SH frequency is lower in bulk devices (about an order of magnitude [59]) and thus pulse I-V technique can provide lesser underestimated values. Figure 10 gives an example of comparative assessment of FDSOI vs bulk devices from the same 28 nm technology node in a wide frequency range [59]. In spite of a stronger self-heating in the FDSOI devices (Fig. 10a), they outperform the bulk counterpart (Fig. 10b) in the entire frequency range. It is worth pointing out that only wide frequency range allowed in this case a fair benchmarking: as can be seen in Fig. 10b, the improvement provided by FDSOI devices

FIGURE 11. Normalized output conductance(a) and intrinsic gain (b) as a function of frequency in FDSOI MOSFETs at different temperatures [65].
estimated from low-frequency values (squares) is larger than that extracted from high-frequency values (triangles). Figure 11 gives an example of wide-frequency band assessment of analog FoM with temperature reduction down to 77 K. The overall increase of analog FoM (g m , g d , A v ) with temperature lowering extracted from DC measurements (shown in Figs. 2 and 3) stays valid in a wide frequency range. Moreover, SH-induced degradation of analog FoM is slightly attenuated at cryogenic temperatures [65]. Thermal time constant is further reduced with temperature lowering and thus wide-frequency technique (we often cite it as "RF technique", because it requires measurements up to GHz range) for SH features extraction becomes even more relevant. It is worth to emphasize that the channel temperature is particularly different from the ambient one at cryogenic temperatures, which is crucial for modeling.
It should be pointed out that SH assessment based on equations 5, while allowing the extraction of main features, is a simplified approach. It models SH by a simple R th , C th thermal network. However, in real device, different heat evacuation paths co-exist (via BOX, via gate, via source/drain and vias, . . . ) and thus a higher order thermal network needs to be involved for more advanced and accurate thermal representation and modeling. Detailed investigation of thermal behavior would request for a combination of experiments with simulations and modeling to allow the extraction of different R th , C th components related to each path. This would also request for detailed information about BEOL (back end of line) architecture (layers, thicknesses, etc.), as well as to include die-level or package-level boundary conditions. More detailed discussion is however, out of scope of this article.

C. PARAMETERS EXTRACTION
Ability to extract main device parameters, such as, e.g., threshold voltage, mobility, etc. which are "free" from the non-stationary effect is very important for the development of fair predictive models. Wide-band frequency measurements allow such possibility. Fig. 12 gives an example of the mobility extraction in partially-depleted SOI MOSFETs strongly affected by gate-induced floating body effect (GIFBE) [92] (or linear kink effect [93]) which appears as a jump in the transconductance curve, thus disturbing correct mobility extraction using standard techniques (either from maximum of g m , or Y-function, or split C-V). Wide-band frequency characterization revealed that GIFBE effect features a characteristic frequency response with a cutoff frequency in the range of hundred kHz [78]. Figure 12a shows that in g m extracted from a 1 MHz S-parameters measurement, this effect is suppressed. Therefrom modified split C-V technique [38] which uses integrals of g m (instead of DC I d in a traditional split C-V) and capacitance measured at very high frequency was proposed: Figure 12b demonstrates the advantages of the application of this revised technique w.r.t "standard" one in terms of the reliable values extraction: smooth mobility curve, without "overestimation" related to GIFBE is extracted.
This approach can be generalized and successfully applied to extraction of main MOSFET parameters unaffected by the non-stationary effects.

V. RF CHARACTERIZATION
When device length is scaled down, importance of parasitic components increases enormously. As we will see later in this section, parasitic elements can even dominate the device performance. This is particularly the case for advanced device architectures with thin-film, 3D geometry (as FinFETs and NWs) or stacked devices. As already mentioned in Section II, different parasitic components (Fig. 13a), as parasitic access resistances and various parasitic coupling capacitances (vulgarized in Fig. 13b along with intrinsic capacitance components) affect the device perspectives for analog/RF applications. In advanced present technologies, the ability to separately extract "intrinsic" and "extrinsic" elements becomes crucial, because: (i) it allows to predict "intrinsically" achievable (or idealistic) device/process values, i.e., the limit one can reach with full optimization of parasitic elements; (ii) for the process/architecture optimization, it is crucial to know whether the deficiency in the performance originates from the "intrinsic device" (and thus one needs to work on optimization of interfaces, channel, µ, gate stack, etc.) or from "extrinsic parasitics" (and thus, the focus of optimization would be on spacers, access resistances, etc.). Extraction of a complete equivalent circuit (including and separating "intrinsic" and "extrinsic" components) demands S-parameters measurement in a wide frequency range up to a hundred GHz. Hence, adequate structures with RF access pads must be included in the layout from the very start of the technology development. Detailed procedure for the extraction of "intrinsic" and "extrinsic" elements of the equivalent circuit shown in Fig. 13 can be found in [61], [77]. Due to the limited space we do not provide it in this article. Figure 14 exemplifies the above discussion in the case of FinFETs and their planar bulk counterpart [35]. "As measured" (i.e., including extrinsic parasitics) and "intrinsic" (i.e., after withdrawing of parasitic elements) values are shown. Firstly, difference between "intrinsic" and "as measured" values increases with device length reduction and is further enhanced in FinFETs w.r.t bulk counterpart. Secondly, it is interesting to point out that very similar "intrinsic" values are achievable in the case of planar and FinFET devices, whereas measurable values (i.e., those which include both intrinsic and extrinsic elements) are much lower in FinFETs comparing with the planar counterparts. Detailing various parasitic components, it was concluded that apart from the effect of R g on f max , the major degradation comes from C inner , which is the sum of fringing capacitances directly linked to the FinFET 3D architecture, contributing to ∼60% of f T and 30% of f max degradation (w.r.t intrinsically achievable values). Effects from R s,d and C outer (related to the feed connection outside the active area) were relatively small in these devices. The largest part of C inner was shown to be due to the 3D coupling between source/drain side walls and the gate wrapping the fin, with some architectural optimization proposed in [76].   Figure 15 gives an example of the effect of parasitic elements on the RF performance of UTBB FD SOI devices. In this figure we show both early-stage UTBB FDSOI technology development at Leti [55] and its more mature industrial version at ST-Microelectronics [6], known as 28FDSOI [61]. One can see a strong role of parasitic elements on the device performance, particularly in "shorter" devices. Series resistance being almost constant versus L, has, nevertheless, naturally stronger impact on the g m of shorter-L devices. Extrinsic parasitic capacitance, C gg,e , also stays almost the same for different gate lengths, so that at it becomes higher than intrinsic component (which scales proportionally to L) and thus dominates in the total C gg (Fig. 15b). Figure 15 shows that process optimization allowed for an improvement (reduction) of both capacitive and resistive parasitic components: R sd is about twice lower and C gg,e is 1.5 times lower in the case of the more mature version. Such reduction of parasitics results in a strong improvement of RF performance with f T increase of ∼100 GHz. Recently, f T values as high as 360 GHz for 30 nm-long device [69], compatible with ITRS requirements for low-power applications, were reported achievable in this technology with further device/process optimization. Figure 16 gives another example case, namely RF performance evolution in the cryogenic temperature range, when separate extraction was important for the proper device modeling [64]. Strong improvement of RF FoMs (∼130 and 75 GHz for f T and f max , respectively, for 25 nm-long FDSOI device) is evident with temperature reduction (Fig. 16a). This improvement was detailed to be related mainly to the mobility, and hence intrinsic g m increase (∼40%) and additionally for f max due to the R g reduction, whereas other parasitic elements exhibited only slight temperature dependence (Fig. 16b).

VI. CONCLUSION
This article reviewed the appropriate characterization techniques and methodologies that allow fair analysis and benchmarking of advanced devices linked to the device physics and operation conditions. Wide frequency band analysis was pointed out as a key element for the fair assessment of different devices and understanding of physical phenonema impacting their behavior and performance. Separation of "intrinsic" and "extrinsic" parasitic elements and related performance impacts was emphasized to be mandatory in downscaled devices with advanced architectures, to guide both device/process optimization and parameter extraction for modeling.