Investigation of Electrical Property and Thermal Stability in Enhancement-Mode InxAl1–xN/AlN/GaN MOS-HEMTs Fabricated by Using NiOx Gate and Fluorine Treatment

In this study, we report a novel approach for achieving high-performance enhancement mode (E-mode) InAlN/GaN MOS HEMTs based on the fluorine treatment and a p-type NiOx gate (F-NiO HEMT). The NiO film was deposited at different substrate temperatures using reactive sputtering in a varied mixture of O2 and Ar. We show that the threshold voltage <inline-formula> <tex-math notation="LaTeX">$({V}_{TH}$ </tex-math></inline-formula>) is effectively modulated by comprehensively optimizing fluorine ion implantation and NiO sputtering conditions without requiring gate recess etching. The influence of different NiO deposition conditions on electrical properties and the critical interface of NiOx/InAlN have been investigated in detail. The proposed E-mode F-NiO HEMT exhibits superior on-state characteristics, including more positive <inline-formula> <tex-math notation="LaTeX">${V}_{TH}$ </tex-math></inline-formula>, enhanced gate voltage swing, larger transconductance <inline-formula> <tex-math notation="LaTeX">${g}_{m}$ </tex-math></inline-formula> and also superior gate control over the channel. The dual C-V and pulsed mode measurements confirm the excellent NiOx/AlInN interface and effective suppression of current collapse. We propose a model to explain the contrasting temperature-dependent coefficients of <inline-formula> <tex-math notation="LaTeX">${V}_{TH}$ </tex-math></inline-formula> shifts observed in pure fluorine ion-implanted and NiO-based devices. The underlying mechanisms at elevated temperatures are also analyzed.


I. INTRODUCTION
The GaN-based heterostructure high electron mobility transistors (HEMTs) incorporating indium (In) components have attracted considerable research interest featuring enhanced polarization effects and reduced barrier layer thickness [1], [2], [3].As compared with the conventional D-mode devices, to broaden the range of applications, the development of E-mode GaN HMETs is crucial.These E-mode HFETs play a crucial role in microwave circuits, simplifying circuit design, and minimizing losses associated with passive components in high-frequency ranges.Converting D-mode to E-mode HEMTs is also desirable for the development of monolithic integrated functional circuits [4], [5], [6], [7], [8].For conventional GaNbased HEMTs, various methods have been implemented to achieve E-mode operation, including fluoride-based c 2024 The Authors.This work is licensed under a Creative Commons Attribution 4.0 License.
For more information, see https://creativecommons.org/licenses/by/4.0/104 VOLUME 12, 2024 plasma treatment [4], Al x Ga 1-x N back barrier [9], different gate metallization [10], recessed gate [11] and p-type gate [12], [13], [14].Nevertheless, when considering In x Al 1-x N/GaN heterostructure, the elevated 2-DEG density (∼10 13 cm −2 ) arising from spontaneous polarization presents challenges for effective channel depletion.Therefore, the well-established fabrication processes for E-mode devices on AlGaN materials require specific optimization when applied to InAlN materials.The utilization of fluorine ion implantation has been considered as a viable approach to achieve E-mode devices for In x Al 1-x N/GaN-based HEMTs [15], [16].However, pure fluorine ion implantation under the gate is known to cause threshold voltage drift and instability issues, particularly at high temperatures.Hong et al. [17] investigated the role of fluorine in GaN HEMTs and revealed the origin of thermal instability of F-treated HEMT using first-principle calculations.The study highlights the critical role of precise control over both plasma conditions and interfacial charge for achieving a stable threshold voltage.The development of enhanced MOS-HEMTs with larger gate voltage swings has recently garnered attention.Promising gate dielectrics, including Al 2 O 3 [18], [19], [20], TiO [21], and Al x Ti 1-x O [22] have emerged due to their ability to reduce gate leakage and enable larger gate swings, which are critical for RF power applications.Those conventional dielectrics require the recessing of the barrier layer under the gate stack, which to some extent affects the channel mobility and device performance.On the other side, obtaining high-quality, uniformly doped p-GaN materials for E-mode devices is still challenging due to the requirement of precise etching outside the gate region [23], [24], even slight errors in the etching process can greatly impact device performance.This situation becomes more pronounced for InAlN HEMTs with thinner barriers.Another approach to achieving Emode operation is to utilize p-type oxides such as CuO [25] and NiO x [26], [27].Recent research has highlighted the effectiveness of those specific oxides in effectively shifting of V TH in GaN HEMTs.i.e., NiO x as a suitable p-type oxide semiconductor has been successfully employed in the fabrication of p-type NiO-based thin-film transistors through Ni film oxidation.Studies conducted by [28] and [29] have implemented the NiO x layer as an insulating layer, whereas [30] has also demonstrated its application as a p-type gate.A high-performance E-mode InAlN/GaN MOS HEMTs is anticipated to be achieved through the combination of fluorine treatment with NiO x deposition.
High-temperature characteristics and thermal stability are critical considerations for E-mode HEMTs.The temperature dependence of planar-integrated E/D-mode AlGaN/GaN HEMTs was extensively investigated by Wang et al. in [31], revealing that F-treated HEMTs maintain V TH stability during high-temperature operation.Reference [32] proposes a vacancy-assisted diffusion model to elucidate the mechanism behind fluorine ion diffusion in bulk GaN and corresponding thermal stability.Although the physics of 2DEG channel depletion and thermal reliability for fluoride ion implantation are well established [31], [33], featuring with thinner barrier, the electrical performance of enhanced InAlN/GaN MOS-HEMT integrated with NiO film deposition has rarely been reported.The understanding of trap charge states at the NiO/InAlN interface and their influence on both electron trapping dynamics and thermal reliability needs to be clarified more in detail.
In this study, different types of HEMT devices were fabricated on lattice-matched (LM) InAlN/GaN epitaxial substrates.We demonstrate a high-performance E-mode of LM In x Al 1-x N/GaN HEMT through a combination of fluorine treatment and p-type NiO x gate.The fabrication process is described in Section II.An adequate modulation range of threshold voltage is achieved by comprehensively regulating fluorine ion implantation and NiO sputtering conditions without requiring gate recess etching.We perform a detailed investigation of the electrical properties affected by varying NiO deposition conditions and the critical NiO x /InAlN interface in Section III.The distinct behaviors and underlying mechanisms of V TH shift under higher temperatures have been carefully analyzed.We summarize the main findings in Section IV.

II. DEVICE FABRICATION AND STRUCTURE
The LM In x Al 1-x N/AlN/GaN epilayer with In fraction of around 18% was grown on SiC substrates using metalorganic chemical vapor deposition (MOCVD) with the detailed structure given in our previous work [1].Four different devices were fabricated on the same wafer substrate, including conventional depleted (MS HEMT), pure fluorine ion-implanted (FII HEMT), NiO x -based (NiO HEMT), and fluorine treatment combined with NiO x gate (F-NiO HEMT).The device's fabrication started with the cleaning of the epitaxial wafer by a standard solvent.Then, devices were isolated using BCl 3 and Cl 2 etching in an Inductively Coupled Plasma (ICP) system.Before the deposition of ohmic metal, surface treatment was performed by immersing in BOE for 60 seconds.The Ti/Al/Ni/Au metal stack was then deposited by E-beam evaporation [34].Rapid temperature annealing (RTA) at 830 • C for 30 seconds in a N 2 ambient was then performed to form Ohmic contact.For fluoride-based HEMTs, after defining the device's gate and interconnection patterns, the samples were subjected to CF4 plasma treatment in an RIE system, with a source power of 100 W for 180 s.The Ni/Au gate electrode, with a uniform thickness of 50 nm/250 nm, was then deposited using electron beam evaporation for all samples.Differing from FII HEMT and MS HEMT, a 12 nm p-type NiOx film was formed by reactive sputtering in an Ar: O 2 (3:1) mixed gas ambient environment under 4 mtorr using a Ni metal target before Ni/Au deposition for F-NiO HEMT.We use AFM to confirm the thickness of deposited NiO x as the result given in Fig. 1d.The sputter-induced damage and plasma-induced damage are repaired using rapid thermal annealing to restore the performance of the device.In this work, postdeposition annealing was conducted at 400 • C for 5 min to improve the contact quality between the sputtered metal layers and the metal/InAlN interface, as well as to activate fluorine ion.Nitrogen is utilized as the annealing gas atmosphere.This treatment serves to strike a balance between performance restoration and threshold voltage stability for the E-Mode devices under consideration.Note that when the annealing temperature increases to 500 • C, the threshold voltage experiences a rapid reduction, leading to a loss in the enhancement mode of the device [33], [35].The space of gate-to-source and gate-to-drain are 10 μm and 30 μm respectively.The gate width and length are 100 μm and 3 μm respectively.The device cross-section views of FII HEMT and F-NiO HEMT are displayed in Fig. 1 A typical X-ray diffraction pattern result of NiO film deposition is shown in Figure 2, and the inset shows more detailed results under different NiO deposition conditions.We observed five peaks at ∼36.9 • , 42.9 • , and 62.4 • , 74.7 • , 78.7 • , which correspond to the face-centered cubic crystalline diffraction patterns of (111), ( 200), ( 220), ( 311) and ( 222) respectively [36].It is widely believed that the non-stoichiometric ratio of (111) orientations within the NiO x structure is associated with the nature of the p-type extrinsic semiconductor of nickel oxide.A remarkable (200) orientation of the NiO film is also observed.More specifically, at a substrate temperature of approximately room temperature, the (111) crystal plane diffraction peak slightly exceeded the (200) peak.With an increase in substrate temperature, the (111) diffraction peak diminished, while the (200) peak intensified.The result suggests that NiO deposited at lower temperatures might undergo insufficient reaction, leading to an abundance of nickel vacancies and excess oxygen.With the elevation of the substrate temperature, along with a more complete interfacial chemical reaction, a decrease in the carrier concentration and a rapid increase in material resistivity were observed.This explains the reason for the lower gate leakage current in NiO-based HEMT as shown in the following section.We confirmed the ptype semiconducting behaviors of NiO x film by studying the electrical properties using the Hall measurement.Taking the NiO film deposited at room temperature with an Ar:O 2 (3:1) mixed gas environment for example, the estimated values of the electrical resistivity and concentration of the holes were approximately 3.98 -cm and 3.74×10 18 cm -3 , respectively.The Hall mobility, which is relatively low at approximately 4.18 cm 2 V -1 s -1 , falls within the range reported by various studies [37], [38].

III. RESULT AND DISCUSSION
The band diagram of a typical InAlN/GaN MOS HEMT with and without fluorine treatment is given in Fig. 3a.Taking the effects of charge polarization, surface trap, and corresponding band offset into account, the threshold voltage of the F-NiO HEMT can be approximately expressed as where E c conduction band offset at the heterostructure, q the electron charge, ρ t the effective polarization charge due to strong spontaneous polarization effect at InAlN/GaN, , t b , t ox are the thickness of the LM In x Al 1-x N barrier and NiO dielectric layer respectively, and is the corresponding dielectric constant, qN t is the interface trap charge the NiO/InAlN, qF − = d 0 N F (x)dx represents the effect of the fluorine ion (negatively charged) calculated by integrating the total fluorine concentration throughout the effective barrier layer.Note that in the absence of NiO x deposition, which is the case of FII-HEMT, the third term of Eq. (1) will be omitted and tends to be approximately simplified to the formula given in [33].For the FII HEMT treated by CF4 plasma at 100 W for 180 s, a threshold voltage shift of approximately + 2.23 V was observed as compared with MS HEMT (see Fig. 3b).This amount of shift can be associated with a Gaussian-like distribution of fluorine ion concentration, which peaks at 1×10 19 cm −3 and extends roughly 15 nm from the barrier surface [32], [39].The presence of F ions away from the 2DEG channel is considered to be negligible.Note that the epitaxial structure and corresponding physics parameters used in Eq. ( 1) were based on our previous work [1], and the doping concentration of the GaN substrate was assumed to be negligible (unintentional doping).Compared to conventional AlGaN/GaN, the InAlN/AlN/GaN interface has a higher charge density (2.03×10 13 cm −2 ) due to its stronger spontaneous polarization strength.However, this amount of F-ion distribution can still effectively deplete the 2DEG density at the interface, and thus shift the device threshold voltage to the positive direction.Furthermore, as seen from Fig. 3b, with the increase of CF4 plasma treatment time, a rapid decrease in transconductance was observed experimentally, accompanied by a rapid increase in gate current.This indicates that the F-ion injection process needs to be carefully optimized for InAlN/GaN HMET with thinner barrier layers.
Analogous to the typical p-GaN gated normally-off mechanism, the combination of p-type conductivity and high conduction band offset between NiO and InAlN efficiently raises the interface potential, resulting in a decrease of the 2DEG and a subsequent positive shift in the threshold voltage.Figure 4 illustrates the transfer characteristics and transconductance of HEMT devices with a p-type nickel oxide (NiO) gate electrode deposited in the gate region under different sputtering conditions.Compared with the MS device, the threshold voltage of the NiO-gated device shifts positively from approximately -3.2 to -0.5 V, as shown in the transfer characteristics.As for F-NiO HEMT, experimental observation revealed a transconductance g m value of 135 mS/mm (slightly lower than that of the MS HEMT) and a threshold voltage of +1.05 V, demonstrating superior DC characteristics.
We attribute the variation in NiO film electrical properties to the changes in the film's resistance characteristics under different deposition conditions [27], [37], [40], [41], [42] Recognized as a p-type semiconductor, the resistivity of nickel oxide film has its resistivity highly dependent on the concentration of cation (Ni) vacancies (also refers to the result of XRD given in Fig. 2).At lower substrate temperatures, the reaction between Ni and O 2 is less complete due to the reduced availability of active oxygen species resulting from the plasma decomposition of O 2 in the sputtering process.This leads to an increased concentration of Ni vacancies in the film, thereby increasing the number of holes and hence, reducing the resistivity [38], [41].Conversely, as the substrate temperature rises, the film contains fewer Ni vacancies than that deposited at a lower temperature, resulting in fewer holes and increased resistivity.Devices fabricated under high-temperature deposition conditions show greater transconductance degradation than those fabricated under low-temperature.Li et al. [38] reported the phenomenon of deteriorating quality of NiO when the oxygen content percentage increases to around 50% -60%.This may be correlated with the increase in surface roughness of the NiO layer.As seen from Fig. 4, the NiO film deposited at approximately 25 • C, with an oxygen partial pressure of 33%, exhibits the lowest resistivity and satisfactory crystalline quality, making it suitable for use as a gate electrode in NiO-based InAlN/GaN HEMT.Unless otherwise specified, this process will be employed for the fabrication of NiO-based devices.
Figure 5 shows the output characteristics of different device types and the transfer characteristics of all the devices at V ds = 10 V is given in Figure 6.The measured specific on-state resistances were 0.6665 .mm 2 and 0.6536 .mm 2 for FII HEMT and F-NIO HEMT, respectively.The main parameters of the different types of devices are summarized in Table 1.Note that the peak of g max is extracted at V DS = 10 V, the gate leakage I G is extracted at V GS = −10 V, the I dmax is extracted under the stable gate voltage within the saturation region, and the V TH from the transfer characteristics using linear extrapolation.
As seen from Fig. 5, for the F-NiO HEMTs, I dsat of 533 mA/mm is achieved at an enlarger gate swing V GS =5 V, with the extracted equivalent resistance R on of 15.2 -mm (R on ∼ 14.1 -mm,@V GS =2 V as for MS HEMT).A higher transconductance g m was observed experimentally as compared to the FII HEMT.The increase of g m might also lead to the enhancement of low-field mobility and a corresponding decrease in the equivalent resistance as indicated in Fig. 4. The combination of ionized F ions and p-type NiO x enhances the depletion effect of the 2-DEG at the interface of oxide/InAlN, leading to a more positive shift of V TH as shown in Fig. 6.A decrease of more than two orders of magnitude in gate leakage current was observed compared to depletion-mode HEMTs.The NiO xbased HEMT with F ion implantation exhibits a positive shift of more than +4 V and minimal degradation in the current characteristics as compared with MS HEMT.The off-state leakage current of F-NiO HEMT is found to be an order of ∼10 −8 A/mm at V GS = 10 V, indicating complete turnoff of the device and achievement of E-mode.Unlike other normal dielectric materials such as SiO 2 , SiN x , or Al 2 O 3 , the incorporation of p-NiO x a proper gate dielectric in InAlN/GaN MOS-HEMTs not only decreases the gate leakage current but also results in a more shift of V TH .This phenomenon could be associated the (200) orientation of the high resistivity NiO film, as evidenced in Fig. 2. the subthreshold swing (SS) extracted for MS HEMT, NiO-HEMT, and F-NiO HEMT around 208, 112, and 95 mV/decade, respectively, demonstrating good gate control capability of the devices.To investigate the interface properties between the gate and different barrier layers, we fabricated a 200 μm diameter circular Schottky diode structure (Fig. 7b).The dual C-V sweep method was employed to analyze trap states at the interface [43].Fig. 7 shows the dual C-V sweep characteristics of different devices at 1 MHz.The measurement was conducted with the voltage ranging from -8V to 3V, with a 0.3V AC small signal superimposed on the DC voltage.It is found that both the MS and F-NiO structures show almost negligible hysteresis, indicating excellent interface properties of these structures.Moreover, the trap states induced by fluorine implantation are effectively mitigated by the gate post-annealing process.It was found that the negative charge density at the InAlN interface can be effectively modulated through fluorine ion implantation or deposition of nickel oxide gate.The p-type nickel oxide gate device, when compared to the MS structure, exhibited a decreased total capacitance due to the series connection of equivalent capacitance of NiO and the gate capacitance.The fluorine-implanted sample showed a voltage hysteresis of approximately 0.13V in the dual sweep curve, accompanied by an increase in total capacitance C tot .This can be attributed to the slight etching effect of fluorine implantation on the barrier surface, resulting in a reduced distance between the gate and barrier layer.The ionization of fluorine ions introduces a substantial negative charge, thereby enhancing the barrier layer's total charge and corresponding capacitance.
The pulsed mode I d -V gs measurement [44] was employed for more accurate extraction of interface states following the method previously given in [43].In this study, the pulse period was fixed at 500 ms, and various pulse widths were selected for measurement: 100 μs, 1 ms, 10 ms, 100 ms, and 200 ms.The forward sweep, chosen as the baseline, was set at -4 V and -2 V for NiO HEMT and F-NiO HEMT, respectively.A low V DS of 1 V was used to rule out any possible trapping effect in the access region.The results of the pulsed I d -V gs curve with varied pulse widths for F-NiO-HEMT are shown in Figure 8, with the inset illustrating the pulsed conditions for the forward and backward sweep of gate voltage.During the pulsed measurement, it was widely assumed that trap states (acceptor-like) would capture electrons during the forward sweep.While in the backward sweep, the corresponding de-trapping process occurs and those trap states with emission times longer than the pulse width would remain occupied by the trapped electrons, leading to a positive shift of V TH , as shown in Fig. 8a.For the two different devices, we extracted the trapped charge density (Q it ) by utilizing the effective capacitance obtained from C-V measurement and the shift of V th from Fig. 8a.As seen in Fig. 8b, compared to the pure NiO-HEMT, the proposed F-NiO HEMT exhibited superior interface characteristics with lower-density trap states.It is found that the trap states within the range of 0.46 eV < E T < 0.657 eV exhibited relatively low concentrations.These traps, which are possibly located at the oxide/InAlN interface, belong to relatively shallow energy levels of trap states and have minimal impact on the performance of power-switching devices.A higher Q it of deep-level trap states (∼3.5 × 10 12 cm -2 , @ E T > 0.65 was also observed in NiO HEMT.These deep traps may provide pathways for electron transitions during testing, which explains why NiO-HEMT devices exhibit higher gate leakage compared to F-NiO HEMT. The of the pulsed I d − V gs and the corresponding transconductance g m curve for HEMT and NiO HEMT,  with a pulse width of 100 μs, are also presented in Fig. 9. Compared to the NiO HEMT, the FII HEMT exhibited a relatively large hysteresis (∼0.6 V), likely associated with the bulk traps in the barrier caused by the injection of F ions.However, in our study, we found almost negligible hysteresis at low gate voltages in NiO-based InAlN/GaN HEMTs fabricated under various conditions.These results suggest that, as compared to FII HEMTs, NiO-based HEMTs may be associated with substantially reduced trap densities due to the involvement of a high-temperature annealing process, or much faster trap/de-trap processes.As for the LM InAlN/GaN E-mode HEMT with the thinner barrier, the Fion implantation process requires more careful optimization.Further comprehensive investigations are necessary for a more accurate characterization of trap properties.Fig. 10 shows the current collapse characteristics of different devices based on the test of high V DS stress following a similar method given in [34], [45].The width and period of the pulse are set to 200 μs and 5 ms, respectively.The biases (VGQ/VDQ) are set at -8/0 V and -8/30 V in the measurement.It was found that the MS HEMT exhibited a larger overall collapse in pulsed I-V mode, while the current collapse is well suppressed in F-NiO HEMT, suggesting a high-quality NiO/InAlN interface related to the effective passivation induced by the high-temperature annealing process.To gain more insights into the mechanisms of trapping phenomena, the drain current collapse, typically defined as the ratio of the current deviation to the original saturation current CC = ((I Pulsed − I D0 )/I D0 ) × 100%, is also extracted at V ds = 20 V with results given in the inset of Fig. 10 under varying gate voltages.A gradual increase in current deviation was observed as the gate bias voltage decreased, potentially indicating a correlation with trapped charges at the barriers and the oxide/InAlN interface.This phenomenon is consistent with the findings reported in [46], where it was demonstrated that during off-state conditions, barrier and surface traps are filled by electrons injected from the gate terminal.Lowering the gate voltage increases the reverse bias across the device's gatedrain junction, thereby enhancing electron injection from the gate contact and consequently yielding an increased current deviation as voltage decreases.However, MS HEMT exhibited a different deviation trend with respect to gate voltage as compared to F-NiO HEMT.In addition to interface traps, this variation might also be associated with buffer traps induced by uncertain substrate doping as indicated in [47].The decrease in gate voltage diminishes the injection of electrons into the buffer layer, resulting in a reduction in the density of filled traps within the buffer and consequently a decrease in the current deviation.
We evaluated the threshold voltage thermal stability of the fabricated devices through temperature-dependent I-V measurements.The devices were placed on a thermostatic heating plate and subjected to temperature testing from 300K to 450K in increments of 25K, During this test, transfer characteristic I-V measurements were conducted with a gatesource voltage (V GS ) scanning range from -4V to 4V.As the temperature increased, the drain current (I D ) in different devices showed a varying degree of decrease as expected.Figure 11 illustrates the variation of the extracted shift of V TH of different devices with increasing temperature.An opposite temperature coefficient of the shift of V TH between pure F implantation and NiO-based devices is observed.For F-NiO HMET, a shift of less than -0.32 V in V TH is obtained at T = 450 K, demonstrating superior hightemperature characteristics as compared with FII HEMT & NiO HEMT.We ascribe the distinct behavior of shift of V TH at elevated temperatures to the variations of transport mechanisms shown in Figure 12.As for FII HEMTs, when transitioning to the ON-STATE at a relatively low gate voltage, electrons start to overflow the InAlN barrier, and some are captured by pre-existing traps which might be associated with the trap state widely reported in [48], [49], [50], [51].With increasing temperature, the trapped electrons with sufficient energy were released (process i), and the diffusion of negatively charged F ions intensified (process ii), reducing the depletion effect at the interface.These processes contribute to the negative shift in the threshold voltage.
Conversely, as for NiO-based HEMTs, extra hole accumulation occurs at the interface of oxide/InAlN (process iii), the p-type nickel oxide structure gains energy at elevated temperatures, leading to the transformation of Ni 2+ into Ni 3+ and thus an increase of the concentration of Ni vacancies.This process, therefore, results in a positive shift in the threshold voltage.Furthermore, the substantial accumulation of holes slightly raises the potential, further restricting the injection of electrons from the channel to the gate as the result present in Fig. 6.The above three transport processes coexist in F-NiO HEMTs, and the inverse temperature coefficient relationship contributes to the superior hightemperature characteristics of the devices.

IV. CONCLUSION
In this study, we experimentally investigate the properties of E-mode LM InAlN/AlN/GaN MOS-HEMTs using fluorine treatment and p-type NiO gate.The nickel film deposited at the substrate temperature of approximately 25 As for F-NiO HEMTs, a gradual increase in current deviation was observed as the gate bias voltage decreased, whereas the opposite holds for conventional MS InAlN/GaN HEMT.This result reveals that the trap state primarily affecting the dynamic performance of E-mode F-NiO HEMTs originates mainly from the interface of Oxide/InAlN, rather than the substrate buffer as observed in MS HEMT.The observed opposite shifts in V TH under elevated temperatures were attributed to distinct transport mechanisms, including electron overflow and trap release in FII HEMTs, while the hole accumulation and Ni vacancy concentration changes in NiObased HEMTs.The E-mode F-NiO HEMTs demonstrate minimal threshold voltage drift (less than 0.32V) at high ambient temperatures (up to 450 K), resulting in better temperature stability and showing their potential value in the development of monolithically integrated GaN-based circuits.

FIGURE 1 .
FIGURE 1. Cross-section schematic of a) FII HEMTs.b) F-NiO HEMT.c) Optical microscope image of F-NiO HEMT.d) thickness of deposited NiO x by AFM.

FIGURE 2 .
FIGURE 2. Typical X-ray diffraction patterns of NiO films, inset present more detailed results under different NiO deposition conditions.

FIGURE 3 .
FIGURE 3. (a) The band diagrams of typical InAlN/GaN MOS HEMT with and without Fluorine treatment, (b) DC I-V transfer characteristic of FII HEMT under various plasma-treatment conditions.

FIGURE 4 .
FIGURE 4. Transfer and transconductance characteristics of F-NiO HEMT with different ratios of oxygen and substrate temperature.

FIGURE 5 .TABLE 1 .
FIGURE 5. Measured I-V output characteristics of the different devices.

FIGURE 6 .
FIGURE 6. Transfer characteristics of different devices at Vds=10 V in (a) linear and (b) semi-log scale.

FIGURE 7 .
FIGURE 7. (a) Measured C-V characteristic of the different devices, (b) Optical microscope image of circular Schottky diode.

FIGURE 8 .
FIGURE 8. (a) Pulsed I d -V gs measurement of F-NiO HEMT with the pulse width of 100 µs, 1 ms, 10 ms, 100 ms, 200 ms, inset: schematic of pulsed V gs condition with forward and backward sweep.(b) extracted trap charge density (Q it ) of NiO HEMT and F-NiO HEMT.

FIGURE 9 .
FIGURE 9. Pulsed I d -V gs and transconductance g m measurement of (a) NiO HEMT, (b) FII HEMT with a pulse width of 100 µs.

FIGURE 10 .
FIGURE 10.Comparison of the measured DC and pulsed output characteristic of F-NiO HEMTs and MS HEMT.Inset: Deviation evaluation for the different devices under varying gate voltage.

FIGURE 11 .
FIGURE 11.Shift of V TH of different devices under elevated temperature.

FIGURE 12 .
FIGURE 12. Schematic band diagram of the F-NiO HEMT at increasing temperature.
• C, with an oxygen partial pressure of 33%, exhibits the lowest resistivity and satisfactory crystalline quality, making it suitable for use as a gate electrode in NiO-based InAlN/GaN HEMT.It is observed that by comprehensively regulating fluorine ion implantation and sputtering conditions of NiO, V TH of Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.thedevices can be effectively modulated without gate recess etching.The comparison of E-mode and D-mode devices is comprehensively done.The proposed F-NiO HEMTs demonstrate a significant improvement in on-state characteristics, including more positive V TH (+1.05 V), enhanced gate voltage swing, and larger transconductance.The thinner barrier and high-quality NiO/InAlN interface provide superior gate control over the channel with I on /I off ∼10 8 , SS ∼ 95 mV/decade.The C-V and pulsed mode measurements confirm the excellent NiO/InAlN interface and effective suppression of current collapse.