Lateral Electrochemical Metallization Cells for Reconfigurable Interconnect Systems

Lateral electrochemical metallization (ECM) cells are fabricated with a combined spacer/damascene process. The process allows the realization of nanoscale geometrical distances between the two electrodes independent of lithography. Such lateral ECM cells are an essential part in a reconfigurable interconnect system that may yield a strongly increased connectivity in artificial neural networks. The lateral cells show memristive properties comparable to vertical cells with switching voltages in the range of −1.5V to 2.5V. The influence of electrode line edge roughness on SET kinetics of such lateral cells is investigated via kinetic Monte Carlo simulations, finding a minor influence on SET time variability.


I. INTRODUCTION
The human brain is the most complex and most sophisticated information processing system known. Due to a massively parallel operation, it is able to process huge amounts of data with very little energy consumption. This extremely parallel information processing is made possible by a very high degree of interconnects between neurons that can be set and reset autonomously during learning processes. Demonstrating a similarly complex yet flexible interconnectivity is a major challenge of artificial neural networks.
Flexible setting/re-setting of interconnects can be realized using, e.g., field-programmable gate arrays (FPGAs) [1], [2], [3]. Recently, neuromorphic circuits based on FPGAs were demonstrated and employed for a number of applications including recognition of handwriting [12], classification of musical notes [2], and biomimetic pattern generation [3] (for further applications see [13]). However, the gate configuration of FPGAs is not remanent and additional storage is necessary. While high-capacity flash memory can be manufactured by 3D integration [14], the combination of a flash memory and an FPGA increases space and power requirements.
As an alternative, reconfigurable circuits based on a combination of CMOS and memristive crossbar structures have been investigated in view of realizing field-programmable interconnects [7], [8], [9]. In particular, electrochemical metallization (ECM) materials [4], [5], [6] have attracted a great deal of attention for such reconfigurable structures: the functionality of a synapse can be mimicked since a conductive filament (CF) of adjustable strength can be grown in between two metallic electrodes (consisting, e.g., of platinum and copper) with an appropriate electric field; reversing the field, the interconnect can be erased [15], [18]. Transistor-free crossbar memristors based on metal-oxides were applied to the computation of an analogue of vector-matrix multiplication [16]. Moreover, crossbar structures consisting of several crossbar layers have been fabricated [7], [8], [9], [10], [11].
In such multilayer memristive crossbar devices sneak current paths can form. These are indirect current paths through non-selected cells during READ/WRITE operations, increasing the power consumption and causing voltage drop along the line [25]. One solution to this problem are selector devices placed at the memristor-crossbar junction [26], [27]. By design, these selectors suppress conductivity for all indirect connections between two crossbar lines. This simultaneously limits any memristive cell-to-cell interconnectivity since the suppressed sneak paths are the only available mechanism for behavior of this type.
By comparison, in a network of biological neurons, many neuron-to-neuron connections of different strength are possible. To emulate this interconnectivity in memristive cell arrays, we suggest to shrink the line-shaped electrodes to a geometry resembling mushrooms, consisting alternately of, e.g., platinum and copper, placed on a quadratic lattice. The top parts of the mushroom-electrodes are embedded into an ECM material and the stems are connected to a buried CMOS layer that allows applying the three voltage levels −V dd , 0 and +V dd to each mushroom-electrode independently.
This layout enables formation of CFs between any two adjacent electrodes in the 2D array, providing interconnectivity at the cell level. The CMOS layer offers additional flexibility compared to addressing by conventional crossbar schemes, as applying potential to Cu electrodes along a crossbar line will always select two electrodes adjacent to any selected Pt electrode simultaneously. On top of the proposed 2D system, additional layers may be fabricated, allowing connections to be SET and RESET both laterally and vertically as illustrated in Fig. 1 (b). The mushroom-shaped electrodes also facilitate alignment between layers, as the thin stem can be positioned anywhere on the larger cap of the opposing electrode in the previous layer.
A central ingredient of such a 3D interconnect system is the realization of low-resistivity CF growth in-between two lateral electrodes. Whereas lateral filamentary growth has recently been investigated [19], [20], [21], the separation between the electrodes is on the order of a few hundred nanometers and hence far larger than in typical vertical ECM cells. The reason for this is that in the fabrication of those lateral ECM cells, two lithography processes are necessary leading to variability issues and requiring sufficient overlay alignment tolerances. In contrast, in vertical cells, the separation between the two electrodes is defined by the unprecedented film thickness control of state-ofthe-art deposition processes (e.g., sputter or atomic layer deposition). As a result, in existing lateral ECM cells large voltages (e.g., 30 V in [21]) are required for the growth of a CF, prohibiting nanoscale dimensions and high integration densities, and resistivity after SET is higher due to the length of the grown CF.
We have therefore developed a combined damascenespacer process where the lateral electrode interdistance is determined by the ECM deposition process enabling true nanoscale lateral ECM cells. Here, we demonstrate the functionality of lateral ECM cells with a sub-25 nm switching layer (SL). Furthermore, we investigate the influence of electrode line edge roughness on the SET kinetics of such lateral devices with a simulation based on a kinetic Monte Carlo approach.

II. DEVICE FABRICATION
Lateral ECM cells are fabricated as illustrated in Fig. 2. A first electrode is patterned onto a silicon substrate using electron-beam lithography (EBL), electron-beam evaporation (EBV) and lift-off ( Fig. 2 (a)). To avoid resist blistering/shrinking during EBV and achieve appropriate deposition results, we employed the EBV technique presented in [22]. Next, SiO 2 doped with 142 ppm of Al and 5 ppm of Cu is sputter-deposited on top of the substrate (b) serving as the SL [23], [24]. Low pressure magnetron sputtering is employed to ensure a deposition with proper conformality; the top right panel of Fig. 2 shows a cross-sectional electron micrograph as an example. Subsequently, a second electrode is fabricated using EBL, EBV and lift-off (c). Finally, chemical-mechanical-polishing is used to remove the second electrode material from the top of the first electrode and a lateral ECM cells is formed (d). In the sketch a cell is formed on either side of the Pt electrode because of the crossed-line pattern.
Importantly, although two lithography processes have been employed during the fabrication, the distance between the two electrodes is determined exclusively by the deposition of the SiO 2 SL. Hence, the use of EBL was only for convenience and the process itself does not require the overlay accuracy and resolution enabled by EBL. Due to the excellent control over the thickness of the deposited films, lateral ECM cells with only a few nanometers distance between the two electrodes become feasible. After polishing, another ECM layer and electrode could be deposited on top of the lateral ECM cell yielding connected vertical and lateral ECM cells for which the inter-electrode distance is not controlled by lithography.
For a lateral device the edge and not the top surface of the metal will be the cell interface. Accordingly, the line edge roughness (LER) at that interface is a combination of the roughness of the deposited film and the typically much larger LER from the lithography process (see Fig. 2 (e)). Provided that the SL deposition is conformal and sufficiently thin, the LER of the first electrode will transfer to both the SL and second electrode which reduces the overall thickness variability compared to an interface defined by two independent LER profiles. For a thicker SL film (in the order of the dominant wavelength of the horizontal LER of the first electrode) the conformal deposition will cause valleys in the roughness profile to fill, smoothing the edge profile but causing variations in effective distance between the electrodes along the interface. In Section IV we investigate one mechanism by which LER may affect switching behavior, which is the position of the initial filament site (valley, hill or flank of the roughness profile), by modeling the subsequent CF growth from these seeds with a kinetic Monte Carlo approach.
Using the fabrication process detailed above, ECM cells with 2 μm wide contacts consisting of Pt (on a Ti adhesion layer, counter electrode (CE)) and Cu (active electrode (AE)) are created in two variations. For the first variant, the CE is Pt-capped Ti (20 nm Pt on 80 nm Ti), the oxide thickness is 40 nm and the AE is 90 nm Cu. In the second variant, the respective thicknesses are 80 nm Pt on 5 nm Ti, 25 nm SiO 2 and 90 nm Cu. The given oxide thickness is a nominal value as non-ideal conformity of the deposition process yields reduced thickness on the sides of the electrode (see Fig. 2 top right). The center SEM micrograph in Fig. 2 shows a top-down SEM image of a complete device with contact pads (left and right), Cu dummy lines to improve polishing (top and bottom) and the laterally oriented metal-insulator-metal interfaces (magnified in the bottom micrograph).

Measurements of the lateral ECM cells are carried out with
Keithley 2636A (first variant) and Keithley 4200A-SCS (second variant) source meters connected to a probe station. A voltage bias is applied to the Cu AE, while the Ti/Pt CE is connected to ground.
For the first variant (40 nm SiO 2 ) a current compliance of 10 μA is used for the initial CF formation, which occurs at approximately 5.7 V. The high resistance state is recovered at −2.5 V (Fig. 3 (a)). Subsequently, the device shows resistive switching behavior at three different current compliance levels (1 mA, 500 μA, 300 μA), as shown in Fig. 3 (b). The transition from the high resistance state (HRS) to the low resistance state (LRS) occurs at approximately 2.5V (HRS to LRS) and −1.5V (LRS to HRS). In addition to a relatively large variation for cycles using the same current compliance, a trend towards lower switching voltages for lower current compliances can be observed. By comparison, in a vertical

V. (b) Switching behavior of 40 nm SiO 2 variant at multiple current compliance (I cc ) settings (indicated by color). An overall trend towards lower switching voltages for decreasing current compliance can be observed, though variance at all compliance levels is relatively large. (c) Initial forming of a CF and first RESET in a device with 2nm SiO 2 thickness. The CF forms at a much lower voltage of 1.3 V (current compliance is 1 mA). The RESET occurs at approximately −1 V. (d) LRS and HRS resistivity in a device with 2nm SiO 2 after switching by 1 ms pulses (3 V SET and −2 V RESET). The LRS are at approximately 100 , the HRS range from 4 k to 3 M . On the right, current/voltage-time plots (absolute values) corresponding to a SET and RESET operation are shown. The switching process during the SET is faster than the time resolution of the measurement setup (1 μs).
device (50 μm by 50 μm electrodes, data not shown here) using the same materials and SL thickness, slightly lower switching voltages (approximately 0.5 V) are observed with cycle-to-cycle variation scaling by a similar factor.
For the second variant of lateral device (25 nm SiO 2 layer), a Keithley 4200A-SCS equipped with a pulse measure unit is used. As expected with a thinner SL, the formation of the CF occurs at a significantly lower voltage of 1.3 V. A current compliance of 10 mA is used. Switching back to the HRS is observed below −1 V, as can be seen in Fig. 3 (c). The device is subsequently switched using 1 ms square pulses (20 μs rise and fall time) with 3 V SET and −2 V RESET amplitude (Fig. 3 (d) right). Equivalent pulses with an amplitude of only 0.5 V are used for READ operations and show LRS near 100 , achieving the goal of lowohmic SET-states, and HRS in the range of 4 k to 3 M (Fig. 3 (d) left).

IV. SIMULATED EFFECTS OF LINE EDGE ROUGHNESS ON SET KINETICS
A previously reported kinetic Monte Carlo (KMC) model [28] was used to investigate the influence of the measured LER on the SET kinetics of ECM cells. The approach is to use an established set of simulation parameters to investigate the influence of electrode/electrolyte interface LER on SET kinetics in comparison to planar electrode/electrolyte interfaces. This allows the difference between lateral cells with LER and vertical cells with planar electrodes to be estimated. The considered processes contain motion of ions, reduction and oxidation. The rate equation for ionic motion is defined as with the vibrational frequency ω hop , the migration barrier W hop , the ion charge number z, the elementary charge e, the Boltzmann constant k B , the local temperature T and the potential difference between two adjacent cells ϕ. The reduction rate can be written as and the oxidation rate as with the reaction rate constants k red and k ox , the charge transfer coefficient α, the overpotential η, and the activation energy for reduction/oxidation W red / W ox . Note that these energies are slightly different depending on the site of reduction/oxidation (c.f Table 1), as explained in [28]. The electric potential is calculated by coupling of two Laplace equations. One accounts for the metallic domains and describes electronic currents, the other one accounts for the SL and describes ionic currents. The Laplace equations are defined as and with the electric potential ϕ 1 within the metallic areas (AE, CE, CF), the electric potential ϕ 2 within the SL, the electronic conductivity σ me of the AE/CE/CF material and the ionic conductivity σ ion of the SL. The ionic conductivity is further defined via the local ion concentration c ion , defined as the average number of ions in a surrounding square with edge length 5a, where a is the lattice constant of the SL material. With the mobility μ ion of an active ion, the ionic conductivity can be written as The coupling of equation (1) and equation (2) is achieved by Neumann boundary conditions, which include the electron exchange mechanism calculated by Butler-Volmer currents (Fig. 4). This implementation leads to continuous current through the cell, but creates a voltage jump at the AE/SL, CE/SL and CF/SL interfaces, called overpotential η. The Butler-Volmer equation is denoted as  with the exchange current density J 0 defined as with the heterogeneous rate constant k et and the activation energy W et . When the gap between CF and AE gets small compared to the SL height, a significant tunnel current sets in. This tunnel current is defined as current density between CF and AE. The tunnel current density between similar electrodes is defined using the linear Simmons equation [30].
with the effective electron mass m eff , the distance x between CF and AE, the tunnel barrier height W 0 , the Plank's constant h and the tunnel voltage V Tu defined as the voltage difference V Tu = ϕ 1,AE − ϕ 2,CF between AE and CF. The parameters used in the simulations are shown in Table 1. As stimulus a rectangular voltage signal with variable amplitude V app is applied to the AE. When the current reaches the maximum current I CC , the simulation is aborted and the time to reach I CC is stored as SET time t SET . A realistic LER profile is needed as a starting point for the described simulation. Such a profile was extracted from an SEM micrograph of the interfaces of a fully fabricated lateral ECM device, with the LER wavelengths being quantified by calculation of the correlation function for points on either edge (see Fig. 2 (e)) and the amplitude estimated directly from the line fit of the edges. The dominant spacial wavelength was roughly 100 nm (first dip in the correlation function) while the 3σ edge variation was approximately 19 nm (over a 90 nm length). To investigate the possible effects of LER on switching kinetics, the simulation was then done for a slightly more pronounced LER profile: the AE/CF and CF/CE domains were evenly, sinusoidally warped with an amplitude of 10 nm and a wavelength of 40 nm over a width of one full wavelength.
The seed, also called critical nucleus, was then placed at 3 relevant positions, which are valley (Fig. 5 (a)), flank ( Fig. 5 (b)) and hill (Fig. 5 (c)). The simulated applied voltages V app are 1 V, 1.5 V, 2 V and 2.6 V. Due to the statistical nature of a KMC model, each simulation was performed ten times for every seed position and at every voltage and the mean values are plotted in Fig. 5 (d). The light outlines of the curves show the standard deviation of the mean. The results for flank and hill overlap, while the results for valley clearly show slower switching. For comparison, the kinetics of a planar geometry corresponding to a regular vertical cell were also simulated. Of the three LER cases examined (valley, hill, flank), the planar geometry corresponds most closely to the flank case; accordingly, both SET times almost coincide. Compared to the scattering of real measurements [29] the influence of the LER on the SET kinetics is negligible.
This leads to the conclusion that the reported self-aligned, conformal fabrication can be used for the development of 2D and 3D ECM structures without additional concerns due to LER effects.

V. CONCLUSION
We have presented a novel process for the fabrication of lateral ECM cells. With this process, the achievable distance between electrodes can be reduced to the few tens of nanometer scale without need for a lithography process with extreme overlay accuracy. Using this process, ECM cells with less than 25 nm lateral separation between electrodes were created and shown to exhibit resistive switching behavior, as well as functionality in pulsed operation. Through the use of a kinetic Monte Carlo simulation we also found that line edge roughness effects on SET kinetics are small and unlikely to be a problem with lateral ECM devices.