THM-OTFT: A Complete Physics-Based Verilog-A Compact Model for Short-Channel Organic Thin-Film Transistors

This paper presents a compact model for organic thin-film transistors fabricated in the staggered or coplanar device architecture which includes short-channel effects related to the potential barrier in the channel region, which manifest themselves as threshold voltage roll-off, drain-induced barrier lowering, and subthreshold swing degradation. Furthermore, the effect of non-linear injection due to a work-function mismatch between the source/drain contacts and the semiconductor is considered. The model includes a charge-based capacitance model considering overlap and fringing regions in short-channel multi-finger layout structures. Extensions include a model for drain-current variability, low-frequency noise and non-quasistatic effects. The introduction of physically meaningful fitting parameters provides a high degree of flexibility to the model. The equation package is verified using the results of measurements performed on transistors fabricated on flexible substrates and is available in Verilog-A for an efficient circuit simulation on different design platforms.


I. INTRODUCTION
Organic thin-film transistors (OTFT) have evolved as candidates for large-area flexible electronics, as they can typically be fabricated at low temperatures compatible with polymeric substrates.Envisaged applications range from wearable electronics to display backplanes [1], [2].Recent advances in device technology have pushed the maximum operational frequency well into the megahertz regime [3].
The design of complex integrated systems based on organic transistors relies on accurate and efficient compact models for these devices, serving as a bridge between device technology and the circuit level and allowing for efficient circuit simulation.Based on the physics of organic semiconductors (OSC) [4], [5], numerous approaches to compact models for organic TFTs have been proposed [6], [7].However, some of them are lacking physical insight or do not provide the flexibility required for the model to be readily adapted to different technologies.Moreover, most compact models are not suitable for both DC and AC circuit simulations.In other words, a standard compact model dedicated to the physics and the static and dynamic behavior of OTFTs is still lacking, despite the fact that such a model is a prerequisite for establishing an effective collaboration between fabless design houses and foundries.
In this paper, we present a complete physics-based compact model for OTFTs fabricated in the staggered or the coplanar device architecture (refer to Fig. 1).The DC model is able to capture the effects of small channel lengths on the potential barrier and of non-linear contact characteristics [8].The AC model uses the same charge expressions as the DC model, considers fringing capacitances in multi-finger structures and includes non-quasistatic effects.Furthermore, a model for low-frequency noise (LFN) has been implemented.Although some parts of the model have already been published, this paper for the first time presents an overview of the complete compact model (including the parameters relevant for the interface to a Verilog-A implementation), explains the interdependencies between the different modules, and provides guidelines for parameter extraction.
The paper is organized as follows.Section II reviews the core DC model and its basic expressions for the accumulated channel charge which are fundamental for the whole model.All model extensions related to short-channel effects, non-linear contact resistance, fringing effects, and the DC variability due to a fluctuation of the channel current are summarized.Hereby, the summary of the model parameters provided in Table 1 serves as a reference for the interface to the model.After comparing the DC model to measurement results, Section III summarizes the capacitance model, including fringing effects, non-quasistatic effects and LFN.Again, verification results are also shown.Finally, guidelines for a parameter extraction for the Verilog-A implementation of the model are given in Section IV, and Section V gives conclusions.

II. DC MODEL
The core DC model is an expression for the current in longchannel devices.Because its equations are fundamental to the entire compact model, they will be briefly reviewed in the next section.After that, model parameters such as threshold voltage and subthreshold swing are replaced by expressions accounting for short-channel effects.Non-linear effects at the source and drain junctions are considered by an additional contact resistance that degrades the effective carrier mobility in the model.Finally, current fringing effects in a multifinger layout are taken into account, and an extension for evaluating the drain-current variability is introduced.

A. LONG-CHANNEL CURRENT MODEL
The DC model for the intrinsic transistor has been derived from a single expression for the accumulated channel charge which is valid from below to above-threshold operation [9].The result is a continuous expression for all regions of operation, without further artificial smoothing.The Gaussian density of states (DOS) in organic semiconductors is included by an empirical power-law mobility expression.
The DC model in [7], [9] is a charge-based model, which means that the current is calculated based on the charge densities Q ms and Q md on the source and the drain ends of the channel (see Fig. 1).These charge densities are calculated as follows: where L is the first branch of the Lambert W function, C ox is the capacitance of the gate dielectric per gate area, S is the subthreshold swing, and V T0 is the threshold voltage.
The model takes into account the hopping transport together with the effect of the Gaussian DOS by a field-dependent mobility [10]: where κ [cm 2 V β−1 s −1 ] is a proportionality factor and β is the power-law factor.An ohmic contact resistance (R contact ) and a possible non-linear resistance (R sb ) at the source-tochannel Schottky barrier due to a work-function mismatch are taken into account by introducing an effective mobility: Finally, the drain current reads as follows: where L ch and W ch,eff are the channel length and the effective width.The parameter λ is the channel-length modulation factor.The effective drain-source voltage V dsx tends to the saturation voltage V dsat in the saturation regime and is given by

B. SHORT-CHANNEL EFFECTS
If the channel length is small (a few micrometers or less), the OTFT's current-voltage characteristics are likely dominated by short-channel effects, similar to those known from silicon transistors.The impact of the source/drain potentials on the potential barrier in the channel region will typically result in a threshold voltage shift (VT roll-off), drain-induced barrier lowering effects (DIBL), and a degradation of the subthreshold swing.In order to incorporate these effects in the model, a two-dimensional solution of the potential in the channel region has been developed, from which closed-form expressions for the aforementioned effects have been derived.The model provides solutions for the staggered and the coplanar device architectures [11], [12], [13].It has been shown that for each of the short-channel effects, the potential solution must be calculated for various distances from the gate dielectric (d poi ).Therefore, three model parameters controlling these short-channel effects separately were introduced.Their impact on an OTFT transfer characteristics is shown in Fig. 2. Please note that in this way, the model is scalable, i.e., there is only one model card for devices with various channel lengths.

C. CONTACT RESISTANCE
Due to the lowering of the channel resistance in shortchannel devices, the current limitation imposed by the source and drain contacts becomes more dominant.If the mismatch between the work function of the contact material and the organic semiconductor is relatively large and cannot be neglected, in addition to the ohmic contact resistance the effect of non-linear current injection can be visible in the transistor's output characteristics.
In our model, the current injection at the source contact through the reverse-biased Schottky barrier is calculated from the effective electric field at the point of injection [13], [14].In view of numerical efficiency, the current-limiting behavior is converted into an equivalent bias-dependent resistance R sb , which is incorporated into the intrinsic transistor model by using equation ( 3) for the effective mobility.The forwardbiased drain barrier is taken into account by an additional voltage drop V sb,d .This is done by one iteration: first, equations (1) to (4) are computed without the voltage drop.From this result, V sb,d is calculated.Finally, the charge density at the drain side is calculated again, but this time taking into account the voltage drop V sb,d , and from (4), the DC current is obtained.
Fig. 3 illustrates the flexibility of the model to capture the s-shape of the output characteristics by using different physically meaningful fitting parameters.

D. FRINGING EFFECTS
The fringing regions open additional paths for the current; this can be viewed as a current spreading.However, the current density in the fringing regions will be smaller than in the channel, especially in regions far away from the channel center, due to the weaker electric field.The current spreading is schematically shown in Fig. 1d.The behavior is modeled as a change in the effective channel width W ch,eff for the current [15], [16].
To account for the fringing effects, the drain current given by ( 4) is modified.It is assumed that the effective channel width is larger than the width of the contacts (N fing •W contact ), but smaller than the width of the gated semiconductor W ch,G (refer to Fig. 1d).Note that the width W ch,G includes both the fringing regions outside the outermost contact fingers (w ovl ) and the fringing regions between the contact fingers.The effective gate width is defined as follows: where N fing is the number of fingers, and d fing is the distance between the fingers.The fitting parameter δ fit ∈ [0, 1] is assumed to be bias-independent [15].

E. DRAIN-CURRENT VARIABILITY
Drain-current variability can be perceived as the timeindependent variation of the drain current of two or more nominally identical transistors under the same biasing conditions.Here, the device-level charge-based variability model from [17] is used.The proposed physical model has two fitting parameters, can be applied directly to the experimental statistical population without the need for Monte Carlo simulations and accurately describes the bias-dependent variability of organic TFTs, fabricated either in the staggered or the coplanar device architecture.
The model parameter N t,var denotes the density of charges being trapped in the channel region per gate area, which cause a local fluctuation of the accumulated charge density in the channel.The parameter α * is related to Coulomb scattering induced by the trapped charges that manifests itself as a reduction of the effective carrier mobility in the channel.However, it should be noted that because of the factor μ eff W ch, eff /L ch in (4), in the current-voltage characteristics, this charge-carrier-correlated mobility fluctuation cannot be distinguished from edge effects [18].
If the drain-current variability model is switched on (model parameter var mod=1), the calculated drain current is equal to its mean value plus or minus a multiple of its standard deviation σ , depending on the model parameters sigma sign and sigma factor.

F. RESULTS
Results obtained using the DC model in comparison to results of measurements performed on coplanar OTFTs with a channel length of 1 µm are shown in Fig. 4. The devices were fabricated on flexible PEN substrates using stencil lithography [19].The gate electrodes are vacuumdeposited aluminum, the gate dielectric consists of plasmagrown aluminum oxide and a self-assembled monolayer (n-tetradecylphosphonic acid) with a total thickness of 9 nm, the source and drain contacts are vacuum-deposited gold with a thickness of 30 nm, and the OSC is vacuum-deposited DPh-DNTT with a nominal thickness of 20 nm.Results obtained using the variability model are shown in Fig. 4d.For further verification of the DC model, including for OTFTs fabricated in the staggered device architecture, please refer to [11], [12], [14].

III. AC MODEL
From the DC model described in Section II, a quasistatic AC model has been derived.The model accounts for the intrinsic channel charges, parasitic charges in the overlap regions and for charges in the fringing regions (in OTFTs with a multi-finger structure) [15], [16].

A. INTRINSIC CAPACITANCES
The intrinsic charges are calculated by integrating the charge density per gate area of the DC model along the channel, which leads to a closed-form equation for the total channel charge.Applying the well-known Ward-Dutton partitioning scheme [20], the channel charges are separated into parts attributed to the source or the drain terminal.
As a result, these charge equations are valid only for transistors that exhibit zero or negligibly small (with respect to the channel resistance) contact resistances.However, contact effects also have an influence on the capacitances, especially  if the contact resistances are high in comparison to the intrinsic channel resistance.In the DC model, the contact resistances R contact and R sb are calculated.For simplicity and numerical performance of the DC model, these resistances are not introduced as lumped elements.Instead, as explained in Section II-C, they lower the effective mobility of the charge carriers in the channel.So while these elements provide an accurate prediction of the current-voltage characteristics of the OTFTs, they cannot necessarily be used to obtain an accurate estimation of the voltage drops at the contacts.To be able to incorporate the voltage drops at the Schottky barriers into a short-channel capacitance model, the parameters K fit and K r have been introduced [16], [21].They make it possible to adapt the characteristics of the internodal capacitances by modifying the weight of the contact resistances and their distribution between the source contact and the drain contact.Furthermore, the parameter ν allows a fine tuning of the Ward-Dutton charge partitioning.
Figure 5 demonstrates how the voltage dependence of the capacitances C gs and C gd of staggered short-channel OTFTs is affected by the model parameters K fit and K r .Numerical results obtained using TCAD Sentaurus [22] are shown as a reference.

B. EXTRINSIC CAPACITANCES
The density of intrinsic charges is calculated in the same manner for staggered and coplanar transistors.However, as illustrated in Fig. 1a and b, due to the overlap regions, there are fundamental differences between the densities of extrinsic charges in the two OTFT architectures.In coplanar transistors, the source/drain contacts are separated from the gate electrode only by the gate dielectric; an arrangement that can be approximated by simple plate capacitors.In contrast, in staggered transistors, the source/drain contacts are separated from the gate electrode by a stack consisting of the organic semiconductor and the gate dielectric.For this series connection of two capacitors, additionally the same density of accumulated charges given by the DC model for the source end (Q ms ) and the drain end (Q md ) of the channel is being considered.This results in a bias-dependent charge model, as presented in [15], [16].
Additionally, in a multi-finger layout, as depicted in Fig. 1c, all charges in the fringing regions have to be considered.In our model, we assume that for both staggered and coplanar devices, the charge density per gate area in the source region (hatched region in Fig. 1c, which excludes the areas of direct overlap between gate electrode and the source/drain contacts) is equal to the density of accumulated charges Q ms and Q md at the source/drain ends of the channel.This has been confirmed by numerical TCAD Sentaurus simulations, and these additional charges are a substantial contribution to the total extrinsic capacitances [16], [21].In this way, in our model we are taking into account the layout of the OTFT.Therefore, our capacitance model goes beyond a simple two-dimensional modeling approach derived from the device cross section alone.The increase of the active area according to the layout of the multi-finger structure is necessary for obtaining a good agreement between the small-signal gain calculated using the compact model and the result derived from measurements [21].

C. NON-QUASISTATIC EFFECTS
The quasistatic small-signal model of the transistor considers capacitances as lumped elements between the device contacts.However, the accumulated charge is distributed along the channel, and therefore with increasing frequency, the channel starts to behave as an RC delay line, with a capacitance distributed along the channel resistance.Furthermore, charge trapping in the gate dielectric or the semiconductor has an additional impact on the formation of the intrinsic charges.These effects cannot accurately be captured by a quasistatic charge calculation as proposed in the previous section.In the literature, sophisticated nonquasistatic approaches have been proposed [23].However, in our model we follow an empirical approach from [24].Here, the quasistatic capacitances are multiplied by a scaling function, modifying the lumped elements depending on the empirical model parameters τ scale and p scale : Since the frequency f is not available within the Verilog-A environment during runtime of an AC analysis, this scaling factor has to be calculated prior to the simulation for the frequency of interest, and its value has to be provided as an input parameter to the compact model.The Verilog-A implementation of our model makes it possible to apply this approach separately for the scaling of the quasistatic extrinsic and intrinsic capacitances, which during runtime are multiplied by the model parameters C scale and C scale2 , respectively [16], [21].

D. LOW-FREQUENCY NOISE
The model takes into account two discrete sources for LFN in organic TFTs.One is the noise due to the carrier-number and correlated mobility-fluctuation effect ( N noise), which originates from local random fluctuations of the carrier density due to trapped charges, additionally causing correlated Coulomb scattering [25].The other is the noise due to the fluctuation of the charge-carrier mobility ( μ noise) [26].
The model equations have been derived following the methodology in [27], in our case starting from the charge density given by equation ( 1) of the DC model, leading to expressions combining the N and μ noise [28].The influence of the model parameters σ , N t , λ tun and α c on the noise power spectral density (PSD) is illustrated in Fig. 6a-c.

E. RESULTS
In Fig. 6d, results of the LFN model are shown in comparison to noise measurements performed on staggered OTFTs.Fig. 7a and b show model results for the internodal intrinsic capacitances in a short-channel OTFT compared to results of TCAD Sentaurus simulations, allowing for a verification with defined structural and material parameters [15].The fitting of the model provides an overall good agreement between model and simulations.However, a compromise has to be made regarding the voltage dependence of C gs and C sg at the transition from the linear to the saturation region, which is due to the consideration of the voltage drops at the contacts by an effective mobility in the DC model (for sake of numerical efficiency), which can only to a certain degree be compensated for by the model parameters K fit , K r and ν in the capacitance model.Fig. 7 shows a verification of the model by comparison to measurements performed on staggered and coplanar OTFTs having a channel length of 0.67 µm and a variation of the gate-to-source and gate-todrain overlaps.The model is able to capture the degradation of the small-signal gain up to frequencies of several megahertz and correctly predicts the higher transit frequencies of coplanar devices [21].

IV. PARAMETER EXTRACTION
In the derivation of the equation package for the compact model, a physics-based approach that considers two-dimensional effects has been followed.As a result, the compact model demonstrates a good scalability and makes it possible to define one parameter set covering devices with a range of layout dimensions.Nevertheless, to obtain a perfect fit for OTFTs with a wide range of channel lengths, several fitting parameters must be adjusted.This is not only due to approximations introduced in the modeling approach, but also due to the fact that the fabrication process of OTFTs introduces an additional variability to the model parameters which are taken as global parameters for the semiconductor.The morphology of the OSC layer is expected to be different in the close vicinity of the source and drain contacts, which has an impact on the local mobility, trap density, contact resistance and non-linear injection.These effects are particularly pronounced in short-channel devices, making an adaption or binning of related model parameters necessary.
A Verilog-A implementation of the equation package is provided by [29].It should be noted that the code includes an option for the separation of the device channel into a number of discrete segments [27], allowing for a more precise simulation of non-quasistatic effects.For details, please refer to [29].Furthermore, the temperature dependence of the DC model in the range of temperatures from 300 to 340 K has been investigated in [16], and empirical expressions for a shift of the threshold voltage and a drift of the effective mobility have been proposed.
In the following, the main steps for arriving at a set of model parameters (refer to Table 1) for the Verilog-A implementation without channel segmentation are summarized.For more details, including a step-by-step illustration, refer to [29].It should be noted that some model parameters show mutual dependencies, and therefore a tool for global parameter extraction is beneficial.
For circuit simulation results demonstrating the numerical stability and convergence of the model, please refer to [15] where several input decks, model cards and data from measurements or TCAD simulations are provided for benchmarking.

A.1. LONG-CHANNEL OTFTs
First, the structural and material parameters are set to the best knowledge to their physical values.With all short-channel models switched off (Schottky-barrier models, subthresholdswing degradation, threshold-voltage roll-off, DIBL effect), the DC parameters for mobility, threshold voltage and subthreshold swing are adapted to obtain a good fitting to the measured transfer and output characteristics of the device with the largest channel length.If devices in a multi-finger layout with varying numbers of fingers or varying finger width are available, this will make it possible to extract the current-fringing parameter δ fit .

A.2. SHORT-CHANNEL OTFTs
The short-channel model extensions related to thresholdvoltage roll-off, DIBL and subthreshold-swing degradation are switched on.The corresponding model parameters are adapted to obtain a good agreement between model and measurement data when these effects are visible in the transfer characteristics of short-channel OTFTs.The physically meaningful values d poi,swing = d poi,dibl = t diel and d poi,rolloff = t diel + t osc (and in the case of coplanar OTFTs: q co = 1) can be used as a starting point.Next, focusing on the output characteristics, the ohmic contact resistance R contact is adjusted together with the power-law mobility factor β.
If the output characteristics show a region of nonlinearity in the linear operation region, the Schottky-barrier models must be enabled.By simultaneously adapting all related parameters, the shape of the non-linear region is adapted.Please note that the non-linear injection model has an impact on the effective mobility in the channel.Therefore, any modification of the model parameters for nonlinear injection makes it necessary to readjust the mobility parameters.Finally, a reinspection of devices with different channel lengths reveals for which model parameters a binning is necessary, resulting in slightly different model cards depending on the channel length.The extracted values for the model parameters from the plots in Fig. 4b and c are shown in the Appendix, Table 1.In this case, the only model parameter which has to be adapted for channel lengths from 1 μm to 10.5 μm is the ohmic contact resistance [14].

A.3. VARIABILITY
Figure 4d illustrates how the model parameters for the drain-current variability can be extracted from a plot of the normalized drain-current variance σ 2 I ds /I 2 ds as a function of the mean-value drain current E[I ds ].In a first step, the parameter α * is set to zero.In the subthreshold region, (i.e., above the leakage-current regime), a specific gate-source voltage is selected, and N t,var at this gate-source voltage is calculated.Black dashed lines show the results of the model without the mobility-fluctuation effect (α * = 0).In a second step, using the extracted value of N t,var , the parameter α * is calculated at the maximum gate-source voltage.Note that the two selected gate-source voltages (subthreshold region and maximum |V gs |) correspond to specific experimental values of σ 2 I ds /I 2 ds that define the subthreshold and maximum-|V gs | asymptotes that are depicted in Fig. 4d as red dashed lines.Extracted values for the model parameters are shown in the Appendix, Table 1.

B.1. LONG-CHANNEL OTFTs
The AC model for long-channel devices during lowfrequency operation does not require further fitting, because the charge-based capacitance model uses the same charge expressions as the DC model.Parameters controlling nonquasistatic effects must be set to C scale2 = C scale = 1.

B.2. SHORT-CHANNEL OTFTs
By comparing the model to low-frequency measurements of the internodal capacitances in short-channel transistors, the corresponding fitting parameters are adapted.Setting of K fit = 1, K r = 1 and ν = 0 is used as a starting point [15].

B.3. NON-QUASISTATIC EFFECTs
From capacitance measurements performed at high frequencies, the model may be adapted by decreasing the values of C scale2 and C scale , thus making it possible to extract proper values for the parameters τ scale and p scale in equation (7).As noted in Section III-C, values of C scale2 and C scale have to be provided externally to an AC simulation according to the frequency of interest.

B.4. NOISE
Noise parameters are extracted from plots of the power spectral density (PSD) versus the frequency (σ ) and versus the drain current (λ tun , N t ) (refer to Fig. 6).From the abovethreshold characteristics, the Coulomb scattering coefficient α c is extracted, whereas the Hooge parameter α H is adapted for the subthreshold region [28].Table 1 in the Appendix gives the extracted values for the model parameters.

V. CONCLUSION
The presented compact model for OTFTs fabricated in the staggered or the coplanar device architecture presented here provides great flexibility to capture typical effects related to a small channel length or non-linear injection at the contacts.Additionally, the model includes expressions for the intrinsic and extrinsic charges in the devices, allowing for AC and transient circuit simulations.Extensions allow for an estimation of the drain-current variability and low-frequency noise.Its accuracy has been demonstrated by comparison to measurements performed on OTFTs with submicron channel lengths.The equation package has been implemented in Verilog-A and is available in [29] for circuit design, simulation and optimization to advance the integration of OTFTs into more complex systems.

FIGURE 1 .
FIGURE 1. Schematic cross section of OTFTs in the (a) bottom-gate, bottom-contact (BC; coplanar) and (b) bottom-gate, top-contact (TC; staggered) device architecture.(c) Schematic top view of a BC TFT close to the gate dielectric surface.For the compact model, it is assumed that the charge density in the source (drain) region is equal to the charge density at the source (drain) end of the channel [15], [21].(d) Schematic of the current flowing in a planar OTFT.If there are fringing regions, the current not only flows directly from source to drain, but also in the fringing regions (dotted arrows).As the paths through the fringing regions are longer, the current density in the fringing regions is smaller than in the center of the channel.At the probe point, the current density is assumed to be low.However, the density of accumulated quasi-mobile charges is assumed to be the same as in the center of the channel.

FIGURE 2 .
FIGURE 2. Influence of short-channel model parameters on the transfer characteristics of an OTFT.Parameter d poi is the "point of interest" in the calculation of the potential barrier height in the channel region.Its value depends on whether the OTFT is operated (a) below the threshold voltage (in which case the most conductive path is located some distance away from the dielectric interface, and d poi defines the subthreshold swing), or (b) above the threshold voltage (in which case the accumulation channel is formed close to the dielectric interface, and d poi is used to calculate the threshold voltage or the drain-induced barrier lowering, DIBL).

FIGURE 3 .
FIGURE 3. Influence of four different parameters that are part of the Schottky-barrier contact model on the DC output characteristics of OTFTs.The source-related parameters B0 , L inj and d B are the Schottky barrier height, the injection length (approximately the gate-to-contact overlap length in staggered transistors, or the thickness of the accumulation channel in coplanar OTFTs), and the distance of the point of injection from the interface to the gate dielectric, respectively.The parameter θ helps to adapt the curve considering an additional voltage drop across the Schottky barrier at the drain.

FIGURE 4 .
FIGURE 4. (a) Schematic cross section of DPh-DNTT TFTs fabricated in the coplanar device architecture [19].(b) Output and (c) transfer characteristics calculated using the compact model including short-channel effects and non-linear injection at the contacts, compared with results of measurements performed on a device with a channel length of 1 μm.(d) Normalized drain-current variance σ 2 I DS /I 2 DS versus mean-value drain current E[I DS ] for OTFTs with L ch = 3 μm.The experimental mean values were calculated over a population of 16 nominally identical transistors [17].

FIGURE 5 .
FIGURE 5. Voltage dependence of the quasistatic capacitances C gs and C gd of staggered short-channel OTFTs (L ch = 2μm) at V ds = −1V.The results from the compact model (solid lines) are compared to results from a TCAD Sentaurus simulation (dotted lines).The curves demonstrate the effect of the fitting parameters (a) K fit and (b) K r .

FIGURE 6 .
FIGURE 6. Influence of the parameters of the model for the LFN on the noise power spectral density (PSD).(a) PSD versus frequency with variation of the exponent in the 1/f σ behavior.(b) PSD versus frequency with variation of the parameter N t .(c) PSD versus drain current at a fixed drain-source voltage and a fixed frequency at which the parameter α c is varied.(d) The LFN model compared to noise measurements performed on staggered OTFTs (averaged over 15 devices with L = 20 μm and W = 100 μm).The μ noise dominates at lower currents, controlled in the model via parameter α H .At higher currents, LFN is due to N noise.In this regime, the model is fitted by parameter α c to measurements [28].

FIGURE 7 .
FIGURE 7. Voltage dependence of the quasistatic capacitances of a short-channel staggered OTFT (L ch = 2μm) at (a) V ds = −1 V and (b) V gs = −2.7 v. Compact model: solid lines, TCAD Sentaurus simulations: dotted lines.The parameters of the capacitance model are chosen as follows: K r = 0.15, K fit = 0.24, and ν = 0.3.(c) Small-signal gain (h 21 ) of staggered (bottom-gate, top-contact; TC) and (d) coplanar (bottom-gate, bottom-contact, BC) OTFTs with L ch = 0.67μm and asymmetric gate-to-source and gate-to-drain overlaps at V gs = V ds = −3 textV [21].Model: solid lines, measurements: dotted lines.The pictogram in (e) shows the asymmetry with a constant total overlap L ov,GS + L ov,GD = 10μm for the measured devices.