Investigations on Wide-Gap Al0.21Ga0.79N Channel MOS-HFETs With In0.12Al0.76Ga0.12N Barrier/Buffer and Drain Field-Plate

This work investigates, for the first time, wide-gap Al0.21Ga0.79N channel metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with In0.12Al0.76Ga0.12N barrier/buffer and drain field-plate (DFP) designs. High-k and wide-gap Al2O3 was grown as the gate oxide and surface passivation by using non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. A control device having the same epitaxial layers, except with In0.12Al0.88N barrier/buffer was studied in comparison. Enhanced spontaneous polarization effect, improved interfacial quality, and enhanced carrier confinement have been achieved by using the In0.12Al0.76Ga0.12N barrier/buffer design, which has successfully resulted in improved carrier transport, increased electron concentration, and high current densities. The present In0.12Al0.76Ga0.12N/AlN/Al0.21Ga0.79N MOS-HFET design with (without) DFP design has demonstrated superior maximum drain-source current density <inline-formula> <tex-math notation="LaTeX">$(I_{DS, max})$ </tex-math></inline-formula> of >1 (>1) A/mm at <inline-formula> <tex-math notation="LaTeX">$V_{DS}\,\,=$ </tex-math></inline-formula> 20 V, high saturated drain-source current density at <inline-formula> <tex-math notation="LaTeX">$V_{GS}\,\,=$ </tex-math></inline-formula> 0 V <inline-formula> <tex-math notation="LaTeX">$(I_{DSS0})$ </tex-math></inline-formula> of 791.1 (755) mA/mm, and low specific on-resistance <inline-formula> <tex-math notation="LaTeX">$(R_{on, sp})$ </tex-math></inline-formula> of 2.83 (2.81) <inline-formula> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula>/cm 2. High device figure-of-merit (FOM) on <inline-formula> <tex-math notation="LaTeX">$BV_{DS}^{2}/R_{on, sp}$ </tex-math></inline-formula> of 93.7 (75.4) MW/cm 2 was also obtained with the three-terminal on-state drain-source breakdown voltage <inline-formula> <tex-math notation="LaTeX">$(BV_{DS})$ </tex-math></inline-formula> of 515 (460) V. The present design is promisingly advantageous to high-current and high-voltage power-switching circuit applications.


FIGURE 1. Schematic device structures of (a) the control sample A1 and (b)-(c) the present MOS-HFET designs of samples B1-B2.
transport would be degraded by the heterointerface defects and alloy scattering caused by different growth temperatures between InN and AlN during epitaxy. This work explores a novel In 0.12 Al 0.76 Ga 0.12 N/AlN/ Al 0.21 Ga 0.79 N heterostructural design to improve the carrier transport with preserved good polarization effect. Besides, a wide-gap In 0.12 Al 0.76 Ga 0.12 N (In 0.12 Al 0.88 N) buffer below the conduction channel was devised in the present (control) devices to enhance the carrier confinement, which would further increase both the electron concentration and current density. In addition, designs of MOS-gate, high-k gate dielectric, oxide passivation, and DFP [20], [21] were integrated to improve the gate modulation capability, reduce gate leakages, alleviate gate-drain electric field, and improve breakdown performance. Al 2 O 3 was grown as gate dielectric and surface passivation layer at the same time by using a costeffective non-vacuum ultrasonic spray pyrolysis deposition (USPD) [22], [23] technique.

II. MATERIAL GROWTH AND DEVICE FABRICATION
Figs. 1(a)-(c) show the schematic device structures of (a) the control In 0.12 Al 0.88 N/AlN/Al 0.21 Ga 0.79 N MOS-HFET (sample A1) and (b)/(c) the present In 0.12 Al 0.76 Ga 0.12 N/AlN/ Al 0.21 Ga 0.79 N MOS-HFET designs with/without DFP (samples B1/B2), respectively. The epitaxial structures were grown on a SiC substrate by using a low-pressure metal-organic chemical vapor deposition (LP-MOCVD) system. Both samples B1 and B2 have the same layer structures, including the GaN nucleation layer, an intrinsic 10-nm In 0.12 Al 0.76 Ga 0.12 N buffer, an intrinsic 20-nm Al 0.21 Ga 0.79 N channel, an intrinsic 1-nm AlN layer, an intrinsic 10-nm In 0.12 Al 0.76 Ga 0.12 N barrier, and a 2-nm Si-doped (∼3 × 10 18 cm -3 ) GaN capping layer, as shown in Figs. 1(b) and (c). The control sample A1 has the identical epitaxial structures with respect to the present samples B1-B2, except replacing with the In 0.12 Al 0.88 N barrier and buffer, as shown in Fig. 1(a).
All the three devices were fabricated at the same time. Standard photo-lithography and lift-off techniques were used for device fabrication [24]. For sample B2, mesa etching was first performed to provide electrical isolation for neighboring devices by using an inductively coupled-plasma reactive ion etcher (ICP-RIE). The etching gas is BCl 3 with a flow rate of 40 sccm. The ICP/RF power settings are both 110/110 W. The chamber pressure is 1 pa and the etching time is 500 seconds. Dry etching was conducted after photolithography to remove the GaN capper between source and drain electrodes. The flow rates of the BCl 3 /Cl 2 mixture gases are 10/5 sccm, with the ICP/RF power settings of 100/12 W. The etching time is 80 seconds under chamber pressure of 1 pa. Metal stacks of Ti (20 nm)/Al (100 nm)/ Ni (20 nm)/Au (70 nm) were then evaporated as the source/drain electrodes. The source/drain ohmic contacts were formed by annealing the sample at 950 • C for 60 seconds by using a ULVAC MILA-5000 rapid thermal annealing (RTA) system. Then, a 30-nm Al 2 O 3 was grown on the exposed barrier surface between source and drain electrodes by using the USPD technique. Finally, after the photolithography to expose the gate/DFP windows, metal stacks of Ni (150 nm)/Au (40 nm) were evaporated on the Al 2 O 3 surface to form both the gate and DFP structures, as shown in Fig. 1(c). The same fabrication procedures were applied to samples A1 and B1, except without the formation of DFP, as shown in Fig. 1(a) and 1(b). Besides, all three samples were gate recessed to the same depth by performing the dry etching simultaneously. The studied devices have the same gate length (L G ) of 2 μm, gate-to-source spacing of 2 μm, and gate-to-drain spacing of 10 μm. For sample B2, the DFP length (L DFP ) is 2 μm, which has resulted in an effective gate-to-drain separation of 8 μm.
The secondary ion-mass spectroscopy (SIMS) profiles of (a) the epitaxial structure (sample A) for the control device and (b) the present epitaxial design (sample B) for samples B1-B2, as shown in Figs. 2(a)-(b), respectively. Under the n-GaN capping layer, apparent decreases in the Gacomposition distribution were observed in sample A, as compared to sample B. The composition variations of the epitaxial structures were verified with the sample designs. The cross-sectional transmission electron microscopy (TEM) photo of the MOS-gate of sample B2 is also shown in Fig. 2(c). The layer thickness of the USPD-grown Al 2 O 3 was verified to be 30 nm. Figs. 3(a) and 3(b) show the atomic force microscopy (AFM) photos of surface morphologies for the In 0.12 Al 0.76 Ga 0.12 N barrier of sample B2 after the gaterecess etching and further after the deposition of Al 2 O 3 by using USPD, respectively. The average root-mean-square surface roughness after (before) the USPD-deposited Al 2 O 3 was determined to be 0.6 (0.77) nm. The surface flatness was apparently degraded by using ICP-RIE and, then, was effectively improved by using USPD.

III. EXPERIMENTAL RESULTS AND DISCUSSION
Hall measurements were conducted for both samples A and B at 300 K under a magnetic field of 5000 G. The electron mobility (μ n ), two-dimensional electron gas concentration (n 2DEG ), and he μ n -n 2DEG product were found to be 417 (282) cm 2 /V-sec, 3.6 (3.5) × 10 13 cm −2 , and 1.5 (0.99) × 10 16 (V-sec) −1 for sample B (A). Samples A-B have similar n 2DEG concentrations since the same In-ratio of 0.12 was devised for the In 0.12 Al 0.88 N and In 0.12 Al 0.76 Ga 0.12 N barriers. Similar polarization effects were maintained to provide appropriate comparison for the studied devices. Due to enhanced carrier confinement by the devised  wide-gap In 0.12 Al 0.76 Ga 0.12 N or In 0.12 Al 0.88 N barrier/buffer, the obtained n 2DEG values are higher than our previous works [15], [16] and other InAlN/AlGaN device [25]. Moreover, the μ n and μ n -n 2DEG product of sample B have been significantly enhanced due to the improved interfacial property in the In 0.12 Al 0.76 Ga 0.12 N/AlN/Al 0.21 Ga 0.79 N heterostructure. High current densities are expected for the present In 0.12 Al 0.88 N/AlN/Al 0.21 Ga 0.79 N MOS-HFET designs.
The measured C-V hysteresis characteristics for the fabricated MOS diodes for samples A and B are shown in Figs. 4(a)-(b), respectively. The diode areas are the same of 31400 μm 2 . The applied voltage was increased from −9 V to 6 V and swept back immediately to the starting voltage. The hysteresis voltage ( V) was defined to be the bias difference between mid-points of the C-V curves. The V was determined to be about 1 (37) mV for sample B (A). Significant decrease in V for sample B, as compared to sample A, has been obtained, indicating the interface property was effectively improved by using the In 0.12 Al 0.76 Ga 0.12 N barrier.  was effectively reduced by the oxide passivation by using USPD. The comparisons of both V and α H are consistent with the observed enhanced μ n behavior in the devised In 0.12 Al 0.76 Ga 0.12 N/AlN/Al 0.21 Ga 0.79 N heterostructure. Besides, the transfer length method (TLM) [28] was employed to measure the specific contact resistivity (ρ c ) and contact resistances (R C ). ρ c and R C were characterized to be 8.7 × 10 −6 (1.8 × 10 -5 ) -cm 2 and 0.18 (0.26) -mm for samples B1-B2 (A1), which are much lower than those wide-gap channel devices of our previous works [15], [16]. It is mainly contributed by the devised n-GaN capping layer to greatly improve the source/drain ohmic contacts. The improved interfacial quality by using the In 0.12 Al 0.76 Ga 0.12 N barrier has further improved the ohmic contact characteristics.
The common-source current-voltage (I DS -V DS ) characteristics source/drain ohmic contacts. The improved interfacial quality (left) at 300 K and the transfer extrinsic transconductance (g m ) and saturated drain-source current (I DS ) density vs. the applied V GS for samples A1, B1, and B2 are shown in Figs. 6(a)-(c), respectively. The applied V GS bias was increased from −8 (−12) V to 6 (6) V at 2 (3) V/step for samples B1-B2 (A1) by using a KEITHLEY 4200 analyzer. All the studied devices have shown good pinch-off phenomena, indicating the good gate modulation capability by the high-k MOS-gate structure. As expected by the Hall data, the enhanced current densities in samples B1-B2 have exceeded the instrumentation limit of the KEITHLEY 4200 analyzer, as observed in Figs. 6(b)-(c). The measured I DS at V GS = 0 V (I DSS0 ) and maximum I DS (I DS,max ) densities at V DS = 20 V were found to be 628 mA/mm and 978.5 mA/mm, 755 mA/mm and >1 A/mm, and 791.1 mA/mm and >1 A/mm for samples A1, B1, and B2, respectively. The corresponding maximum extrinsic transconductance (g m,max ) values are 89.7 mS/mm, 148.3 mS/mm, and 150.8 mS/mm. Both samples B1 and B2 have demonstrated superior current drive capability. It was contributed by the improved channel conductivity by the devised In 0.12 Al 0.76 Ga 0.12 N/AlN/ Al 0.21 Ga 0.79 N heterostructure. Sample B2 (B1) has shown about 26% (20%) and 68% (65%) improvements in I DSS0 and g m,max performances as compared to sample A1. Higher I DSS0 density of sample B2 than B1 is due to the increased electric field resulted from the decreased gate-to-drain spacing by the inserted 2-μm DFP structure, as shown in Fig. 1(c). Consequently, enhanced g m,max performances have been achieved by the improved current densities in the present samples B1 and B2. The devised MOS-HFETs are superior to our previous woks [15], [16] and other wide-gap-channel devices of g m,max = 16 mS/mm and I DS,max = 90 mA/mm [25], g m,max = 9 mS/mm and I DS,max = 350 mA/mm [29], I DS,max = 114 mA/mm [30], g m,max = 38 mS/mm and I DS,max = 635 mA/mm [31], I DS,max = 420 mA/mm [32], g m,max = 2.4 mS/mm and I DS,max = 13 mA/mm [33], and g m,max = 97.9 mS/mm and I DS,max = 473 mA/mm [34].
The gate-voltage swing (GVS) was defined to be the available V GS range where the g m value was within 90% of g m,max . Sample A has wider GVS of 4.9 V than 2.9 (2.3) V of sample B1 (B2), indicating its good linearity. The threshold voltage (V th ) was defined as the V GS intercept by the extrapolated line of (I DS ) 1/2 . Sample A1 has the lowest V th of about −11 V as compared to −6.8 (−8.6) V of sample B1 (B2). The observed small V th deviations from the C-V curves in Fig. 4 was due the different anode/cathode separation as compared to the MOS-HFETs. Higher GVS and lower V th of sample A1 than sample B1 were due to its wider bandgap and higher conduction-band discontinuity ( E C ) of the In 0.12 Al 0.88 N barrier/buffer than those of In 0.12 Al 0.76 Ga 0.12 N. Moreover, higher I DS density of sample B2 has resulted in its lower V th value than sample B1, since more negative V GS was needed to deplete the channel. The specific on-resistances (R on,sp ) of samples A1, B1, and B2 were determined to be 5.14 m /cm 2 , 2.81 m /cm 2 , and 2.83 m /cm 2 . The present samples B2/B1 with/without DFP have shown comparable R on,sp values. They have also exhibited lower R on,sp than sample A1. Since R on,sp was extracted at low electric fields, reduced R on,sp was resulted from the improved channel conductivity by the devised In 0.12 Al 0.76 Ga 0.12 N/AlN/Al 0.21 Ga 0.79 N heterostructure. It is consistent with the characterized Hall data. The present devices has shown lower R on,sp than other AlGaN channel devices [25], [35]. Besides, the subthreshold swing (SS)  and on/off-current ratios (I on /I off ) for the studied samples A1, B1, and B2 were found to be 112.2 mV/dec and 2.2 × 10 8 , 104 mV/dec and > 10 9 , and 124.3 mV/dec and > 10 9 , respectively. The studied devices have shown higher I on /I off ratios than other works [25], [29], [35]. It was due to the devised In 0.12 Al 0.88 N or In 0.12 Al 0.76 Ga 0.12 N barrier/buffer, since I on was increased by the improved self-polarization effect, whereas the I off densities were reduced by the widegap barrier/buffer. Besides, improved gate insulation, g m,max gain, and I DS density resulted from the MOS-gate design with high-k dielectric, wide-gap Al 2 O 3 , and good surface passivation have also contributed to the enhanced switching performance. Moreover, the I off leakage in sample B2 was further suppressed by the DFP design. High I on /I off and superior SS performances with decreased R on,sp of the present design are advantageous to the power-switching circuit applications.
The two-terminal off-state gate-drain breakdown voltage (BV GD ) and three-terminal on-state drain-source breakdown voltage (BV DS ) characteristics of samples A1, B1, and B2 at 300 K are shown in Figs. 7 and 8, respectively. BV GD and BV DS were determined to be the corresponding V GD and V DS biases where the I GD and I DS densities were equal to 1 μA/mm. The source terminal remained float while characterizing BV GD , and the V GS was biased at −12 V for measuring BV DS for all devices. BV GD and BV DS were found to be −410 V and 425 V, −465 V and 460 V, and −455 V and 515 V for samples A1, B1, and B2. Good breakdown characteristics have been obtained in the studied devices. It is attributed by the reduced gate/substrate leakage currents by the devised MOS-gate structure with the USPD-grown Al 2 O 3 surface passivation, wide-gap Al 0.21 Ga 0.79 N channel, and widegap barrier/buffer using In 0.12 Al 0.76 Ga 0.12 N or In 0.12 Al 0.88 N compounds. About 13% improvement in BV GD was obtained in sample B1 with respect to sample A1. It is possibly due to the decreased gate leakage by improved interfacial quality of the devised In 0.12 Al 0.76 Ga 0.12 N/AlN/ Al 0.21 Ga 0.79 N heterostructure, as discussed before. Though BV GD was slightly degraded in sample B2 due to reduced gate-to-drain separation, it has shown about 21% (12) improvement in BV DS as compared to sample A1 (B1). It is because that the electric field distribution has been effectively smoothed out [21] by the DFP design. BV 2 DS /R on,sp is known as an important device figure-of-merit (FOM) for power switching applications. The present In 0.12 Al 0.76 Ga 0.12 N/AlN/Al 0.21 Ga 0.79 N MOS-HFET with (without) DFP design has shown superior device FOM of 93.7 (75.4) MW/cm 2 as compared to other AlGaN channel devices [25], [34], [35]. Table 1 summarizes the device characteristics of the studied devices. Superior current densities, high breakdown voltages, and improved switching characteristics have been successfully achieved in the present design.

IV. CONCLUSION
Wide-gap-channel In 0.12 Al 0.76 Ga 0.12 N/AlN/Al 0.21 Ga 0.79 N MOS-HFETs grown on a SiC substrate with/without DFP have been reported for the first time. Superior I DS,max in excess of 1 A/mm with low R on,sp has been achieved due to improved polarization effect, interfacial property, and carrier confinement by the In 0.12 Al 0.76 Ga 0.12 N barrier/buffer design. The DFP was further integrated to improve the breakdown