Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN MIS-HEMTs IC Platform

In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.


I. INTRODUCTION
AlGaN/GaN HEMTs become a promising candidate for power converter switches in recent years due to high switching frequency, power density, and conversion efficiency [1], [2], [3], [4]. Stray inductances and commutation loops are the main factors that limit the switching speed of GaN-based power electronics with discrete driver chips [5]. The lateral structure of the GaN-on-Si technology allows the monolithic integration of several devices for a compact design to restrain parasitic effects [6].
For GaN devices, the dual-gate technology could be applied to realize the unique function and reduce requirements on the extra component [7], [8], [9], [10]. With the back gate technology, Hazra et al. [8] proposed a dualgate structure to control the threshold voltage. A cascade dual-gate structure is proposed by Lin et al. to suppress current collapse [11]. Gong et al. [12] reported a normally-on dual-gate AlGaN/GaN MIS (metal-insulator-semiconductor) HEMTs (high-electron-mobility-transistors) with Al 2 O 3 gate oxide layer, which showed a lower reverse gate leakage current than its normally-on dual-gate Schottky HFET, while the gate insulators are also used to enhance the gate swing [13], [14], [15]. However, all the above applications are examined with depletion-mode (D-mode) devices. Since D-mode HEMT technology requires a negative voltage control, its counterpart, the enhancement-mode (E-mode) HEMT, is more suitable for the power conversion application [16], [17]. Wolf et al. [18] fabricated a monolithically integrated bidirectional switch based on E-mode p-GaN HFETs using dual-gate technology.
For a high-level integrated power system, dual-gate technology is a feasible solution for monolithic design [19]. Chvála et al. demonstrated a monolithic NAND cell that is based on InAlN/GaN MIS-HEMTs with a maximum gate voltage of 3 V, and confirming the validity of the proposed models [20]. As an essential building block for digital circuits, implementing dual-gate E-mode NAND (DG-NAND) by p-GaN HEMTs with a smaller area provides an optimization method [21]. However, as a result of the limitations of p-GaN technology with low gate breakdown voltage, the gate driver voltage is limited to 5 V, which requires extra protection circuits for an all-GaN integrated circuit (IC) development. Moreover, the dynamic test is necessary to analyze the superior characteristics of the dual-gate design.
In this work, we demonstrate double E-mode devices NAND (DD-NAND) and dual-gate E-mode device NAND logic gate circuits by monolithic integrated E/D mode MIS-HEMTs. The static and dynamic measurements are conducted to evaluate the performance of the logic gate. The experimental investigation is reported about the compact solution to logic blocks for power IC applications.

II. EXPERIMENTS AND DISCUSSION
Fig. 1 depicts a schematic cross-section of the proposed DG-NAND circuit by utilizing the AlGaN/GaN MIS-HEMTs technology. All devices are fabricated on a Si substrate consisting of a 4.2 μm GaN buffer layer, a 420 nm layer GaN channel layer, a 1 nm AlN spacer and a 25 nm AlGaN layer. GaN devices with D-mode and E-mode are capable of forming logic circuits by Direct Coupled FET Logic (DCFL) structure [22], [23]. For E-mode devices, recessed-gate technology has been utilized [24], and MIS gates have been implemented to extend the swing voltage of the gate and thus improve performance [25]. An interconnect layer of Al is deposited to allow the integration of monolithic integrated circuits. An in-depth description of the fabrication process is provided in [26]. The D-mode device features a 5 μm source to gate distance (L GS ), a 3 μm gate length (L G ), a 5 μm gate width (W G ), and a 10 μm drain to gate distance (L GD ). For dual-gate E-mode device dimension, L GS /L G /L GD /W G = 5/3/5/200 μm, and the separation between the two gates is set to 10 μm.
The schematic diagram of the GaN-based double device E-mode (DD-E) structure is illustrated in the red border, as shown in Fig. 2 (a) and reported in [19]. Unlike traditional NAND design uses two E-mode devices connected in series [27], the two E-mode devices share the common pad for the connection part to optimize the chip layout. The D-mode device functions as an active load resistor and two E-mode gates serve as logic input. In this work, the presented GaN-based dual-gate E-mode (DG-E) structure is used to replace the counterpart DD-E structure. Thus the DG-NAND logic circuit is formed, as shown in Fig. 2 (c). The employment of dual-gate devices aims to replace two E-mode HEMTs in the logic circuit design and eliminates redundant ohmic contacts [28], which could reduce onstate resistance and parasitic capacitance. The corresponding microscope views of the DD-NAND and DG-NAND circuits are shown in Fig. 2 (b) and Fig. 2 (d), respectively. The size of the layout with the probe pad reduces from 0.155 mm 2 to 0.118 mm 2 owing to the advantages of a dual-gate structure.

A. EXPERIMENTAL SETUP
The static test platform is illustrated in Fig. 3 (a), and the experimental setup is represented by the blue and black connection. A fixed DC bias voltage is provided to V 2 . It is worth pointing out that DD-E structure measurements use V 1 and V 2 to regulate the switching states of the two E-mode devices. For DG-E device, V 1 and V 2 are utilized to control the G 1 and G 2 gates of the dual-gate E-mode device, as shown in Fig. 3 (a) left part. Meanwhile, the static performance of the NAND circuits is monitored by the same analyzer, the supply voltage V DD is provided. The dynamic experimental setup is represented by the red and black arrows in Fig. 3 (a). Two input signals V 1 and V 2 are supplied by

. (a) The experimental setup diagram of the DG-NAND logic circuit for static (blue and black line) and dynamic measurement (red and black line), (b) test setup, (c) monolithic integrated GaN driver with DG-NAND circuit.
a signal generator, and they are set to output different logic levels. The dynamic performance of the NAND logic circuit is monitored and recorded by an oscilloscope. The test setup is demonstrated in Fig. 3 (b). Fig. 3 (c) shows an integration of the logic unit into the pre-drive module [13], in which the dual-gate NAND circuit could be utilized to replace the first-level DCFL inverter in the driver stage. This method would contribute to the high integration level all-GaN power conversion system.

B. STATIC CHARACTERISTICS MEASUREMENT FOR DD-E STRUCTURE AND DG-E DEVICE
The characteristics of the devices and the NAND circuits were measured by an Agilent B1505A power device analyzer. As illustrated in Fig. 4 (a), the threshold voltage (V th ) of the DD-E structure is 1.9 V, and the V th of the DG-E device is 1.7 V. Fig. 4 (b) shows the I D -V D curve, the current density (I D, max ) is approaching 124.8 mA/mm when two gates are biased at 9 V for DD-E structure. As could be observed in Fig. 4 (b), the current density of the DG-E structure reaches a peak value of 133.9 mA/mm.

C. STATIC AND DYNAMIC CHARACTERISTICS MEASUREMENT FOR GAN-BASED TWO-INPUT NAND LOGIC CIRCUIT
In all-GaN monolithic IC design, the logic circuit serves as the drive control module applied to modify the drive voltage  based on the feedback signal [29]. The voltage transfer characteristics (VTC) of the investigated DG-NAND circuit are demonstrated in Fig. 5, and it is compared with the VTC of the DD-NAND circuit. A supply voltage V DD of 9 V is applied. The minimum output voltage (V OL ) of the DD-NAND circuit is about 1.69 V, and V OL of the DG-NAND circuit is nearly 1.56 V. Meanwhile, the output voltage of 9 V are obtained in Fig. 5 The NAND dynamic test is used to emulate different operating conditions on an all-GaN integrated power chip. Logic circuits are designed to generate a drive signal based on the input operating signal (V 1 ) and enable signal (V 2 ) as shown in Fig. 3 (c). Different output states could be observed in the output waveforms by adjusting the phase between the input operating signal and enable signal. In Fig. 6, the voltage output waveforms of the DG-NAND and DD-NAND logic circuits working at 100 kHz are monitored by the oscilloscope. The black and red curves represent the gate voltages applied on the first gate and the second gate, respectively, from signal generators. When the DD-NAND circuit and DG-NAND circuit work at a switching frequency of 100 kHz, the falling time of the DG-NAND circuit is 15 percent shorter than the DD-NAND circuit.   Table 1 compares the dual gate technology for different applications. References [8], [10], and [12] apply a second gate in the D-mode to improve device performance. Papers [18] and [30] uses a second gate to complete the design of a bidirectional device. Both papers [20] and [21] utilize a dual-gate structure for the functional block of the monolithic integrated GaN platform. Verifying the dynamic performance and comparing it with the conventional design is necessary. In this paper, a logic circuit module for the GaN MIS-HEMTs platform is designed based on DG-E device and compared with the conventional design of the DD-E structure through dynamic and static tests. Furthermore, this design also exploits the advantages of the MIS-HEMTs platform. The large gate swing lowers the demand for gate voltage protection, resulting in a compact design.

III. CONCLUSION
In this work, two types of AlGaN/GaN -based NAND logic circuits are demonstrated. Static and dynamic measurements experimentally validate the NAND logic circuit of both structures. The dual-gate E-mode device NAND logic cell utilizes fewer devices and the die area drops by 24%. Indicated parasitic parameters are also reduced due to the elimination of redundant ohmic contacts. The static characterization of the dual-gate E-mode device NAND circuit indicates a lower V OL about 1.46 V. From the dynamic measurement results, the DG-NAND logic circuit observed less falling time, which decreased by 15%. Furthermore, the dual-gate NAND will be applied as a subunit of the drive unit development for compact design and functional integration of the all-GaN MIS-HEMTs IC platform.