Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application

In this paper, floating fin structured vertically stacked nanosheet gate-all-around (GAA) metal oxide semiconductor field-effect transistor (FNS) is proposed for low power logic device applications. To verify the electrical performance of the proposed device, three-dimensional (3-D) technology computer-aided design (TCAD) device/circuit simulations are performed with calibrated device model parameters. As a result, it is found that gate propagation delay <inline-formula> <tex-math notation="LaTeX">$({\tau }_{\mathrm{ delay}})$ </tex-math></inline-formula> and dynamic power <inline-formula> <tex-math notation="LaTeX">$(P_{\mathrm{ dyn}})$ </tex-math></inline-formula> are improved by 8% and 19%. respectively as compared to conventional vertically stacked lateral nanosheet (LNS). Through the rigorous analysis on the resistance and capacitance components of FNS and LNS, it is clearly revealed that the <inline-formula> <tex-math notation="LaTeX">${\tau }_{\mathrm{ delay}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm{ dyn}}$ </tex-math></inline-formula> are improved at the same <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm{ dyn}}$ </tex-math></inline-formula> (50 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula>) and <inline-formula> <tex-math notation="LaTeX">${\tau }_{\mathrm{ delay}}$ </tex-math></inline-formula> (187 GHz) by the reduced effective capacitance which results from the diminished gate-to-sorece/drain overlap area. Based on the TCAD simulation studies, it is expected that the FNS is suitable for next generation logic digital applications.


I. INTRODUCTION
The scaling of complementary metal-oxide-semiconductor (CMOS) has been investigated since the emergence of semiconductor integrated circuits [1]. There are several options to sustain the scaling-down for future semiconductor devices. Among various devices after Fin fieldeffect transistor (FinFET) technology, gate-all-around (GAA) MOSFETs have been considered as one of the most promising devices [2], [3]. Thanks to two main reasons. The first is excellent gate controllability and the second is compatibility with the FinFET process [4], [5]. However, single GAA MOSFETs with a circular-shaped channel have the disadvantage that the current per unit area is lower than FinFETs.
To overcome this challenge, vertically stacked GAA-MOSFETs with lateral nanosheet (NS)-shaped channels (LNS) have been extensively studied to enhance the current per unit area [5], [6], [7]. However, unfortunately, LNS has the disadvantage that the effective capacitance is significantly increased by the overlap capacitance between source/drain (S/D) and channel to-channel space (T sp ) [7] with the enhancement of the current drivability per unit area as contrast to conventional FinFETs.
Thus, the gate propagation delay (τ delay ) is degraded by the increased effective capacitance and the dynamic power (P dyn ) is also more consumed although the τ delay is maintained. To mitigate the degradation of the device performances, the process to introduce the inner spacers between the channels has been considered [5]. However, there is a disadvantage in terms of fabrication cost since the formation of the inner spacers requires additional process steps. Also, it is hard to form the inner spacers with ideal rectangular   shape [8]. Unexpectedly, a semicircular shape is formed by selectively etching the SiGe used as a sacrificial layer, which halves the effects of the overlap capacitance reduction. In this paper, a novel fin-shaped vertically stacked NS device (FNS) is proposed to improve power, performance and area (PPA) as shown in Fig. 1(a). In order to confirm the feasibility of FNS, the process flow, which improves the structural weak point of LNS, is demonstrated. Furthermore, to verify the device/circuit-level performances, the gains of the τ delay and the P dyn are extracted from inverter characteristics with geometric parameters of Fig. 1(c) and the origin of the performance improvement is rigorously investigated by analyzing the capacitance and resistance components of FNS and LNS.

A. CALIBRATION CONDITIONS
For accurate technology computer-aided design (TCAD) simulations, model parameters are calibrated by referring the experimental data with two channels stacked on top of bulk Si where the stacked nanowires are modeled based on the transmission electron microscope (TEM) images [9]. Then, drift-diffusion approximation is applied under 0.7 V of supplied voltage (V dd ) condition to calibrate drain current (I d )-gate voltage (V g ) characteristics as shown in Fig. 2. Shockley-Read-Hall (SRH) and Lombardi models are calibrated to reflect generation-recombination and mobility of carriers, respectively [10]. Also, quantum confinement is considered owing to thin channel thickness (T ch ) and threshold voltage (V th ) is tuned by adjusting the work-function of metal. Based on the calibrated models for the short channel nanowire devices with high-κ/metal gate structure [11], (100)<110> mobility (LNS) and (110)<110> mobility (FNS) are reflected using Lombardi auto-orientation model depending on the channel orientation of each device. A contact resistivity of ρ C = 1 × 10 −10 -cm 2 is used in LNS and FNS to evaluate advanced technology nodes, and the resistivity value referred from the experimental results of previous studies. [12], [13]. Here, it should be noted that two stacked channels are utilized for the simulations of FNS and LNS. Recently, there was the report that the number of channel stacks is limited in terms of power and performance. At the same V dd , speed gain can be maximized up to 4 stacks and it starts to decrease with the number of stacks larger than 4. Also, the speed gain at the same power continuously decreases as the number of stacks increases. These phenomena can be explained by noticing that the increase of the current tends to be diminished with the increasing number of stacks due to the increase of series resistance [14]. Thus, 2 or 3 stacks have been considered as an optimal number and thereby FNS and LNS with 2-stacked channels are evaluated by considering the complexity and feasibility of the fabrication process.

B. DEVICE STRUCTURE
The device parameters of LNS and FNS with the vertically stacked two NSs based on the 3-nm node of the international roadmap for devices and systems (IRDS) 2018 [15] are shown in Table 1. LNS has channel width (W ch ) of 25 nm and T ch of 7 nm whereas W ch of 7 nm and T ch of 25 nm are applied to FNS. Accordingly, both the devices have the same effective width (W eff ) of 116 nm by the formula [W ch × π +(T ch − W ch )×2]×2 and [T ch ×π +(W ch −T ch )×2]×2, respectively. For both LNS and FNS, gate length (L g ) of 15 nm and effective gate length (L eff ) of 13 nm are used where L eff is defined by L g without overlap length. NS-to-NS space (T sp ) is 15 nm, inner

C. PROCESS FLOW
The fabrication process flow of the FNS is highly compatible with LNS as shown in Fig. 3. Although FNS has the disadvantages in terms of increasing the number of stacks since fins should be vertically stacked, FNS is applicable through the improvement of the current channel stacking process in the case of stacking 2 or 3 channels which has been considered as an optimal number in terms of power and performance.
The most remarkable difference from the LNS is that the thicker epitaxial growth of Si (T Si ) is required than that of SiGe (T SiGe ) for the formation of the channels [ Fig. 3(a)] where the T Si and T SiGe determine the T ch and the T sp , respectively. After fins are patterned [ Fig. 3(b)], dummy poly gate [ Fig. 3 Fig. 3(d)] are formed sequentially. It should be noted that the metal gates and the S/D face each other with the gate dielectric and semicircle-shaped inner spacer in between after the metal gate formation process of Fig. 3(e). It means that the dielectric area (namely, multiplication of W ch and T sp ) between the metal gates and the S/D serves as an undesired S/D overlap capacitance (C ov ) which is V g -independent (constant capacitance). In this regard, the FNS can diminish the C ov effectively by reducing the W ch without the change of the W eff .

(c)] and S/D with inner spacers [
Additionally, in FNS, the increase of width can be simply implemented by modulating the fin height for the enhanced current as contrast to LNS where it is difficult to increase the width of the nanosheet because it affects multi-V th process margin by changing the space between nanosheets with different V th or between NMOS and PMOS [16].

A. BASIC ELECTRICAL CHARACTERISTICS
Effective current (I eff ) vs. off current (I off ) correlation plot are described in Fig. 4(a). The three different V th s are implemented by changing the work function to evaluate the current drivability and capacitance. Compared to LNS, FNS has the degraded I eff by 20% and 9% for n-MOSFET (NMOS) and p-MOSFET (PMOS), respectively (at fixed I off of 1nA/μm) although other main electrical parameters such as V th and subthreshold swing (SS) are not significantly different. For the NMOSs of LNS/ FNS, the V th s are 236/232 mV and the SSs are 69.9/69.7 mV/dec, respectively.
In terms of capacitances, the V th -C ov correlation plot [ Fig. 4(b)] shows that the C ov of FNS is decreased by 22% (NMOS) and 25% (PMOS), respectively as compared to LNS. Based on the similar reduction amount of the C ov for the entire V th regions (∼90 aF/μm), it can be noticed that the constant capacitance component of the C ov is reduced. By evaluating the difference of the I eff -I off and V th -C ov characteristics between LNS and FNS, it is expected that geometry-dependent parasitic capacitance and resistance components might affect the electrical characteristics significantly.

B. CAPACITANCE ANALYSIS
To analyze the C ov difference between LNS and FNS, it is necessary to define all the composition of effective capacitance (C eff ) including the C ov . One-stage inverter capacitance can be defined as the total C eff . Considering the operation of an inverter, the C eff is divided into the C in (capacitance from previous node), the C out (that from output node), and the fan-out (FO). capacitance (C fo ) [17] as shown in Fig. 5 and equation (1).
Here, the C in and C out are composed of gate capacitance (C gg ), gate-to-drain capacitance (C gd ), and drain to body capacitance (C db ) [18]. The capacitance for the n-type device (C nmos ) and that for the p-type (C pmos ) are separately considered. Since the inverter oscillates between 0 V and V dd , each capacitance component is also modulated between a depletion mode capacitance [C (dep.) ] and an inversion mode capacitance [C (inv.) ] depending on the inverter bias condition [19], [20], [21]. Thus, the C in and the C out can be expressed as below.
Furthermore, two representative capacitance components, equations (4) and (5), C gg(inv.) (V g = V dd , V d = 0 V) and C gg(dep.) (V g = 0 V, V d = 0 V), consist of the gate to S/D fringing capacitance through spacers (C of ), the gate to S/D fringing capacitance across the channel (C if ), the gate to S/D overlap capacitance (C do ), the gate-to-channel capacitance (C ox ), and the parasitic capacitance between the gate and S/D contact metal (C mol ) as depicted in Fig. 6(c). Here, note that the C ov is the half of the C gg(dep.) . Considering the signal oscillation of ring oscillator, the summation of all these capacitances becomes the C eff because the capacitances are connected in parallel at the node that located between two inverters.
It should be noted that the constant gate-to-S/D capacitance through inner spacers (C side ) is inevitably added to both C gg(dep.) and C gg(inv.) by the metal gate formation process of LNS and FNS, which degrades the device performance [22]. However, it is clearly observed that the FNS has the reduced C side [reduced shaded overlap area in Figs. 6(a) and (b)]. In order to investigate the effect of C side on C ov , each capacitance components are compared between FNS and LNS [Figs. 7(a) and (b)]. As a result, it is found that the C ov s of FNS are decreased by 89 (NMOS) and 90 (PMOS) aF/μm compared to LNS due to the reduction of the C side .

C. RESISTANCE ANALYSIS
Although FNS has the capacitance reduction, the degradation of the I eff is accompanied. To reveal the origin of the I eff degradation and to enhance the I dsat , its resistance components are rigorously analyzed. In the stacked GAA-MOSFETs, over-drive linear resistance (R odlin ) can be divided into channel resistance (R ch ), extension resistance (R ext ) [23]. Equivalent resistance circuits for LNS and FNS can be described as shown in Figs. 8(a) and (b) where the R ch and the R ext of each layer are connected in series. Thus, the R odlin can be expressed as following equation (6).
Importantly, Figs. 9(a) and (b) indicate the comparison of the R ext and the R ch between the LNS and FNS. The analysis on each resistance is performed using linear regression by applying the same over-drive voltage (V od ) which is 0.5 V for NMOS and -0.5 V for PMOS (from V th of the devices). As shown in Fig. 9(a), the R ch increased by 28 ·μm for NMOS and decreased by 37 · μm for PMOS in FNS compared to LNS. This R ch difference can be explained by that of mobility because FNS and LNS have the different channel orientations of (110)<110> and (100)<110>. In Fig. 9(b), R ext of the FNS is increased (NMOS 134 · μm, PMOS 140 ·μm) compared to the LNS by the due to the reduction of S/D contact area and the increase of S/D height. The current contributed by the bottom fin region is negligible for LNS and FNS since the region has the high doping concentration (namely, large resistance) by ground doping.

D. GATE DELAY AND DYNAMIC POWER ANALYSIS
To estimate the AC characteristics of the FNS, inverter performances are analyzed. Especially, τ delay (7) and P dyn (8), which are function of C eff , inverter effective resistance (R eff )   and frequency (f ), are analyzed because they are representative indexes for evaluating the AC performance of inverters.
For the accurate analysis of the device performance, V dd is swept from 0.2 to 1.1 V and the device is evaluated with reasonable criteria in the correlation graph between P dyn and frequency (namely, inverse of τ delay ). Fig. 10(a) demonstrates the P dyn comparison with respect to the frequency between LNS and FNS. It is clearly seen that FNS has 19% P dyn gain (9.4 μW) at the same frequency (187 GHz, FO1, V dd = 0.7 V). In other words, the 8% gain of frequency (15.3 GHz) at the same P dyn (50 μW, FO1, V dd = 0.7 V) is achievable, meaning that FNS is suitable for low power operations. This can be understood by noticing that the C eff of FNS is improved by 17% in all the V dd range [ Fig. 10(c)] although the inverter drive current (I drive ) becomes degraded with the V dd increasing compared to LNS [ Fig. 10(b)] due to the increase of the inverter resistance [ Fig. 10(d)]. That is, the reduction of the C eff overwhelms the I drvie degradation and thereby the performance improvements are obtained. In addition, note that the R eff and R ext of FNS can be diminished without sacrificing C eff gain by applying wrap-around-contact (WAC) [5].
Furthermore, the FO is added to consider inverter operations in complex circuits. It can be expected that the C eff is increased by the number of C fo because inverter FO is located between the input and output stages and the additional C fo component serves as the capacitance component of the output node with C gg(inv) and C gg(dep) when one point of inverter oscillation is captured as follows.
C fo = C gg_p(dep.) + C gg_n(inv.) (9) Fig. 11(a) shows that the C eff difference between the LNS and the FNS becomes larger with the increasing number of FO. Also, as depicted in the frequency vs. P dyn correlation with respect to the FO number [ Fig. 11(b)], the P dyn is decreased by 19% at the same frequency and the τ delay is reduced by 8% at the same P dyn even in the FO3 case. Thus, it is confirmed that the performance gain of FNS is still maintained despite of the addition of the FO, indicating the feasibility of FNS to the actual logic circuit.
In Table 2, the performance and electrical parameters of FNS are compared to those of LNS. It is clearly observed that FNS has the improved speed at same P dyn and, in other words, the reduced P dyn at same speed. Based on the comparisons, it is confirmed that the performance enhancement results from the capacitance reduction, and particularly the decrease in C side is noticeable in both NMOS and PMOS.

IV. CONCLUSION
In this paper, FNS have been proposed for low power logic device applications because FNS can have the improved electrical characteristics than LNS although the process flow is highly compatible with those of FinFETs and LNSs. Through the TCAD device and circuit simulations, the device performance of FNS is rigorously investigated. As a result, it is found that the P dyn at the same frequency (187 GHz) and  the τ delay at the same P dyn (50 μW) are reduced by 19% and 8% in the one-stage inverter, respectively. Even, the same amount of τ delay reduction is achievable in the inverter with FO3.
To verify the origin of the performance improvements, the analysis on the resistance and capacitance components of LNS and the FNS is performed. It is clearly revealed that the R ext is increased by the reduced S/D contact area and the extended floating fin height, and the C eff is diminished due to the reduction of the C side . Consequently, the τ delay and the P dyn are improved despite of the I eff degradation because the C eff reduction overwhelms the drivability degradation during the signal propagation through inverters.