A Tall Gate Stem GaN HEMT With Improved Power Density and Efficiency at Ka-Band

In this letter, AlGaN/GaN HEMTs with tall-gate-stem structures were realized to improve the power performance of Ka-band devices, and a film thinning process is adopted in the fabrication process to reduce the parasitic capacitance caused by the thick silicon nitride film. According to the S-parameter measurement results, devices owning a tall-gate-stem structure and undergoing the film thinning process have higher cut-off frequency (fT) and maximum oscillation frequency (fmax) values with lower extracted parasitic capacitance. For the load-pull measurement result, the AlGaN/GaN HEMT with a tall gate stem has improved output power density (Pout) and power added efficiency (PAE) at Ka-band. The device with the elevated stem shows a steady-state current density of 883 mA/mm and a maximum transconductance of 323 mS/mm at 20 V bias, and it achieves <inline-formula> <tex-math notation="LaTeX">${\mathrm{ f}}_{\mathrm{ T}}$ </tex-math></inline-formula> of 39.5 GHz, <inline-formula> <tex-math notation="LaTeX">${\mathrm{ f}}_{\max }$ </tex-math></inline-formula> of 112.9 GHz with the maximum PAE of 24.6% and the maximum <inline-formula> <tex-math notation="LaTeX">${\mathrm{ P}}_{\mathrm{ out}}$ </tex-math></inline-formula> of 6.6 W/mm at 38 GHz.

When operated at high frequency, device performances such as cut-off frequency (f T ), maximum oscillation frequency (f max ), output power density (P out ), and poweradded efficiency (PAE) suffer from parasitic effects. The parasitic capacitance is mainly contributed by the gate-tosource capacitance (C gs ) and the gate-to-drain capacitance (C gd ). To alleviate these effects, the tall-stem-gate structure is implemented in this study. Using simulations, it was found that reduction of C gs and C gd can be achieved by properly increasing the height of the gate stem [14]. The tall-stemgate structure increases the distance between the gate head and the channel, resulting in the reduction of the C gs and C gd due to the decrease of the head-to-channel capacitance.
The impact of height of gate stem on power performance has not been discussed in the literature; in this study, GaN HEMT devices with gate stem heights of 150 nm and 250 nm are fabricated and compared to investigate their difference in   power performance. Improved power gain, output power density, and efficiency of the device at Ka-band are observed in this study due to the adoption of the tall gate stem structure.

II. DEVICE DESIGN
As shown in Fig. 1, the -gate structure of the AlGaN/GaN HEMT used in this study generates the head-to-channel capacitance (C hc ) and the stem-to-channel capacitance (C sc ), which are parasitic capacitance contributing to C gs and C gd . According to [14], the simulated C gs and C gd values of the elevated T-gate device were reduced because raising the stem height alleviates C hc significantly with only a slight increase of C sc . Similar to the T-gate device, the -gate AlGaN/GaN HEMT with a higher head level will have a lower C gd value; and modifying the gate architecture at the drain side will also influence the value of C gs [15]. Therefore, for the contribution to C gs , if the reduction of C hc is more significant than the increase of C sc , C gs of the elevated -gate device is expected to be reduced as well.
Based on the concept, two types of devices were designed, one with a 150nm-stem-height gate and the other with a 250nm-stem-height gate. The structure and dimensions of -gate AlGaN/GaN HEMTs in this study are shown in Fig. 2. With a higher gate stem, the device would have lower C gs and C gd values with better RF power performance.
On the other hand, different heights of gate stems are determined by the thickness of the first deposited silicon nitride (SiN) film in the fabrication process. Therefore, to minimize the parasitic capacitance difference caused by different thicknesses of the first deposited SiN film, a  film thinning process is adopted during the process. The film thinning process is also expected to improve the gain compression of devices during the load-pull measurement through the dispersion control. For the deposition of a SiN film, the 2-step PECVD was adopted. For the first step of the deposition, low-power plasma was used to form the first 50 nm of the SiN film thickness for better quality; for the second step of the deposition, the relatively high-power plasma was then used to accelerate the deposition rate till the target thickness. The SiN film formed by the relatively high-power plasma tends to have more defects and it leads to more significant dispersion [16]. The film thinning process removes the part formed by the relatively high-power plasma of the SiN film, and thus is expected to improve the dispersion characteristic. Therefore, an experiment on the 150nm-gate-stem-height devices with and without film thinning process is conducted to investigate its influence on RF power performance.
Overall, as shown in Table 1, 3 types of devices were prepared. One with a 150nm-stem-height gate and has undergone the film thinning process is labeled as group A, another with a 250nm-stem-height gate and has undergone the film thinning process is labeled as group B, and the other with a 150nm-stem-height gate and has not undergone the film thinning process is labeled as group C.
To investigate the relationship between device RF characteristics and parasitic capacitance, a small-signal equivalent circuit model of an AlGaN/GaN HEMT with parasitic elements is provided in Fig. 3. Where C pgi , C pdi , C gdi stand for the inter-electrode and crossover capacitance between gate, source, and drain. Then, the cut-off frequency (f T ) and the maximum oscillation frequency (f max ) are introduced to explain the relationship between device RF characteristics and parasitic elements of the AlGaN/GaN HEMTs in this study. Equation (1) and (2) shows the general forms of f T and f max formulas: where R s is the source resistance, R d is the drain resistance, R g is the gate resistance, and g o is the output conductance [17], [18]. Based on the formulas, it can be observed that f T and f max have a negative correlation with parasitic capacitance C gs and C gd , which is roughly inversely proportional to C gs + C gd . Therefore, the reduction in C gs and C gd improves f T and f max significantly. Because the definition of f max is the frequency that Mason's unilateral gain (G U ) becomes unity, the reduction of parasitic capacitance not only improves the RF characteristics but also benefits the power gain characteristic.

III. DEVICE FABRICATION
From bottom to top, the AlGaN/GaN HEMTs on SiC were composed of the following epitaxial layers: GaN buffer layer, GaN channel layer, AlN spacer layer, and AlGaN barrier layer as shown in Fig. 4. The fabrication process for devices with film thinning can be divided into four main parts: Ohmic contact formation, isolation, gate formation, and metallization. For the Ohmic contact formation, the Ti/Al/Ni/Au Ohmic metal stack was deposited by the E-gun evaporator, followed by RTA at 835 • C in nitrogen ambient. Device isolation was performed using boron ion implantation. For the gate formation, the first SiN film was deposited using PECVD for device passivation, and its thickness is equal to the height of the gate stem. The first SiN film thickness of 150 nm and 250 nm were prepared for devices in group A and group B, respectively. Afterward, E-beam lithography was conducted twice to perform gate shift technology as shown in Fig. 5. The first E-beam lithography defined the region to be etched of the first SiN film, and the second E-beam lithography defined the area for gate metal deposition. The pattern of the second E-beam lithography was slightly shifted from the pattern of the first E-beam lithography, and the overlap equals the gate length, which is 100 nm. For the two-step E-beam lithography method, the as-deposited SiN film provides steady support for the tall stem structure, and the height of gate  stem can be accurately determined by the thickness control of the SiN film. After two steps of E-beam lithography, a gate metal stack of Ni/Au was deposited by the E-gun evaporator. Afterward, the device was covered with the second SiN film of 100 nm to protect the deposited gate metal and fill the etching vacancy left by the gate shift process. The overall SiN thickness of the 250nm-gate-stem-height device so far is 100 nm thicker than the 150nm-gate-stem-height device. A film thinning process, as shown in Fig. 6, was applied not only to minimize the parasitic capacitance difference caused by different first deposited SiN film thicknesses (150/250 nm) but also to improve the dispersion control for the devices in groups A and B. During the film thinning process, the deposited SiN film were directly etched by ICP-RIE, and the thickness was reduced to 50 nm. The deposition of second SiN film before film thinning is necessary; otherwise, the etching vacancy will lead to the collapse of the gate structure during directly etching. After the film thinning process, the devices in groups A and B were passivated by the third SiN film of 100 nm to protect the gate metal. That is, the devices in group C did not undergone the film thinning process and the deposition of the third SiN film. Finally, for the metallization, the via hole opening of the passivation film was performed by ICP-RIE and then thick Au metallization of 2 um was deposited.

IV. RESULTS AND DISCUSSION
The devices with different heights of gate stem (150/250 nm for group A/B) and devices with or without the film thinning process (group A and C) were fabricated and evaluated in this study. The evaluation of the device includes the DC characteristics, the S-parameters, and the RF power characteristics.

A. IMPACT OF SIN FILM THINNING ON ALGAN/GAN HEMTS
To investigate the impact of SiN film thinning on performance, devices with thinned (group A) and un-thinned (group C) first SiN film are compared. The overall thickness of SiN films for devices in groups A and C are 150 nm and 250 nm, respectively. The gate width of the device is 4×25 um and the height of the gate stem is 150 nm for each group.
The DC characteristics of the devices in group A and C are shown in Fig. 7 and Fig. 8. The IDVG measurements were conducted under 20V drain bias voltage (V DS ) as shown in Fig. 7 (a) and Fig. 8 (a). For the device in group A, the steady-state current density (I dss ) was 863 mA/mm and the maximum transconductance (g m,max ) was 317 mS/mm. For the device in group C, the I dss was 888 mA/mm and the g m,max was 322 mS/mm. The IDVD measurements were conducted under different gate bias voltages (V GS ) from 0 V to −5 V as shown in Fig. 7 (b) and Fig. 8 (b). Based on the measurement of DC characteristics, the SiN film thinning process does not cause obvious difference in DC performance.
The S-parameter measurement results of the devices in groups A and C with 4×25 um gate width are shown in Fig. 9 (a) and (b). The bias condition is V DS = 20V and V GS = −2.7V. The values of f T can be obtained from the measured |H21| gain results and the values of f max can be obtained from the measured MSG/MAG results. For the device in group A, f T was 32.7 GHz and f max was 92.9 GHz; for the device in group C, f T was 29.6 GHz and f max was 87. 6 GHz. Both f T and f max of the device in group A are higher than in group C. According to the results of S-parameter measurements, the values of the parasitic elements of the devices can be extracted referring to the approach proposed in [19]. The intrinsic elements C gs and C gd of devices in groups A and C are extracted under bias condition of V DS = 20V and V GS = −2.7V. The values of the extracted R g , C gs and C gd of the AlGaN/GaN HEMTs in this study are listed in Table 2. The device in group A has a C gs value of 78.2 fF and a C gd value of 12.1 fF, while the  device in group C has a C gs value of 82.3 fF and a C gd value of 13.7 fF. The film thinning process slightly reduces the parasitic capacitance of the AlGaN/GaN HEMTs. Since the film thinning process does not change the gate structure, the gate resistance of devices in groups A and C are similar. The extracted results are consistent with the formulas of f T and f max , which indicate that higher f T and f max values are due to lower parasitic capacitance. For the S-parameter result of devices in groups A and C, it can be concluded that the reduction of 100 nm in SiN film thickness causes the decrease in the parasitic capacitance, and therefore the RF performance is improved. This phenomenon is expected to be more significant on 250nm-gate-stem devices because the SiN thickness difference will be 200 nm between thinned and un-thinned devices.
The 38 GHz load-pull measurement results of devices in groups A and C with 4×25 um gate width are compared in Fig. 10. During the measurement, V GS was set at class A and V DS was biased at 28 V for each device. The impedances of both the source port and the load port were matched for the maximum output power density. The device in group A achieved the maximum output power density (P out,max ) of 4.7 W/mm, the maximum power-added efficiency (PAE max ) of 14.7%, and the linear gain of 5.8 dB; the device in group C achieved P out,max of 4.1 W/mm, PAE max of 10.2%, and the linear gain of 5.6 dB. Based on the load-pull measurement results, a more severe gain compression is found for the device in group C due to worse dispersion control. For device in group A, the film thinning process not only reduces the parasitic resistance, but also significantly improves the dispersion characteristic. Therefore, the SiN film thinning process is necessary to further improve the output power density and the power-added efficiency of the device; otherwise, the influence of dielectric thickness will be more significant on 250nm-gate-stem device.

B. ALGAN/GAN HEMTS WITH DIFFERENT HEIGHTS OF GATE STEM
To investigate the impact of height of gate stem, devices with gate stem height of 150 nm (group A) and 250 nm (group B) are compared. For each group, the gate width of device is 4×25 um and the thickness of first SiN film is thinned to 50 nm.
The DC characteristics of the devices in groups A and B are shown in Fig. 7 and Fig. 11. The IDVG measurements were conducted under V DS of 20 V as shown in Fig. 7 (a) and Fig. 11 (a). For the device in group A, the I dss was 863 mA/mm and the g m,max was 317 mS/mm. For the device in group B, the I dss was 883 mA/mm and the g m,max was 323 mS/mm. The IDVD measurements were conducted under different V GS from 0 V to −5 V as shown in Fig. 7 (b) and Fig. 11 (b). Based on the measurement of DC characteristics, different gate stem heights in this study have only a minor impact on the DC performances of the devices.  The S-parameter measurement results of the devices in groups A and B with 4×25 um gate width are shown in Fig. 9 (a)    a C gs value of 78.2 fF and a C gd value of 12.1 fF, while the device in group B has a C gs value of 59.7 fF and a C gd value of 8.7 fF. This proves that appropriately raising the gate head can efficiently improve the parasitic capacitance. Although the tall-gate-stem structure causes an increase in R g value, it is still worth applying the tall-gate-stem structure because the reduction in C gs and C gd is significant.
The 38 GHz load-pull measurement results of devices in group A and B with 4×25 um gate width are compared in Fig. 13. During the measurement, V GS was set at class A and V DS was biased at 28 V for each device as well. Also, the impedances of both the source port and the load port were matched for the maximum output power density. The device in group A achieved P out,max of 4.7 W/mm, PAE max of 14.7%, and the linear gain of 5.8 dB; the device in group B achieved P out,max of 6.6 W/mm, PAE max of 24.6%, and the linear gain of 8.0 dB. It can be observed that the tall-gate-stem structure significantly improves P out and PAE of the device at 38 GHz. Based on the load-pull measurement results and the extracted C gs and C gd values from the S-parameter results, it is shown that the tall-gate-stem AlGaN/GaN HEMT with reduced parasitic capacitance not only has better f T , f max , and power gain characteristic, but its output power and power-added efficiency are also enhanced. Table 3 compares the device performances in this study with the reported data of the Ka-band device in the literature. It shows that the RF power performance of AlGaN/GaN HEMT with a tall gate stem is comparable with the data of the reported Ka-band devices in the literature.

V. CONCLUSION
The increase of the head-to-channel distance for a GaN HEMT device was realized by increasing the gate stem height. This leads to lower head-to-channel capacitance (C hc ), which is included in the gate-to-source capacitance (C gs ) and the gate-to-drain capacitance (C gd ). According to the experimental results, raising the gate stem mitigates the parasitic capacitance and enhances the RF power performance of the device under high-frequency operation. Based on the S-parameter measurement results, the device with a gate stem of 250 nm can achieve f T of 39.5 GHz and f max of 112.9 GHz, which are higher than the device with a gate stem of 150 nm. For the AlGaN/GaN HEMT with gate stem height of 250 nm, the load-pull measurement results at 38 GHz showed the maximum output power density (P out,max ) of 6.6 W/mm, the maximum power-added efficiency (PAE max ) of 24.6%, and the linear gain of 8.0 dB. The power performance of the 250nm-gate-stem device is much better than the 150nm-gate-stem device. Again, the results indicate that raising the gate head can alleviate the parasitic effects of C gs and C gd . Furthermore, the device demonstrates the RF power performance comparable to the data reported in the literature.