Characterization of Oxide Trapping in SiC MOSFETs Under Positive Gate Bias

SiC MOSFETs devices with double-trench dominate the market due to their low on-resistance. However, studies on its temperature-dependent properties are not comprehensive. This work uses fast I-V and static I-V techniques to explore the location of electrons trapped in the device under moderate gate stress. Threshold voltage instability (<inline-formula> <tex-math notation="LaTeX">${\mathrm {V}}_{\mathrm {TH}}$ </tex-math></inline-formula> hysteresis and <inline-formula> <tex-math notation="LaTeX">$\Delta{\mathrm {V}}_{\mathrm {TH}}$ </tex-math></inline-formula>) and on-resistance degradation (<inline-formula> <tex-math notation="LaTeX">$\Delta{\mathrm {R}}_{\mathrm {ON}}$ </tex-math></inline-formula>) are used to characterize oxide trapping. Although the observation method is different, it can be found that the <inline-formula> <tex-math notation="LaTeX">${\mathrm {V}}_{\mathrm {TH}}$ </tex-math></inline-formula> instability and <inline-formula> <tex-math notation="LaTeX">${\mathrm {R}}_{\mathrm {ON}}$ </tex-math></inline-formula> degradation increase linearly with logarithmic time over a wide time range from <inline-formula> <tex-math notation="LaTeX">$100~\mu{\mathrm {s}}$ </tex-math></inline-formula> to 104 s, suggesting that the direct tunneling mechanism dominates the electrons trapping in the oxide near the SiO2/SiC interface. The interface trap density is <inline-formula> <tex-math notation="LaTeX">$3.8\times 10^{12}$ </tex-math></inline-formula> cm−2<inline-formula> <tex-math notation="LaTeX">$\cdot$ </tex-math></inline-formula>eV−1. In addition, a negative temperature dependence is shown in the test, and the fitting parameter <inline-formula> <tex-math notation="LaTeX">$\gamma$ </tex-math></inline-formula> from 0.16 to 0.18 indicated that these traps are concentrated in the oxide layer. These traps’ energy level at 0.68 eV below the conduction band was obtained in the recovery phase through the Arrhenius plot.


I. INTRODUCTION
Silicon carbide (SiC) is considered a promising wide bandgap semiconductor material to supersede silicon for developing high-efficiency, high-power, and hightemperature electron devices [1]. In particular, SiC metaloxide-semiconductor field-effect transistors (MOSFETs) are expected to meet the growing demand for electrical power generation, distribution, and switching due to their high breakdown voltage, low conduction, and low switching loss capabilities [2], [3].
Studying the positive gate stress of SiC MOSFETs is crucial to circuit design. For example, SiC MOSFET is usually used as the DC circuit breaker in protection circuits, gated on for prolonged periods. The changed threshold voltage (V TH ) under positive gate bias would cause a response time delay of the faulty system [4]. V TH instability is generally characterized by threshold voltage shifts ( V TH ) and hysteresis (V TH hysteresis). Besides the V TH , the on-state drain-to-source resistance (R DS(ON) or R ON ) is an important parameter related to power loss.
Semiconductor manufacturers enthusiastically research device structures and optimize gate oxide to restrict V TH instability and alleviate the R ON degradation [4], [5], [6], [7]. Several papers have investigated the negative or positive temperature dependence of V TH instability and R ON degradation in planar structures [3], [8], [9], [10], yet few studies on the trap level of devices [8]. Meanwhile, very little is known about trench gate structure [7], [11]. Although some articles have observed that trench gate structures had larger V TH  instability than planar gate structures under the same gate bias [12], [13].
Double trench devices dominate the market due to their low on-resistance. However, there is still a research gap on the temperature-dependent properties of the double trench structure. In this work, fast I-V and static I-V methods are used to investigate the V TH instability and R ON degradation over a wide time range from 100 µs to 10 4 s under moderate stress voltages. The trap level and their distribution are analyzed and calculated. These results may help manufacturers to optimize the gate oxidation process and improve the threshold voltage stability of the device.
The organization of this article is shown below. Section II investigates the V TH hysteresis and R ON degradation with different ramp speeds, gate stress voltages, and stress times using the fast I-V technique. Section III investigates the device degradation under gate stress at high temperatures over a broad time scale using the static I-V technique. Section IV is the conclusion part.

II. FAST I-V EXPERIMENTAL PROCEDURE AND TEST RESULTS
The SiC MOSFETs studied in this work came from leading commercial manufacturers. From its datasheet, the device has a breakdown voltage of 1200 V and R DS(ON) of 105 m , measured at V GS = 18 V and I D = 7.6 A at room temperature. The simplified structure of SiC MOSFETs with double trench is shown in Fig. 1. According to their technical report, the source trenches can effectively disperse the electric field at the bottom of the gate trench [14].
Fast I-V measurement relied on a paramet er analyzer system involving Agilent DSO-X 2024A digital oscilloscope, Agilent E3647 DC power supply, Rigol DG 2041A pulse generator, and computer control program [15], [16]. A schematic experiment setup for fast I-V measurement is shown in Fig. 2 (a). Changeable square pulses were applied to the gate terminal of the devices under test (DUTs). The load resistance (R L ) of 10 was carefully selected for limiting resonance and a low off-state current. During DUT's switching along the load line, the voltage waveforms of the gate (V GS(t) ) and drain (V DS(t) ) terminals were simultaneously recorded by the digital oscilloscope with the sampling rate of 50 M/s, as exhibited in Fig. 2

(b).
A small V DD of 0.5 V was selected to eliminate the current collapse and hot-electron effect [16]. It is worth mentioning that before the test, all terminals of the DUTs were grounded for 1 min to achieve a steady state by releasing the charges initially trapped in the MOS interface and oxide bulk. After the up-and-down ramping of each pulse, all terminals of the DUTs were grounded for 10 s to release the trapped charges to restore their initial state.
According to the schematic, time-dependent drain current I D(t) and drain-to-source resistance R DS(t) could be calculated using the following equations: The calculated up (solid line)-/down (dotted line) ramp I D -V GS and R DS -V GS curves are shown in Fig. 3 (a) and (b). In Fig. 3 (a), The V TH hysteresis (pink-dotted-line) is defined as the gate voltage difference read at the up/down ramps when the drain voltage (V DS(t) ) is 0.3 V [17]. In Fig. 3 (b), R ON is defined as the value of R DS when V GS = 6 V. R ON is defined as the ratio of R ON on the down-ramp to R ON on the up-ramp [17]. It can be seen from Fig. 4 (a) and (b) that the ramping time t r/f greatly influences the extraction of threshold voltage hysteresis and on-resistance. In Fig. 4 (c), the V GS and on-resistances extracted from the up-ramp shift to the left as the ramp speed becomes faster. Furthermore, it was observed that the V GS and on-resistances extracted by the down-ramp shift towards the right direction as the ramp speed become faster. Fig. 4 (d) shows that the V TH hysteresis and R ON increase with faster ramp speed. Moreover, a strong correlation between threshold voltage and on-resistance can be observed [7].
In the ramp region, the slow ramp speed will change the charge state close to the MOS interface. In this case,  the threshold voltage hysteresis is usually underestimated. In other words, faster ramp speed allows for more accurate observation of oxide traps near the interface because less charge state changes during the test [5], [6], [15], [18], and [19]. To achieve acceptable threshold voltage and transconductance, the gate oxide in SiC MOSFETs is usually thinner than its Si counterparts. However, it will lead to more severe degradation in the gate oxide because a higher electric field is applied [4], [18]. The gate stress voltage significantly influences the threshold voltage hysteresis and on-resistance, as shown in Fig. 5. In Fig. 5 (a), the V TH hysteresis is more pronounced at larger stress voltages than at smaller stress voltages. In Fig. 5 (b), the degeneration of on-resistance is in the same pattern. It is further confirmed in Fig. 5 (c), where extracted V GS and R ON did not change significantly during the up-ramps with increasing gate stress compared with the down-ramps. This is because more oxide defects are filled at higher voltages. Fig. 5 (d) shows the V TH hysteresis and R ON observed under different gate biases using the fast I-V method.
Depending on the results in Fig. 4 and 5, an up-/downramp speed of 100 µs and moderate gate stress of 7 V is selected for the following short-term stress test. In Fig. 6, V TH hysteresis, R ON , and maximum transconductance changes ( G m.max %) are monitored during the 1 s stress time. The G m.max is defined as the maximum value of I D / V GS . The degradation of transconductance G m.max % is defined as the percentage of the G m.max difference read at the up/down ramps divided by the G m.max value of up-ramps. Fig. 6 (a) and (b) show that V TH hysteresis and R ON degradation increase with stress time. In Fig. 6 (c), the extracted V GS , R ON , and G m,max did not change significantly on the up-ramps but changed greatly with increasing stress time on the down-ramps. Fig. 6 (d) shows that V TH hysteresis and R ON increase linearly with logarithmic time [2], [6], [20], [21], [22], and the transconductance degradation G m.max % also increases with stress time.
Based on the direct tunneling model of charge transfer into MOS devices, it is assumed that the traps are randomly distributed in the oxide. The total charge transferred into the oxide trap follows a logarithmic time dependence [18], [23], as described by the following equation: Where Q NIOT is the charge states in the near-interfacial oxide traps, N is oxide trap density, e is the electronic charge, β is the tunneling parameter, t 0 is the initial tunneling transition time, and ζ is the Euler's constant. It can be seen from the equation that trapped charge states increase linearly concerning the logarithm of stress time, which is consistent with the results shown in Fig. 6 (d).
It is suggested that the V TH hysteresis and R ON are attributed to the direct tunneling of channel electrons into as-grown oxide traps near the interface within 1 s bias time [6], [21]. As shown in Fig. 6 (c) and (d), the decrease in transconductance with stress time is more pronounced since transconductance is related to bulk traps in the oxide layer [24].
It can be predicted that more electrons would be trapped into the deeper oxide defects as stress time increases, causing more significant V TH hysteresis and R ON .

III. STATIC I-V EXPERIMENTAL PROCEDURE AND TEST RESULTS
In the previous section, we discussed the V TH hysteresis and R ON under short-term stress within 1 s; in this section, we will discuss the V TH and R ON under longterm stress within 10 4 s. The static I-V technique uses the measure-stress-measure (MSM) process, as illustrated in  Fig. 7 (a). The MSM procedure consists of four steps: initial stabilization, I-V reference curves measurement, multiple stress-sense measurement, and recovery-sense measurement. The schematic experiment setup for static I-V measurement is shown in Fig. 7 (b). Due to the pulse width limitation of the pulse generator in the fast I-V technique, the MPSMU module of Agilent B1505A is used to generate long-term pulse width for stress periods and recovery periods. The maximum current level is limited to 60 mA to protect the parameter analyzer.
At the beginning of the test, four virgin devices were initialized by all terminals being grounded for 1 min. Then the DUTs were heated to elevated temperatures for 1 hour to stabilize the device package temperature. After that, I-V reference curves at elevated environment temperatures were performed with V GS from 0 V to 7 V at V DS = 0.1 V by Agilent B1505A, as displayed in Fig. 7 (c). The V TH is defined as the gate voltage when the drain current reaches 0.1 mA. There are three temperature ranges from room temperature to 75 • C, to 100 • C, to 125 • C. Threshold voltage shifts are defined herein as the difference between the threshold voltage at different temperatures and the room temperature threshold voltage. It can be observed that in  Fig. 7 (c) and (e), the V TH shifts increase with higher temperatures consistently with the Arrhenius plot [25], [26]. In Fig. 7 (f), the interface traps per unit area, Nit increases from 1.31×10 11 to 2.41×10 11 with temperature from 25 • C to 125 • C, which is caused by the massive electron emission from the interface traps [25] and [27]. In Fig. 7 (d), the subthreshold swing decreases at high temperatures due to the alleviated Coulomb scattering effect [3], [26], [28], [29].
In the stress period, 7 V gate bias was applied to the DUTs for 10 4 s with other terminals grounded. The stress process was interrupted at the mean logarithmic time. Transfer characteristic curves were performed in the negative orientation (V GS from 7 V to 0 V at V DS = 0.1 V) to monitor the V TH and R ON [11]. The threshold voltage instability V TH is defined as the difference in V TH before and after stress.
In the recovery period, the gate voltage of 0 V was applied to the DUTs for 10 4 s with other terminals grounded to release electrons that had been trapped in the MOS interface and bulk defects.
To obtain the capture/emission time constant and describe the distribution of defects in the oxide layer, the V TH data in Fig. 8 (a) and (b) are fitted with the stretched exponential functions by using the following Equations (4) and (5), with the high R-square values between 0.95 to 0.99 (dash fitted line) [3], [26], [27].
V TH_hys(max) is related to the total trap density, V TH_hys(ts,0) is the non-recovered V TH_hys value, γ is related to the trap energy distribution, t s/r is stress/recovery time, and τ s /τ r is the time constant of stress/recovery periods. It can be found in Fig. 8 (a) that the time constant τ s increases from 10 3 to 10 5 as the temperature increases, leading to a negative activation energy of -0.52 eV, extracted in Fig. 10 (a). This may explain why the V TH decreases with the elevated temperature, the same phenomenon observed in [3], [11]. In other words, during the high-temperature  stress phase, the de-trapping is even more thermally activated than the trapping, caused by the emission time constant being shorter than their associated capture time [11].
In Fig. 8 (b), after removing the gate bias, we found the de-trapping in the recovery phase is accelerated by high temperatures, with the time constant τ r dropping from 10 6 s to 10 2 s with increased temperatures, leading to a trap level at 0.68 eV activation energy, extracted by Fig. 10 (b) in the Arrhenius plot.
Moreover, the trap energy distribution shows consistency in the stress and recovery phases, with the parameter γ from 0.16 to 0.18, as shown in Fig. 8 (a) and (b). This indicates that the trap energy distribution is concentrated in the gate oxide [3].
We also found that the V TH increases linearly with logarithmic time (solid fitted line), the same as in Fig. 6 (d). It is suggested that channel electrons are trapped in the oxide defects near the interface [30], [31], [32].
In Fig. 9, the interface trap density D it at room temperature is calculated by I-V subthreshold method [33], [34], [35]. The D it increases exponentially near the conduction band edge. E CS is the potential of the conduction band surface, and E t0 is the surface potential related to the trap level. At the E CS − E T0 = 0.1 eV, the D it is 3.8×10 12 cm −2 ·eV −1 .
The time evolution of R ON during the stress and recovery process are shown in Fig. 11 (a) and (b), respectively. It can be found that the R ON decreases with elevated temperature, which is consistent with the V TH tendency in Fig. 8 (a). The R ON also fits well with the stretched   39 40 exponential function, with the parameter γ from 0.02 to 0.05 during both the stress and recovery phases.

IV. CONCLUSION
This work uses fast I-V and static I-V techniques to explore the oxide trapping mechanism under positive gate bias in the double-trench SiC MOSFETs.
By monitoring V TH hysteresis and R ON within 1 s stress time using the fast I-V technique, it was found that these two parameters are affected by ramp speed, bias voltage, and stress time. By monitoring the V TH and R ON within 10 4 stress time using the static I-V technique, it was found that the V TH and R ON decreased with the elevated temperature due to the activated de-trapping effect. Moreover, during the 10 4 recovery time, the trap level at 0.68 eV below the conduction band is obtained, and these recoverable trap sites are concentrated in the oxide layer.
Although the observation method is different, it can be found that the instability of the threshold voltage and onresistance increases linearly with logarithmic time regardless of the long or short stress time, indicating that direct tunneling dominates the electrons trapping in oxide near the interface. The interface trap density is 3.8×10 12 cm −2 ·eV −1 .
Comparisons of D it and E a between the SiC MOSFETs with different structures are shown in Tables 1 and 2, respectively.