Optimization of Low-Voltage-Operating Conditions for MG-MOSFETs

Adaptive threshold-voltage controlling of thin-film multi-gate (MG) MOSFETs, using independent back-gate biasing, is applied for realizing latency and power optimization. The controlling-method validity for low-voltage operation is analyzed with the compact model HiSIM-MG, considering all internally induced charges specific for MG controlling. Current-drivability degradations, due to back-gate-charge contribution under positively-biased back-gate voltage and existence of an optimized operating condition, are confirmed. The optimized operating condition is shown to keep the back-gate charge under the weak inversion with a corresponding relatively small back-gate charge. It is also demonstrated, that an input-voltage optimization accompanies the back-gate-voltage optimization, sustaining the optimized low power loss with low input voltage. Circuit-performance improvement of 27% by about 30% reduction of substrate thickness, while keeping switching-power loss small, is also verified.


I. INTRODUCTION
Thin film multi-gate (MG) MOSFETs are widely acknowledged as an attractive alternative for low-voltage-circuit applications, due to an additional independently-controllable back-gate [1]- [3]. The Silicon on thin SOI layer (ETSOI) MOSFET has been widely studied with relatively thick Buried Oxide (BOX) [4]- [7], where the body is separated from the substrate by a BOX layer to reduce the effects of parasitic capacitances and undesired punchthrough currents [8]. This helps to achieve better switching performance, and thus the ETSOI structure has been widely applied for RF circuits. Together with the thin SOI layer, the thin BOX (SOTB) MOSFET [9]- [12] is one of the MG-MOSFET derivatives [13]. Bidirectional gate control improves the subthreshold characteristics significantly. It has been demonstrated, that the influence of the backgate control is an important factor for performance and power-loss optimization. Supply-voltage (V dd ) scaling is one of the most effective ways to reduce dynamic power loss, as it has a quadratic relationship with the switching loss [14]- [15]. However, scaling down the supply voltage weakens the front-gate control over the channel, especially for short-channel-length devices, due to the lateral-field dominance, produced by the source/drain junction depletion extension [16]- [18]. This degrades the subthreshold slope. Therefore, to significantly strengthen the vertical electric field dominance over lateral field, a contribution from the back-gate is essential, and this is what multi-gate structure offers. In an MG-MOSFET structure, both front-and back-gate-controlled currents constitute the overall drain current (I ds ). In the subthreshold condition, a weaker frontgate-controlled-current contribution is inadequate for fast switching operation. Positive back-gate biasing is essential to increase the back-gate-controlled current. However, the efficiencies of front-and back-gate-current control by V gs and V bg , respectively, are vastly different in nature, due to different oxide thicknesses (FOX and BOX) and presence of an additional substrate region underneath BOX. Although positive back-gate biasing increases the drain current, its efficiency varies over a wide range of values [19].
Our investigation focuses on V bg -control efficiency for back-gate-current generation and its impact on circuit performance. The near-or sub-threshold region is specifically analyzed, as it is highly attractive for the purpose of improving the energy efficiency. As a substitute for measurement data, 2D-device simulations [20] are used in the analysis. By applying the developed compact model HiSIM_MG [21], the key factors for optimizing circuit performance and device structure are clarified. It is demonstrated, that an independent control of the MG-MOSFET gates provides the necessary optimization freedom for simultaneously achieving the requirements of both low switching loss and sufficiently high switching speed.

II. MG-MOSFET FEATURES AND THEIR MODELING
The SOTB-MOSFET structure, applied in our investigation, is shown in Fig. 1a, where also the device parameters and their values are listed. Figure 1b depicts the I ds -V gs characteristics of 2D-device simulation for different back-gate voltages (V bg ). The extracted threshold voltage V th is plotted in Fig. 1c as a function of V bg . This extraction is done with the GMLE method, which has been verified to provide reliable results for advanced MOSFET generations [22]. It can be seen, that V th is reduced drastically for V bg > 0, which is used to realize low-power operation [23]. The main effect of a positive V bg is the additional formation of a back-gate charge Q b , as schematically depicted in Fig. 2a. The surface potentials φ s and φ b at front and back gate are compared in Fig. 2b as a function of V gs for different V bg values. The threshold condition occurs, when either of the potential values φ s and φ b reaches 2 B . It can be seen roughly, that the threshold condition is mainly determined by the back-gate potential φ b for V bg > 0 and by the front-gate potential φ s for V bg < 0.
We have developed the compact model HiSIM_MG, which is applicable for independent-gate control of MG-MOSFETs. The model can be utilized for common-gate control as well as for more advanced technologies such as those of SOTB-MOSFETs. Our main focus here is to analyze the Q b contribution of the SOTB-MOSFET generation in circuits. For this purpose, all possible induced charges within the device are considered explicitly, together with the deep current flow near the BOX side. The Poisson equation is used together with the Gauss law to derive the V gs dependency of the total charge as [24]- [27] where Q s , Q b , and Q bulk are the carrier charges at front gate, back gate and the opposite side of BOX, respectively, as depicted in Fig. 2a. Q dep describes the depletion charge within the channel. The Poisson equation is solved iteratively together with the boundary conditions at the different material junctions [28], [30]. Figure 1b reveals, that HiSIM_MG can realize a good fit to the 2D device simulation results for any bias conditions. For V bg ≤ 0, mostly φ s dominates over φ b (see Fig. 2b), which indicates that the inversion charge Q s at the front-gate side is giving the major contribution, while the influence of the back-gate-inversion charge Q b is significantly smaller. Fig. 3 depicts the charge distribution of Q s and Q b as a function of V bg . An operation condition with smaller V bg improves the subthreshold swing but reduces the gate overdrive (V gs − V th ), because V th increases as demonstrated in Fig. 1b.
For V bg > 0, on the contrary, φ b starts to increase as a function of V gs first and φ s follows, resulting in Q b domination over Q s for smaller V gs . Under such a condition, the MOSFET has degraded subthreshold slope, because higher V bg introduces a Q b -originated current flow deep inside the SOI layer. Here, Q b is not easily controlled by V gs but rather  by V bg through T box . The gate control is kept sufficiently high for a thin SOI-layer thickness, however, so that the subthreshold slope degradation is not so obvious in our studied case.

III. EFFICIENCY OF BACK-GATE CONTROL IN A CIRCUIT
With the use of HiSIM-MG, a CMOS-inverter circuit (see Fig. 4a) is investigated to analyze the switching-power loss with different V bg values for high (1V) and low (0.4V) V dd cases. Figure 5 shows the schematic explanation of the two different operation conditions with the simulated I ds − V gs characteristics, depicted in Fig. 1b. As demonstrated in this figure, the voltage range of both 0 ≤ V gs ≤ 1V and 0 ≤ V gs ≤ 0.4V becomes insufficient to ensure lower static-power loss at higher V bg . Thus, upper and lower limits of the gateinput pulse are scaled up and down by an input-voltage scaling V in , respectively, so that switching can complete while leakage currents are negligible, as shown in Fig. 4b. Figure 6 depicts the power loss as a function of V in at low V dd , separately for the switching-power loss (Fig. 6a) and  the static-power loss (Fig. 6b). Even though the switchingpower loss is only lightly dependent on V in , the static loss can be reduced drastically by adjusting V in for such a CMOS-inverter circuit.
The V in value is fixed to 0.6V hereafter to limit the static loss below 0.2µW, keeping an identical value for any bias conditions of V bg . Figure 7 compares the simulated switching performance for the two V dd conditions with various V bg values. As can be seen in Fig. 7a, higher-voltage operation of V dd = 1V, doesn't show any significant delay change for the inverter-output-voltage transition even at higher V bg , which is explainable by the fact, that higher V dd drives the MOSFET to operate far beyond the threshold condition, eliminating the V bg dependence of φ s , i.e., indicating a strong-inversion attainment. Rather, the V dd = 1V case is compromised by a substantial switching-power loss, being mostly due to the current increase, caused by the effective V gs increase by V in (see also Fig. 5). Namely, efficiently controlled φ s (and hence Q s ) improves the transition delay significantly.
For low-voltage operation (V dd = 0.4V), the outputvoltage transition happens in the sub-threshold region, which

FIGURE 6. (a) The switching-power loss in CMOS-inverter remains weakly coupled with input-pulse scaling (increasing V in ), as it doesn't influence the transition region apart from a slight slope deviation. (b) On the other hand, Static power loss reduces significantly for higher V in values. For V bg > 1V, without V in scaling, static power loss is relatively high and comparable to the switching-power loss.
provides more efficient V gs control along with stronger V bg dependence. At V bg = 0, the contribution of the surface charge Q s still dominates during the transition. Therefore, relatively large V gs is required, as reflected by the higher delay value in Fig. 7b. On the contrary, Q b starts to control the transition as V bg increases, and the transition delay becomes smaller. Therefore, ample opportunities are available for 0V < V bg ≤ 2.0V to achieve optimization with respect to V bg .
As discussed in the previous section, 0V < V bg ≤ 1.0V limits the generation of Q b (see Fig. 3), resulting in only small influence on the switching performance. Figure 8 illustrates the extracted results for delay time (τ d ) and averaged power loss (P switching loss ), using the simulation results shown Fig. 7. For the low-V dd case, it is evident that 1V < V bg < 1.5V is the optimum window, where delay-time (τ d ) reduction is possible while power-loss increase is kept small. Our investigation reveals that V bg of 1.2V provides the lowest power loss with simultaneously short τ d .
The results shown in Figs. 7 and 8 are those at fixed V in of 0.6V. However, it is essential for low V th devices, especially with negative V th , to operate additionally with scaled input pulses for realizing an appropriate switching performance. Since the switching loss is not much dependent on V in , V in is optimized only for the static loss. Figure 9a depicts the minimum V in values, extracted from the result  shown in Fig. 6, as a function of V bg together with the boundary condition of V gs + V in > V th . This V in,min is considered as the optimized value in accordance with V bg , demonstrating that such an optimization can be done successfully as depicted in Fig. 9b. It can be seen, that the simultaneous optimization of V in sustains the power loss of the higher input voltage. As can be seen in Fig. 3, both Q s and Q b are contributing for the formation of the threshold condition at 0V < V bg ≤ 1.5V. However, Q b alone   starts to contribute to the switching at V bg = 1.2V. Table 1 summarizes the scope of MG-structure back-gate biasing for high and low V dd cases.

IV. STRUCTURAL OPTIMIZATION FOR LOW POWER LOSS
For further improvement of the power loss, the validity of a structural optimization is investigated. To reduce the switching loss, V gs controllability must be improved. At the same time the Q b contribution must be increased to enable the low voltage application. To fulfil these contradicting requirements, T BOX is reduced together with T SOI . The modifications are summarized in Table 2, where the rest of the overall device size is kept the same. I ds − V gs characteristics for the optimized structure are depicted in Fig. 10 and show good agreement with 2D-simulation results, using identical model parameters as for the original structure (see Fig. 1b), except for the device-structure parameters. This verifies the accuracy of the developed model. Figure 11 compares the results for the 2 device structures. Down-scaling of the T SOI layer allows Q b to be decreased due to increased V gs control. Contradictorily, T BOX scaling allows Q b to be increased. At lower V bg (0V < V bg ≤ 1.2V), the T SOI -scaling contribution dominates over that of T BOX due to the relatively small Q b (see Fig. 3), whereas for higher V bg the reverse holds true because Q b becomes more important. The magnitude of Q b is strongly dependent on V bg and T SOI . As observed in Fig. 11a, I ds decreases for the scaled structure with higher V th when 0V < V bg ≤ 1.2V. Beyond that, I ds increases with lower V th . Fig. 12 summarizes the V th values as a function of V bg . The reduction of V th as a function of V bg is quite drastic for the scaled structure. Hence, in regards of switching-loss improvements, 0V < V bg ≤ 1V is a comfortable region for circuit operation with scaled devices, without sacrificing a small power loss. Figure 11b demonstrates, that a switching-loss reduction of 27% can be achieved with the studied structure scaling at constant V bg = 1V, which would not be possible for V bg = 0V.

V. CONCLUSION
The SOI-MOSFET with thin SOI and BOX thicknesses was investigated with HiSIM_MG, to verify the back-gatevoltage V bg contribution for low power operation. It was found, that the relative electrostatic controllability of carriers within the SOI layer by front gate and back gate varies  depending on the operating region when increasing V bg . It is further shown, that the back-gate charge Q b increases as V bg increases, which results in a switching-power-loss increase mostly due to the slow transition in a CMOS inverter. It is shown that the input-voltage scaling is additionally efficient to achieve the desired low-power operation. A specific range of V bg (0V < V bg ≤ 1.2V for the studied case), where both performance and power loss are optimal, is validated to be suitable for low-voltage operation. This refers to the condition, where Q b is still kept under the weak-inversion condition. Within this V bg -bias range, multi-stage cascaded circuits can be operated without V in scaling and with minimal switching-power loss. Structural device optimization in high-density circuits is found to yield 27% lower switching loss for about 30% reduced substrate thicknesses. It is also demonstrated, that the MG-MOSFET optimization can be successfully performed by applying the compact model HiSIM_MG.