Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 um from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full self-heating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.


I. I
Quantum computers have the potential to solve certain computational problems that would otherwise take a prohibitive long time to complete using classical computers. For proper operation, the quantum bits (qubits) -the basic unit of information in quantum computers-need to be cooled down to deep-cryogenic temperatures, around a few Kelvin in some cases [1] but typically below 100 mK [2]. Since state-of-the-art quantum computers comprise only a handful of qubits, each qubit can be individually wired to equipment placed at room temperature (RT) [3]. However, to be of any practical use, future quantum computers require thousands to even millions of physical qubits, making today's approach unworkable due to the need for thousands of cables going from the cryogenic qubits to the RT equipment. The problems associated with scalability, manufacturability and reliability of these systems could be solved by placing integrated control electronics in close vicinity to the qubits, thus requiring electronic circuits operating at cryogenic temperatures. Such electronics are typically operated at liquid helium (LHe, 4.2 K) temperature, as commonly-adopted dilution refrigerators can offer significant cooling power (≈ 1 W) [4] only at those temperatures. The technology of choice for the cryogenic controller is nanometer CMOS, for its high speed, maturity, integration density and its potential to operate down to 30 mK [5], [6], all required for handling a large number of qubits. It has been shown that core device parameters, such as  Fig. 1. Thermal conductivity of silicon over temperature, replotted from [11]. threshold voltage, mobility, subthreshold slope, mismatch and leakage, can shift significantly from their RT values at low ambient temperatures ( ) [5], [7]- [10]. The incorporation of device temperature in compact models extended to the cryogenic environment is thus paramount to guarantee reliable circuit simulations and hence, robust circuit operation under these conditions. However, self-heating (SH) can raise the device temperature ( ℎ ) significantly above . This effect is amplified at cryogenic temperatures, as thermal properties of silicon, such as thermal conductivity ( ℎ ), vary almost over 1.5 orders of magnitude in the temperature range from RT down to 4.2 K, as shown in Fig. 1. For instance, a recent cryo-CMOS microwave driver for spin qubits operating at = 3 K was subjected to SH exceeding 10 K for a dissipated power above 400 mW [12]. SH does not only impact the characteristics of the device itself, it can also propagate through the surrounding silicon forming thermal feedback loops with neighboring devices [13]. While this can be already critical in electronic cryogenic circuits, it will become crucial in future system-on-chip (SoC), integrating both electronics and qubits, which are extremely sensitive to any thermal crosstalk [1]. SH at RT has received much attention in literature, specifically focused on silicon-on-insulator (SOI) technologies as the buried oxide (BOX) poses a thermal impedance 2 orders of magnitude higher compared to that of bulk silicon at this temperature [11], [14]. Far less attention was devoted to studies on SH at cryogenic temperatures. Early work dates back to the beginning 1970s [15] and has been extended more recently by investigations on bulk MOSFETs [13], [15]- [18], resistors [19], [20] and SOI [21], [22]. SH was investigated both by measurements of the device temperature itself [20]- [22] and by placing temperature sensors in the vicinity of on-chip heaters [13], [19], [20], [23]- [25]. All these works show that SH is exacerbated at cryogenic temperatures and that the effect is highly dependent on device geometry (size, aspect ratio) and power density. This variability is clearly observed in recent cryo-CMOS integrated circuits for qubit interfacing, as SH ranged from 1 to 3 K in a 40-nm bulk-CMOS high-speed ADC [26] to more than 10 K in a 22-nm FinFET microwave driver [12]. As device geometry and power density differ considerably between advanced bulk CMOS nodes and the previously studied mature technologies, it is necessary from a modeling perspective to characterize SH on devices better resembling those employed in practical cryo-CMOS designs [26]- [29], both in geometry and power density. Understanding the impact of SH is especially crucial for the cryo-CMOS low-noise amplifiers (LNA) necessary for the detection of the weak signals from quantum processors, as an increase of the device temperature of only a few Kelvin can strongly affect the noise performance, e.g., in a thermal-noiselimited amplifier in which the noise is directly proportional to the device temperature. This paper bridges this gap by characterizing and modeling the effects of SH on the device itself and on the surrounding silicon, using a typical NMOS device. It is found that SH can have a severe impact on both the device operating temperature and the temperature of the surrounding silicon at deep-cryogenic temperatures, and, that the former effect can be be successfully predicted using a simple modeling approach. This paper is structured as follows: Section II describes the test chip, measurement setup and the device calibration. Section III presents the measurement results, which are discussed and modeled in Section IV. Finally, conclusions are drawn in Section V.

II. T S M S
A test chip was taped-out, specifically designed for the characterization of SH at deep-cryogenic temperatures. The chip was manufactured in the TSMC 40-nm bulk-CMOS process. Fig. 2 and Fig. 3e show a simplified overview of the test structures and a die micrograph, respectively. Three NMOS devices are employed as heaters (H1, H2 and H3), formed by a 5 fingered device with fingers measuring / = 12 µm/40 nm each, individually selectable (separated gates and drains) and able to dissipate ≈ 7 mW of power. The gates of the two MOSFETs separating H1 and H3 from H2 are connected to V SS in order to electrically isolate the heaters from each other (Fig. 2 top). The center heater (H2) has additional connections available, enabling the measurement of the gate resistance, further discussed in Section II-A. The choice for NMOS over a PMOS device was motivated by its higher current driving capability (and thus power), as no significant thermal differences are expected between both types.  In addition to the MOSFETs, a linear array comprising 52 diodes is placed perpendicular to the channel, along a line through the center of the heaters (Fig. 2 top). These diodes act as temperature sensors, enabling the detection of the spatial thermal profile in the heaters' vicinity, further discussed in Section II-B.

A. Gate Test Structure
To enable ℎ characterization through a range of , gate thermometry is employed, in which the calibrated temperature dependence of the gate resistance ( , see Section II-D) is used as a temperature sensor [22], [30]. Kelvin connections to both top ( , ) and bottom ( , ) side of the H2 gate are therefore available to mitigate the impact of temperature dependence of back-end metals and parasitics on the resistance measurement (see Fig. 2).
The assumption was made that the gate and the channel are tightly thermally coupled, since only a thin (< 3 nm) insulating layer separates them: = ℎ .

B. Diode Test Structures
For the measurement of the thermal profile around the heaters, the substrate temperature is sensed by measuring the  calibrated thermal dependency of the voltage drop ( ) across P + /NWELL silicon diodes operated at a constant current 0 . A graphical representation of this structure can be seen in Fig. 2, comprising pad-accessible diodes and a multiplexed diode array. Pad-accessible diodes: two diodes (D1 and D2 in Fig. 2) are placed in close vicinity to the heaters (one on each side), with connections directly available via bond pads, to measure the substrate temperature at small distances from the heaters with high spatial resolution (300 nm). Different combinations of heaters (H1/H2/H3) and diodes (D1/D2) allow for a total set of 6 distances: = {1, 1.3, 1.6, 2, 2.3, 2.6} µm. Because of the direct connection to the pads, these diodes have been used as benchmark to verify the correct operation of the pass gates in the multiplexed diode array. Multiplexed diode array: a multiplexed array comprising 50 diodes to characterize the substrate temperature over larger distances, up to 30 µm from the heaters, enables automatic characterization. Thick-oxide pass gates were employed to allow the diode potential to rise above the nominal supply voltage (1.1 V), required as | 0 increases with decreasing temperature. An array was placed on both sides of the heaters. The 'dense' array ( Fig. 2 top right) comprises diodes placed at the minimum allowed distance, resulting in a spatial resolution of 0.8 µm and is used for the actual measurements. The 'sparse' array ( Fig. 2 top left) is a copy of the 'dense' array with every other device removed, resulting in less contact/metal density compared to the latter array. By comparing the results from the two arrays, it can be verified if the metal/contact density significantly impacts the thermal profile due to heat-leakage via the biasing metal lines.

C. Measurement Setup
A photographic overview of the measurement setup can be seen in Fig. 3. The dies were glued and wire-bonded to ceramic DIP packages, which were fitted in a socket on a PCB  mounted at the end of a dipstick (Fig. 3c). The PCB contains relays, enabling different configurations to be switched in and out during characterization. A Cernox type Resistance Temperature Detector (RTD) clamped to the package was used to measure .
Measurements at ≥ RT were carried out by inserting the end of the dipstick into a Vötsch VTM7004 climate chamber (Fig. 3b). The PCB inside the climate chamber was enclosed by a metal box to improve thermal stability, thus reducing temperature drift/gradients over time (Fig. 3d). The dipstick was inserted into a dewar containing LHe for the cryogenic measurements (Fig. 3a). The height of the sample above the LHe level modulates . Electrical characterization was carried out by 3 Keithley 2636B SMUs.

D. Calibration
The temperature characteristics of both the gate resistor and the silicon diodes need to be calibrated before they can serve as temperature sensors. During calibration, the parameters of interest ( and | 0 ) as a function of are characterized while is slowly varied with all heaters disabled. For ≥ RT, the climate chamber is used to generate a slowly varying : after warming up to ≈ 350 K, the climate chamber is switched off and allowed to (slowly) cool down while calibration takes place. Cryogenic calibration was carried out by manually lowering the dipstick into the dewar, cooling down the sample. Diode Calibration: for the 2 pad-accessible diodes, thecurves are measured as a function of . Deviation from ideal exponential behavior at cryogenic temperatures can be observed in Fig. 4. From these curves, as a function of is subsequently extracted by a horizontal cut along the line = 0 as indicated in the figure. As recording the fullcharacteristics for all 50 diodes in the array would take a prohibitive amount of time, is directly measured by forcing = 0 for these devices. Since there is some variability present among different diodes, all diodes need to be calibrated individually, see Fig. 5. An example of a diode calibration curve and the resulting temperature sensitivity can be observed in Fig. 6 top and bottom, respectively. The de-facto standard value (for commercial diode temperature sensors) of 0 = 10 µA was used for ≥ RT. To increase the sensitivity at deep-cryogenic temperatures, the current bias was reduced to 0 = 1 µA for < 300 K. The maximum temperature drift ( ) during a single -characterization was 0.6 K ( ≥ RT) and 1 K ( < RT). Gate Calibration: is measured by setting = 0 V and simultaneously sweeping from 0 to 50 mV, see Fig. 2, while recording the current through the gate ( ). Note that was left open to avoid any current and consequent heating in the device.
is extracted from the slope of a first-order fit of the -characteristic. The full gate calibration curve can be observed in Fig. 6 top. The maximum during a single characterization was 0.25 K ( ≥ RT) and 0.4 K ( < RT). The gap between 220 K and 300 K results from limitations in the minimum and maximum attainable temperature of the climate chamber and LHe dewar, respectively.

III. E R
This section presents the measurement results, focusing on the experimental methods and discussing data validity. Indepth analysis and discussion of the reported data is given in Section IV.

A. Gate-resistance Measurements
In the first step of the ℎ characterization, the sample is brought to the target by placing it at a certain height above the LHe level, or for RT measurements, by keeping it inside the (switched-off) climate chamber. When stays within ± 0.2 K of the set point, thermalization is assumed and different power levels are dissipated in the center heater ( 2 ) by stepping in a staircase pattern: = {0, 0.05, 0.1, ..., 1.1} V, while and are both set to 1.1 V. Following each step in , a 10 s delay was added to allow the structure to reach thermal equilibrium.
is subsequently swept from 1.1 to 1.15 V, while both and are recorded. Finally, the routine described above is repeated for multiple . is extracted from the -data as per the calibration routine described in Section II-D. The ℎ is inferred from these extracted values by local Taylor-expansion of the calibration curve (Fig. 6 top) around that operating point. As one side of the gate ( ) experiences a voltage change of 50 mV during measurement, increases slightly. The dissipated power is therefore calculated using the mean , 2 = ·¯, resulting in a maximum error of 2.5 % in power.
The absolute ℎ as a function of 2 for different is plotted in Fig. 7. The channel self-heating, Δ ℎ , is derived from these data by subtracting the extracted temperature at 2 = 0 for each from the corresponding curve, as shown in Fig. 8. As the temperature sensitivity of drops to very low values for ℎ < 11K, the RTD temperature reading was used for compensation instead of ℎ | 2 =0 for these curves. In order to protect against sudden temperature changes in the helium vapour (caused by varying pressure in the building's helium recovery system), the readings of the RTD are monitored: measurements are discarded when exceeds ± 0.5 K during a gate measurement at a single set point. In addition, these readings are also cross-checked with the extracted ℎ | 2 =0 as an additional safeguard.

B. Diode Measurements
The diode characterization is very similar to that of the gate (Section III-A); however, apart from H2, in this case, H1 and H3 can additionally be used as heaters. The characterization and analysis of the diode measurements can again be split into two groups: Pad-accessible diodes: , power dissipation and thermalization are handled as per the gate measurements. For each set point, is swept while and are recorded. These data are collected for all 6 combinations of H1, H2 or H3 with D1 or D2 over all targets. From thedata, | = 0 is extracted in the same manner as during diode calibration and the diode temperature ( ) is inferred with the use of the individual diode calibration curves (Fig. 6 top). The absolute for = RT and 4.2 K as a function of the enabled heater and the heater power can be seen in Fig. 9. Finally, the substrate heating ( Fig. 10) is calculated by compensating each absolute temperature curve in Fig. 9 with the corresponding temperature extracted at = 0, identical to the procedure followed in the channel SH analysis, while for < 10 K the temperature reading of the RTD was used. Multiplexed diode array: the measurement and analysis of the diode array follow the same routine as the pad-accessible diodes described above; however, due to the large number of devices (50), resulting in an increased measurement time, some adaptions were implemented to mitigate long-term : since sub-µm resolution is not required, only H2 was enabled; of each diode is directly measured by forcing = 0 and the number of set points was reduced to the set = {0, 0.1, 0.2, ..., 1.1} V. With these measures in place, characterization of the full array still consumes a considerable amount of time, therefore needs to be taken into account.  Long-term temperature drift is only present for samples in helium vapour, caused by time-varying pressure in the building's helium recovery system. To further minimize impact, each diode in an array is fully characterized over all set points (power levels), before switching to adjacent devices. During characterization of a single diode, is assumed to be small (comparable to that of the pad-accessible diodes) as the characterization time is relatively short: ≈ 115 s. However, there is still a longterm present between diode measurements, since a full array characterization takes ≈ 97 min. Therefore, the same compensation employed in the channel and pad-accessible diode characterization is applied here, which in this case, additionally auto-zeros the drift component between individual diode measurements. The long-term drift is assumed to be small enough to maintain , however, large enough to distort the SH measurement, the effect of which is dependent on the height above the LHe. During the full array characterization, the RTD readings are therefore used to guard against too large short-and long-term . The allowed short-term drift (during single-diode measurements) is as per the pad-accessible diode characterization, while the long-term drift must stay within ±0.5 K of the target for the data not to be discarded. Extracted absolute substrate temperatures as a function of distance for 2 = 0 and 2 = 6.3 mW measured at = RT are plotted in Fig. 11. Substrate heating as a function of distance at 2 = 6 mW measured at different can be observed in Fig. 12. The corresponding measured temperatures of the pad-accessible diodes and the channel have been added to the figure. The temperature profiles associated with different heater powers at a fixed = 160 K are plotted in Fig. 13, exemplifying the effect of on a single diode measurement.

IV. S -H : D , M T -A A. Diode-Based Temperature Sensing
Deviation from exponential behavior in cryogenically operated diodes shown in Fig. 4, are compatible with previous observations in literature [31], [32]. The sharp increase for < 50 K can be attributed to carrier freeze-out [32]- [34], also present in diodes specifically designed for cryogenic temperature sensing [35]. Consistently and significantly lower | 0 = were found for diodes in the 'sparse' array compared to the 'dense' array as indicated in Fig. 5. Most likely these differences can be ascribed to a combination of two effects: 1) diodes in the 'dense' array lie in a single continuous NWELL, while each 'sparse' diode sits in its own well. This causes differences in doping densities, and subsequent electrical characteristics, through the Well Proximity Effect (WPE) [36]. 2) the different Shallow Trench Isolation (STI) widths between diodes in the two arrays cause different mechanical stress to be present, altering the carrier transport parameters through the piezo-junction effect [37].
The calibration curves of and in Fig. 6 show a near-constant temperature sensitivity of −1.2 mV/K and 0.18 %/K for > 50 K, respectively. Freeze-out causes a large increase in sensitivity below this temperature, however, sensitivity drops to a very low value for < 10 K, compatible with measurements in [34]. 0 was reduced to 1 µA during cryogenic measurements to mitigate the latter effect [31], the value being a trade-off between improved sensitivity and increased impact of array leakage at deepcryogenic temperatures [38]. The temperature sensitivity of decreases to a value close to zero for < 11 K, inline with metal-like behavior [39]. For > 50 K, carrier transport is limited by phonon scattering, exhibiting a positive temperature coefficient (PTC), while below this temperature transport becomes increasingly limited by impurity scattering, which being temperature independent, prevents further resistance decrease. Due to the diminishing temperature sensitivity of both the diodes and gate resistance, the reading of and have been excluded for temperatures below 10 K and 11 K, respectively. However, due to the rapid temperature increase to values above 10 K already at low for = 4.2 K, this results in the loss of only a small part of the data (see Fig. 7 and 9). SH due to biasing of the temperature sensors is insignificant for the range of interest ( > 1 mW), as it has been simulated in COMSOL to be below 8 µW for the diodes, resulting in Δ < 20 mK; and below 1 µW for the gate resistor, resulting in Δ < 10 mK, respectively.

B. Channel Temperature Sensing
From the ℎ measurements in Fig. 7, an agreement between the RTD temperature reading and extracted ℎ | 2 =0 was found, indicating the correct operation of the setup through the full temperature range. Larger SH at equal 2 can be observed for lower temperatures in Fig. 8: Δ ℎ ≈ 14 K (RT) vs Δ ℎ ≈ 52 K (4.2 K) at 2 = 6 mW. For < 100 K, Δ ℎ is highly non-linear with respect to dissipated power, resulting in large SH for low 2 in this temperature range, also observed by [24] and [18]. As shown in the inset of Fig. 8, the SH behavior from RT down to 4.2 K for a given 2 shows a decrease down to 125 K, below which its effect starts to increase again, exhibiting a dramatic increase below = 75 K. This behavior hints to a temperature-dependent ℎ , with a minimum at ≈ 100 K, also shown in other works [20], [24]. Previously reported values of the minimum lie between 77 K and 250 K and have been attributed to the impact of parasitic ℎ (package, glue, etc.) dominating at these low temperatures in bulk CMOS. The crowding of ℎ between 40 K and 60 K for deep-cryogenic temperatures, visible in Fig. 7 for heating power above 1 mW, is a direct consequence of this ℎ behavior: below the ℎ minimum, ℎ has a negative temperature coefficient (NTC), which impedes SH more and more as ℎ approaches the minimum. The implications of this observed effect are further discussed in Section IV-E. Comparing the SH magnitude extracted in this work with literature, much higher SH was found in SOI technology at comparable power densities [22]. As the main ℎ in such technology is determined by SiO 2 , which exceeds that of Si by ≈ 2 orders of magnitude, a large difference in SH is expected. Regarding bulk technology, in which no BOX exists, the geometry and area of MOSFET devices significantly impact SH. Far lower SH was observed in a large square heater in bulk technology [20], which has significantly more enclosing area and hence a much lower ℎ to the surrounding silicon compared to the wide/short devices measured in this work. Also, the power density is orders of magnitude less compared to that in this work. The values published on a bulk device with an aspect ratio better resembling the structures characterized in this work, but with much larger and , show a slightly smaller SH effect. The structure in question had ≈ 100× larger area [13] and considerably lower power densities. The preliminary work done by [18] shows values that compare very well with the measurements presented here, although no geometrical details are given. These results stress the importance of geometry on SH, which is why in this work a transistor geometry comparable to the ones employed in practical cryo-CMOS circuits was chosen.

C. Spatial Thermal Measurements
Observations in line with the previous two sections can be made for the pad-accessible diodes. Both diodes show a smaller Δ compared to the Δ ℎ at identical conditions, as the effect of heating falls off rapidly with a 1/ -law (with the distance to the heater and a factor between 1 and 2): at = 4.2 K, 30 K less Δ was measured 1 µm from the heater compared to Δ ℎ itself, see Fig. 9 and 10. Again, larger Δ at cryogenic temperatures compared to RT was observed: Δ ≈ 3.5 K (RT) vs Δ ≈ 21 K (4.2 K) at = 6 mW, measured at 1 µm from the heater. All 6 diode/heater combinations are distinguishable at both RT and 4.2 K in Fig. 9, with 2 > 1 , as D2 is closer to the heater than D1. The Δ as a function of the enabled heater is flipped between D1 and D2, reflecting the mirror symmetry of the structure (see Fig. 2 top). In Fig. 10, a similar behavior as in the ℎ measurements can be observed in the pad-accessible diodes below 30 K. The inset clearly shows the same behavior: a decreasing Δ with decreasing with a minimum at ≈ 100 K, which compares well with the channel measurement. Additional cryogenic effects were observed in the heaters, see Fig. 9. At = 4.2 K, the power in H1-H3 increases by 17 % to 20 % at equal bias conditions compared to RT, attributed to the improved mobility, resulting in an increased and . At equal , H2 was able to dissipate consistently more power compared to H1 and H3. H2 is effectively shielded from STI stress by adjacent devices (H1 and H3), which alters carrier transport parameters (and thus and ) through the piezoresistive effect [37]. Another interesting observation on the SH structure is the heat propagation from the heaters to the 'dense' and 'sparse' diode arrays. As seen in Fig. 11, there is good agreement between the in both arrays, indicating no significant effects of metal/STI density on the thermal transport for these measurements, as was described in Section II-B. The readings at 2 = 0 correlate well with the RTD readings and an agreement within ±0.25 K between both 'dense' and 'sparse' diodes was found at both low and high 2 ; the latter indicates a stable and a successful calibration. The temperature mismatch between the two arrays is mainly due to the large time span between individual measurements, as each array is fully characterized before switching to the other. Compatibility of the array data with both channel and pad-accessible diode measurements can be seen, the shape corresponding to simulations shown by [20]. The substrate Δ falls off with the distance from the heater for all measured , following a similar shape to Δ measured at RT, see Fig. 12. At = 4.2 K, the observable range is limited as the substrate temperature drops below 10 K for > 15 µm, as discussed previously. The Δ evolution over matches the pad-accessible diode data, e.g. a minimum at ≈ 100 K. At = 4.2 K severe substrate heating was observed, as much as 7 K, measured 15 µm from the heater dissipating 2 = 6.5 mW. Substrate heating at = 160 K as a function of 2 ( Fig. 13) uncovers detectable substrate heating 30 µm from the heater at 2 > 3.6 mW, while negligible heating is observed at 2 ≤ 0.6 mW. A 0.1 K short-term is visible, impacting the diode measurement at = 6.3 µm.

D. Ultra-Wide-Temperature Self-Heating Model
In order to make the IC design work-flow cryo-SH aware, SH was modeled via a similar approach as in [22], but for bulk CMOS. First, the differential thermal resistance ( * ℎ = Δ ℎ / ) has been calculated from data in Fig. 8, and plotted as a function of absolute channel temperature ( ℎ = +Δ ℎ ) in Fig. 14. The extracted * ℎ at < 50 K partially overlap, proving the validity of the measured channel SH. Since SH in bulk is far less pronounced compared to SOI, and even less at higher temperatures, the ℎ range for > 50 K is limited and gaps appear in the * ℎ curve. The previously discussed minimum and rapid increase in SH at deep-cryogenic temperatures are also reflected in this curve. The shape of the * ℎ curve, and in particular the deviation from the expected * ℎ valley around 40 K, is compatible with the one shown in [20]. This curve illustrates that a single function is able to describe the complete * ℎ behavior of this structure over the full temperature range from RT down to 4.2 K, and can thus be employed to model SH over and . As the data at deep-cryogenic temperatures are similarly shaped to those in [22], but deviates at higher temperatures (containing a minimum, not monotonically decreasing), * ℎ was split into two regions, only to aid fitting. For ℎ ≤ 70 K Eq. (1) [22] was used: * while for ℎ > 70 K a simple parabolic function was fitted to the data to capture the minimum and the PTC behavior, both shown in Fig. 14. Finally, these two fitted functions and Eq. (2) [22] were used to predict SH as a function of and .
The resulting models for various are plotted in Fig. 15. These plots show that the very simple Eq. (2) is capable of successfully predicting SH over the full range from 4.2 K up to RT, including both the linear and square-root-like behavior, with < 3 K error in the 0 to 7 mW range.

E. SH Impact on Cryo-CMOS Circuits
While the cryo-SH data and modeling presented above could enable the next steps in reliable cryo-CMOS design, conclusions on the impact of circuit behavior can already be drawn. Although SH is indeed severe for below 50 K (see Fig. 8), ℎ will not exceed an absolute temperature above 60 K even for a dissipated power of a few mW's, due to the minimum in the thermal resistance, as clearly highlighted by replotting the data from Fig. 7 in Fig. 16. Since the key transistor parameters, such as threshold voltage, current factor and subthreshold slope, as well as passive-device characteristics, such as (see Fig. 6), were shown to saturate at temperatures below 50 K [8], [9], SH would not significantly impact the circuit bias conditions and its dynamic performance, causing a relative temperature insensitivity in this regime. However, the increase in circuit temperature by tens of degree Kelvin above can significantly degrade the noise performance for a thermal-noise-limited circuit, although it is still unclear whether temperature-independent shot-noise may be the main limitation in transistor's noise performance at deep-cryogenic temperatures [40]. Moreover, since the exact position of the thermal-resistance minimum cannot be fully attributed to the thermal properties of silicon, but heavily depends on the die thermalization, such as the package, the ℎ may vary due different positions on the die or boundary conditions of the die with the surrounding enclosure. Devices at tens of µm distance from each other can still experience significant thermal crosstalk at deep-cryogenic temperatures even at moderate power levels ( > 4 mW) within at least a radius of 30 µm (see Fig. 12 and 13). This directly translates into layout guidelines to properly space power-hungry devices from noise-sensitive circuits and precision circuits for which matching is a major consideration.
V. C A 40-nm CMOS test structure was fabricated and characterized for a comprehensive evaluation of self-heating in bulk CMOS technology in the ambient temperature range from 300 K down to 4.2 K. The temperature rise was measured both in the MOSFET channel through the change in the gate resistance, and in the surrounding silicon substrate by a linear array of diodes operating as sensors. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 40 K for a dissipated power of only 2 mW at a 4.2 K ambient temperature. Although the thermal conductivity of silicon is relatively low at very low temperatures, the absolute channel temperature does not exceed 60 K even for significantly higher power, due to the thermal resistance for a typical MOSFET, which has minimum above 70 K. This effect was confirmed by extracting the device thermal resistance from measured data at different temperatures and modeling it with a simple analytical expression able to predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The spatial propagation of SH results in a rise in substrate temperature detectable and quantifiable at a distance of 30 µm from the heater. The thorough characterization of nanometer bulk-CMOS devices at cryogenic temperatures is of paramount importance for the design of the integrated control electronics for quantum processors. For achieving first-time-right silicon, it is imperative to simulate the circuit at the actual operating temperature rather than assume the ambient temperature. Towards that goal, the results and modeling presented in this work will contribute towards the full self-heating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.
A The authors would like to thank Dr. H.P. Tuinhout for the helpful discussions and Intel for funding.