Analytical Modeling of Modular Multilevel Converter Under Pole-to-Pole DC Fault and Application to System Design and Protection

An analytical model for the half-bridge submodule based modular multilevel converter (MMC) under pole-to-pole fault is formulated, implemented, and validated. The events after the fault occurrence are categorized into four stages, and the equivalent circuit of each stage is derived. A generic equivalent circuit is developed respectively for the analytical calculation of the AC grid currents and the circulating currents during the fault, taking into account the conducting states of the switching devices. With knowledge of those currents, further analytical expressions of the fault currents of the converter arms and the DC grid are derived. Since the analytical expressions of the fault currents are functions of the main circuit parameters and the prefault operating point, the analytical model of the MMC under the pole-to-pole DC fault offers an answer to an entire set of problems. Enhanced insight into the parameters influencing the fault currents is available with the help of the analytical model. As a promising application, the proposed analytical models are utilized for the parameter design of the converter and for the selection of the interrupting capability of the circuit breakers. In the performed validation involving the CIGRE B4 DC test system, the analytical results are shown to be highly consistent with those of computationally more expensive solutions based on numerical simulation.

T HE modular multilevel converter (MMC) has become the most prominent converter topology for high-voltage direct current (HVDC) and multi-terminal DC (MTDC) applications [1], [2], [3]. The performance of converters subjected to DC fault is to be considered when developing DC grids. The susceptibility to a DC short-circuit fault, and particularly the potential damage caused to the converter IGBTs due to overcurrent, is an issue that must be addressed. As such, efforts have been taken to investigate the fault responses and protections [4]. In this context, the availability of an analytical model of the MMC under DC fault condition would be very valuable. It would provide an in-depth insight into parameters influencing overcurrent and overvoltage. Thanks to analytical modeling, engineering formulations for system design and circuit breaker configuration become available, providing valuable information for both manufacturers and system operators. This observation has motivated the analytical modeling described in this paper.
An important building block of the MMC is the submodule, denoted by SM in Fig. 1. Submodules are available in several variants. Among those variants, the most common one is the half-bridge submodule for its merits of low initial cost and high efficiency [4]. When employing the half-bridge submodule, an MMC is vulnerable to DC short-circuit faults, among which the pole-to-pole fault is the most severe one [5]. During the pole-to-pole fault, an overcurrent occurs in the converter due to a low DC link voltage. The rate of change of the fault currents is limited by the arm inductors. When selecting an appropriate arm inductance design, the overload capability of the insulated gate bipolar transistors (IGBTs) is to be considered since the IGBTs in the converter arms have limited overload capability and may be damaged by large currents [6], [7]. The fault currents are eventually cleared by opening the AC circuit breakers (CBs). The requirement of the interrupting capability of the circuit breaker relies on the knowledge of the fault currents [8]. Taking into account the physical limitation of the converter and the importance of a secure operation of the power system, it is essential to understand the fault response. It is also essential to quantify the impacts of the system parameters as well as of the operating point on the fault currents.
To quantify the fault currents, numerical simulation may be adopted. In [9] and [10], the solutions of the fault currents are obtained from electromagnetic transient (EMT) simulations for HVDC systems based on the two-level voltage source converter (VSC) and the MMC. Repeated EMT simulations are necessary to get information such as the minimum arm inductance needed to keep arm currents within acceptable limits. Moreover, the influence of each parameter on the fault currents is not readily apparent.
Compared with a numerical model, an analytical model offers mathematical closed-form expressions of fault currents and so gives an in-depth illustrative insight. Analytical models of the MMC under the pole-to-ground fault are given in [11], [12], [13]. The power keeps being transmitted in the first few milliseconds after the pole-to-ground fault. The submodules are not blocked. The two arms of a phase and the AC grounding path in the corresponding phase form a circuit in star connection. Applying the star-delta transformation to the circuit yields an equivalent circuit of constant parameters [11]. While this is applicable to the pole-to-ground fault, such transformation cannot be applied to the MMC under the pole-to-pole fault. The fault current flows through different paths under these two types of DC faults. Instead of flowing through the AC grounding path, the fault current of the MMC under the pole-to-pole fault flows through the arms and the DC link.
After a few milliseconds of the fault occurrence, all IGBTs may be turned off due to overcurrent. Simultaneously with the turning-off actions of the IGBTs, the submodules are blocked. Then, the fault current flows through the freewheeling diodes, as denoted by D 2 of the submodule shown in the upper left part of Fig 1. The MMC may behave like a three-phase halfwave rectifier, and analytical solutions to fault currents are given in [13]. Such analytical solutions cannot be extended to the MMC under pole-to-pole faults. During such faults, large arm currents and low DC-link voltage result in different switching actions of freewheeling diodes in comparison with the MMC under the pole-to-ground fault.
For the MMC under the pole-to-pole fault, most of the analytical models for the fault current calculation are proposed on the premise that the submodules are non-blocked. Such a premise is reasonable if the arm currents could remain at relatively small values [14]. Analytical models of the MMC with non-blocked submodules are given in [14], [15], [16]. In those models, the ripples of the submodule capacitor voltages are neglected. In fact, the voltage ripple could reach up to 10% of the DC component of the capacitor voltage [17]. Neglecting the capacitor voltage ripples results in inaccurate calculation of the capacitor discharging currents. Shortly after the fault occurrence, all IG-BTs may be turned off due to overcurrent caused by capacitor discharging behaviors. For the MMC with all IGBTs in off states, the fault currents flow through the freewheeling diodes. The conducting states of the arms vary due to changing operating states of the freewheeling diodes. The varying conducting states of the arms result in diverse topologies of the converter [18]. Two converter topologies with respectively three and four arms in conducting state are taken into consideration in [14]. Based on observations from reality, with diverse main circuit parameters and operating points, there are more topologies beyond those two considered. A generic analytical model valid for diverse topologies of the MMC under pole-to-pole faults is still missing.
In this work, the events following the pole-to-pole fault occurrence of the MMC based on the half-bridge submodule is categorized into four stages, and the equivalent circuit of each stage is derived. In the analysis, the impacts of the capacitor voltage ripples are taken into consideration. Generic equivalent circuits valid for all four stages are developed, taking into account the conducting states of the circuit breakers, the submodules, and the converter arms. Based on these generic equivalent circuits, the analytical solutions of the fault currents of the AC grid, of the converter arms, and of the DC grid are derived. As an engineering application, the proposed analytical model is applied to the design of the arm inductance and the selection of the circuit breaker interrupting capability. Iterative numerical computations are not involved.
Following this introduction, the mathematical model of the MMC in the steady state is summarized in Section II. In Section III, the events following the pole-to-pole fault occurrence are categorized into four stages, and the equivalent circuit of each stage is derived. Section IV is concerned with the derivation of the analytical solutions of the fault currents and voltages. In Section V, the analytical model is applied to the circuit parameter design and the selection of the circuit breaker interrupting capability. The validation is performed using the CIGRE B4 DC test system in Section VI. Conclusions are drawn in Section VII. Plausible assumptions and modeling details are summarized in the appendix.

II. REVIEW OF BASIC OPERATING PRINCIPLES
The three-phase MMC, as depicted in Fig. 1, is shown to be composed of three legs. Each leg consists of two arms connected in series. An arm contains N identical half-bridge submodules in series connection. Each such submodule consists of two insulated gate bipolar transistors (IGBTs), two diodes, and one capacitor. In each arm, there is one inductor of inductance L arm connected in series with the submodules.

A. Mathematical Model of MMC in Steady State
The voltages generated by the cascade of submodules in the arms of phase a are represented by v ua and v la , where subscripts u and l denote the upper and lower arms. Likewise, the upper and lower arm currents in phase a are denoted by i ua and i la . The AC terminal voltage of the converter and the AC grid current in phase a are respectively denoted by v ta and i sa , while the DC terminal voltage is v dc .
The DC and AC terminal voltages can be obtained by Kirchhoff's voltage law as The arm resistance R arm representing the on-state resistance of power electronic switching devices is negligible in normal operation [19]. With respect to (2), it is convenient to define the inner electromotive force e sa generated in the leg of phase a as [20] To determine the phase angles of sinusoidal quantities, a reference waveform must be chosen: where ω s is the angular frequency of the AC grid, andV s is the amplitude of the inner electromotive force. For steady-state analysis, the AC grid current is defined as whereÎ s is the amplitude of the AC grid current, and ϕ is the phase lag of i sa with respect to e sa . The AC grid current is equally fed into the two arms of one leg under balanced condition. Except for the AC feeding current, the circulating current also exists in each arm [18]. The circulating current flowing in each leg of the converter consists of a DC component and harmonic components [21]. The DC component is one third of the DC link current. The harmonic components of the circulating current are well suppressed in accordance with assumption 1 of Appendix A. Consequently, the upper and lower arm currents can be expressed by the sum of the AC feeding current and the circulating current as Neglecting R arm and inserting (6) into (1) eliminates i la and i ua from (1), resulting in v dc = v la + v ua in steady-state operation. Combining the obtained equation with (3) and then inserting (4) results in the upper arm voltage v ua and the lower arm voltage v la as where the modulation index M is given by

B. Calculation of Ripple Voltages of Capacitors
As shown in the upper left part of Fig. 1, depending on the switching signal issued by the controller to the submodule, the submodule capacitor is inserted into the arm, or it is bypassed. The inserted capacitors may discharge or be charged according to the arm current polarity. Due to switching actions, the ripple voltages of the capacitors appear at the AC terminal of the submodule. According to [19], taking into consideration N submodules in one arm, the total ripple voltages up to third-order terms respectively for the upper arm and the lower arm are given by (49) and (50) in Appendix B. By summing up the ripple voltages of the upper and lower arms, the total ripple voltage v a,rip (t) of the leg in phase a is approximated by v a,rip (t) = − NMÎ s 8ω s C sinϕ (9) where N is the number of submodules in one arm, and C is the capacitance of the submodule capacitor. The ripple voltages for phases b and c can be obtained in a similar manner. Because of symmetry in the steady state, the ripple voltages of the three phases will be identical apart from phase shifts of 0 rad, −4π/3 rad, and 4π/3 rad applied to the sinusoidal quantities that are functions of time t in the phases a, b, and c.

C. Half-Bridge Submodule With Bypass Thyristor
Overcurrents have been reported during transient disturbances, such as AC and DC short-circuit faults [17], [18]. To avoid damage on diode D 2 , as shown in Fig. 2(a), it is common practice to connect a single thyristor in parallel with the AC port of the submodule [18]. The fault current then flows through thyristor S 2 in parallel with diode D 2 . A single thyristor is usually sufficient if the aim is just to protect the diode from overcurrent. Double thyristor switches, as shown in Fig. 2(b), provide a path for both positive and negative arm currents [5]. Thus, the AC current cannot feed into the DC grid thanks to the symmetrical topology of the converter. The impacts of the thyristors on the fault responses are detailed later in Section III-D. The analytical modeling of the MMC under the pole-to-pole fault makes use of the proposed equivalent circuits. There are multiple equivalent circuits during the fault stages due to the varying conducting states of the circuit breakers, the submodules, and the converter arms. According to those varying conducting states, the events following the pole-to-pole fault occurrence are categorized into four stages. An overview of the fault stages is given in Section III-A. The transient responses and the equivalent circuit of each stage are detailed in Section III-B. The conducting states of the circuit breakers, the submodules, and the converter arms for the four stages of the fault responses are summarized in Section III-C. In Section III-D, the impacts of the protection scheme using thyristors are discussed.

A. Overview of Fault Scenario and Fault Stages
A pole-to-pole short-circuit fault on the DC link of the MMC is considered. The analysis focuses on the converter based on half-bridge submodules with the basic circuit as shown in the upper left part of Fig. 1. The submodule topology with bypass thyristor switches, as discussed in Section II-C, is considered as a special case. The fault scenario is described as follows. The pole-to-pole short-circuit fault on the DC link occurs at time t 0 . Shortly after the fault occurrence, the submodules are blocked at t bs due to overcurrent. The MMC based on half-bridge submodules is unable to extinguish the DC arc by blocking the submodules [22]. Therefore, the AC circuit breakers are opened at t ob so as to isolate the short-circuit fault. The time interval from the time t bs of blocking submodules to the time t ob of opening the circuit breaker is expected to lie in a range of 60 ms to 100 ms [23].
The fault process is decomposed into four stages, as shown in Fig. 3. The stage I, extending from time t 0 of fault occurrence to time t bs of blocking submodules, is the capacitor discharging stage. The stage II is the diode freewheeling stage with the time span from t bs to the time t cz of the first zero-crossing of the arm currents. Spanning from t cz to the time t ob of opening AC circuit breakers, the stage III is defined as the grid current feeding stage. Going from the time t ob to the end, the stage IV is called the AC circuit open stage.

B. Transient Responses and Equivalent Circuits
In what follows, the system behavior and the equivalent circuit of each stage are detailed.

1) Stage I -Capacitor
Discharging Stage: During this stage, the submodules continue to switch as in the prefault operation. The submodule capacitors, as shown in the upper left part of Fig. 1, alternate between inserted and bypassed states. The inserted capacitors discharge through the arms and the DC link due to low voltage at the DC terminal, leading to overcurrent. Despite the discharging behavior, the capacitor voltages may be regarded as constant because of the short duration of the discharging period [15]. Consequently, the topology of the converter is the same as that in the prefault condition.
The equivalent circuit for the stage I is shown in Fig. 4. At the AC terminal of the converter, the AC circuit breakers (CBs) remain closed. In the DC link, R dc and L dc are the resistance and inductance of the cable between the converter DC terminal and the fault location, respectively. In each arm of the converter, there is one resistor of resistance R arm , representing the on-state resistance of the power electronic switching devices in the arm. Anti-parallel equivalent diodes are added to each arm since the arm current can be positive or negative. For the upper arm of phase a, the anti-parallel equivalent diodes are referred to as D ua,1 , D ua,2 . When the arm current is positive, the upper arm current of phase a flows through D ua,1 . Referring to Fig. 1, the positive arm current flows through the T 1 of inserted submodules and through the D 2 of the bypassed submodules. When the arm current is negative, the upper arm current of phase a flows through D ua,2 of the equivalent circuit in Fig. 4. Referring to Fig. 1, the negative arm current flows through the D 1 of inserted submodules and through the T 2 of the bypassed submodules.
A variable capacitor is added to each arm to represent the total inserted capacitors. The voltages of the variable capacitors in the upper and lower arms are denoted by v uj,arm and v lj,arm . Each capacitor voltage is composed of two terms. One term is the voltage v uj or v lj representing constant capacitor voltages as given by (7). The other term is the voltage v uj,rip (t) or v lj,rip (t) caused by ripples of the capacitor voltages, as given by (49) and (50). The composite of those two terms yields the voltages of Referring to (7), (49), and (50), the second-order harmonic components are included in the arm voltages v uj,arm (t) and v lj,arm (t).
The higher-order harmonic components of the arm voltages are neglected in accordance with assumption 2 of Appendix A.
The AC grid operates in the same way as in the prefault time period since the submodules continue to switch as under normal operating conditions. With the AC grid in quasi-steady state, the grid current i sj , j ∈ {a,b,c} is the same as that in the prefault condition. The AC grid current is equally fed into the upper and lower arms since the converter topology is symmetrical. Besides the AC feeding currents, the circulating current i j,cir , j ∈ {a,b,c} does exist in the arms, as marked by the dashed lines in Fig. 4. The circulating currents flow through the legs and the DC link. Because of the discharging behavior of the inserted capacitors, the circulating currents increase rapidly. Consequently, the arm current is composed of the AC feeding current and the circulating current as where i uj,Af (t) and i lj,Af (t) are the AC feeding currents in the upper and lower arms, and i j,cir (t) is the respective circulating current. The reference directions of the AC feeding currents are the same as those of the respective circulating current, as marked in Fig. 4. Due to the rapidly increasing circulating currents, the arm currents increase rapidly, too.  3) Stage III -Grid Current Feeding Stage: This stage is initiated as soon as one of the six arm currents reaches zero. The corresponding arm gets into a non-conducting state, and the circuit becomes asymmetrical. Due to the resulting asymmetry of the circuit, the AC grid currents begin to feed into the DC grid. The equivalent circuit of this stage is shown in Fig. 6, in which at least one of the six arms is non-conductive. In the illustrated equivalent circuit, the lower arm of phase a is non-conductive, and the equivalent diode D la,1 is in off state. The AC grid current i sa flows through the upper arm of phase a, while the circulating current i a,cir of this leg becomes zero. The operating states of the freewheeling diodes vary during this stage. A diode becomes non-conductive when the arm current reaches zero and is forced to be conductive when its forward voltage drop becomes positive.

4) Stage IV -AC Circuit Open Stage:
To isolate the DC shortcircuit fault, the AC circuit breakers are opened within tens of milliseconds of the fault occurrence [17]. The equivalent circuit of this stage is shown in Fig. 7, in which all six arms are in the conducting state.
The AC grid currents i sj , j ∈ {a,b,c} are forced to be zero since the AC circuit breakers are opened. In the converter arms, the AC feeding currents are absent, while the circulating currents i j,cir continue to flow. The circulating currents decay slowly since the arm resistance R arm and the cable resistance R dc are relatively small, while the arm inductance L arm is relatively large. Thus, it takes a relatively long time for the circulating currents to practically disappear.

C. Operating States of Switching Devices
The topologies of the equivalent circuits differ among the fault stages. For the purpose of finally deriving a generic equivalent circuit that is valid for the entire transient process, three sets of operating states are defined, as summarized in Table I.
Firstly, the conducting states (ρ sa , ρ sb , ρ sc ) of the AC circuit breakers in phases j ∈ {a, b, c} are defined as ρ sj (t) = 1, circuit breaker closed 0, circuit breaker opened.
The circuit breakers remain closed in stages I to III and are open in stage IV. Secondly, the operating states (σ ea , σ eb , σ ec ) of the submodules in phases j ∈ {a, b, c} are defined as The submodules are non-blocked in the stage I and are blocked in the stages II to IV. In the non-blocked state, the IGBTs are turned on and off as in the prefault operation. The submodule capacitors, as shown in the upper left part of Fig. 1, alternate between inserted and bypassed states. In the blocked state, all IGBTs of submodules are in off states, and submodule capacitors are bypassed. The arm currents flow through the freewheeling diodes, as depicted by D 2 in the upper left part of Fig. 1. Thirdly, the conducting states (ς ua , ς ub , ς uc , ς la , ς lb , ς lc ) of the converter arms are defined as ς lj (t) = 1, lower arm conductive 0, lower arm non-conductive.
The converter arms are conductive in stage I. The arm currents can be positive or negative. The bidirectional arm currents flow through the anti-parallel equivalent diodes D uj,1 , D uj,2 of the upper arms and D lj,1 , D lj,2 of the lower arms in Fig. 4. In stages II and IV, the converter arms are also conductive. The arm currents are positive and flow through the freewheeling diodes, as shown by D 2 in the upper left part of Fig. 1. As shown in Figs. 5 to 7, the unidirectional arm currents flow through the equivalent diodes D uj,1 and D lj,1 . In stage III, the arm conducting states vary. The arm currents could be positive or zero, as discussed in Section III-B3. In the illustrated equivalent circuit in Fig. 6, the lower arm current of phase a is zero, and the equivalent diode D la,1 is in off state.

D. Impacts of Bypassing Thyristors on Fault Stages
For a submodule with a single thyristor, as depicted in Fig. 2(a), the thyristor S 2 operates in parallel with the diode D 2 . The thyristor S 2 is kept in the off state in the prefault condition and stage I, and it is triggered on as soon as the fault is detected. The transient responses to the pole-to-pole fault are the same as that of the MMC utilizing submodules without bypass thyristors. The corresponding equivalent circuits for the four stages of the transient responses are given as in Figs. 4 to 7. The arm resistance R arm in the stages II, III, and IV includes the on-state resistance of the freewheeling diodes and the thyristors of one arm with each diode D 2 and thyristor S 2 of one submodule illustrated in the upper left part of Fig. 1.
For the submodule with double thyristors, as depicted in Fig. 2(b), the thyristors are kept in the off states in the prefault condition and in the stage I. Both thyristors are switched on as soon as the fault is detected. With those bidirectional switches, all arms are conductive throughout the fault period. Consequently, the transient responses stay within the stages I and II.
In order to develop a generic model of the MMC under the pole-to-pole fault, the submodule without thyristors as shown in the upper left part of Fig. 1 is considered hereafter. From the so obtained generic model, MMCs with thyristors in the submodules are obtained as special cases.

IV. ANALYTICAL MODELING OF FAULT CURRENTS OF MMC UNDER POLE-TO-POLE FAULT
To address the varying topologies of the converter caused by changing conducting states of switching devices, two generic equivalent circuits respectively for the calculations of the AC grid currents and the circulating currents are developed. Through these two generic equivalent circuits, the analytical expressions of the AC grid currents, the arm currents, and the DC grid current are derived.

A. Generic Equivalent Circuits for Severe Pole-to-Pole Fault
A pole-to-pole fault could happen at any location on the DC link. For applications such as the parameter design of the converter and protection, it is of interest to focus on the most severe situation [24]. As such, a pole-to-pole fault is applied close to the converter in accordance with assumption 3 of Appendix A. Thus, the resistance R dc and the inductance L dc in the DC link are set to zero. The bypassing thyristors of the submodules illustrated in Fig. 2 are not considered yet as those lead to special cases as discussed in Section III-D.
The topologies of the equivalent circuits of the fault stages vary because of the changing conducting states of the switching devices, as depicted in Figs. 4 to 7 and given in Table I. Referring to assumption 4 of Appendix A, for any topology as defined by the states of the switching devices, the corresponding equivalent circuit is linear. In order to develop the generic equivalent circuits, considerations start with the composition of the arm currents. As discussed in (12) of Section III-B, the arm currents are composed of the AC feeding currents and the circulating currents. The AC feeding currents are attributed to the AC grid currents, while the circulating currents only flow through the legs and the DC link. Since the circulating currents do not flow into the AC grid, the AC grid currents and the circulating currents are decoupled.
Depending on the equivalent circuits of Figs. 4 to 7, taking into account the conducting states of the switching devices listed in Table I, two equivalent circuits respectively for the calculations of the AC grid currents and the circulating currents are developed and given in Fig. 8. The equivalent circuit for the calculation of the AC grid currents is shown in Fig. 8(a). The AC grid voltages are denoted by v sa , v sb , and v sc . Binary variables ρ sa , ρ sb , and ρ sc denote the states of the ideal AC circuit breakers, as given by (13). The equivalent resistance R j and inductance L j of phase j ∈ {a, b, c} cover the resistors and inductors of the AC grid and the converter arms. The upper and lower arms of one leg operate in parallel if both arms are conductive, resulting in R j = R s + R arm /2 and L j = L s + L arm /2. If one of the upper and lower arms of one leg is non-conductive, the AC grid current of the corresponding phase only flows through the conductive arm, resulting in R j = R s + R arm and L j = L s + L arm . Taking into account the above mentioned arm conducting states, the resistance R j and the inductance L j of the phase j ∈ {a, b, c} are defined as where ς uj and ς lj represent the arm conducting states, as given in (15) and (16). The voltage sources e ta , e tb , and e tc represent the converter inner electromotive forces obtained by the voltages of the capacitors inserted in the arms. During the stage I, the capacitors continue to switch as in the prefault operation, as shown by the variable capacitors in Fig. 4. Thus, the AC grid operates in quasi-steady state, and the inner electromotive force is given by e sj with j ∈ {a, b, c}, as shown in (4). During the stages II to IV, the capacitors are bypassed since the submodules are blocked, resulting in the absence of e sj in the equivalent circuit. Thus, the voltage source e tj is defined by weighting e sj by the operating state σ ej of the submodules as: where σ ej is equal to 0 or 1 as given by (14). The equivalent circuit for the calculation of the circulating current i j,cir of phase j ∈ {a, b, c} is shown in Fig. 8(b). The circulating current flows through the leg and the DC link. Considering upper and lower arms of one leg, the equivalent resistance and the equivalent inductance of the leg are given by 2R arm and 2L arm . In each leg, the ideal switches ς uj and ς lj with j ∈ {a, b, c}, as given by (15) and (16), represent the arm conducting states. The binary variable σ ej gives the state of submodules of phase j ∈ {a,b,c}, as given by (14). The binary variableσ ej denotes the negation logic of σ ej . According to (14), σ ej = 0 when the submodules are non-blocked, andσ ej = 1 when the submodules are blocked. The binary variables ς uj , ς lj , and σ ej in the four stages of the DC fault are given in Table I. In stage I, all these binary values are equal to 1. With each submodule having a capacitor of capacitance C, the equivalent capacitance of one leg is given by C/N since N submodules are inserted within one leg [25]. The voltage across the ideal switch σ ej with j ∈ {a, b, c} and the equivalent capacitance C/N is given by v j,leg . In the stages II to IV, the binary variable σ ej is equal to 0. The equivalent capacitance C/N is bypassed since the submodules are blocked. In stage III, the conducting states of the ideal switches ς uj and ς lj are changing since the arm conducting states are varying, as discussed in Section III-B3.
The voltage v j,leg in Fig. 8(b) represents the total voltage across the inserted capacitors of one leg of phase j ∈ {a, b, c}. For the convenience of later calculating the circulating current i j,cir , the initial values of v j,leg at the beginning of each fault stage are to be formulated. The total voltages of the inserted capacitors respectively in the upper and lower arms at time t 0 of fault occurrence are given by v uj,arm (t 0 ) and v lj,arm (t 0 ) in (10) and (11). The ripple components v uj,rip (t) and v lj,rip (t) of v uj,arm (t) and v lj,arm (t) at the beginning of the stage I are considered since they are to affect the capacitor discharging currents. The voltage v j,leg (t 0 ) of one leg is then obtained by summing up the upper and lower arm voltages at the time t 0 of the fault occurrence, that is v uj,arm (t 0 ) + v lj,arm (t 0 ). During the stages II to IV, the capacitors are bypassed since all IGBTs are turned off, resulting in zero initial and steady-state values of v j,leg in each stage. Consequently, the voltage v j,leg at the beginning of each stage is obtained as where σ ej is the representation of the state of the submodules of phase j ∈ {a, b, c} according to Table I, and 0 + denotes the time instant of the beginning of a stage. Inserting (7) and (9) into (10) and (11), and further inserting the obtained result into (20) yields the voltage v a,leg at the beginning of each stage for the leg a as: where v dc,pre and i dc,pre are the DC voltage and current at the prefault operation. Taking into consideration the phase shifts of 0 rad, −4π/3 rad, and 4π/3 rad in the phases a, b, and c of the ripple voltages, the voltages v b,leg (0 + ) and v c,leg (0 + ) for the legs b and c can be obtained similarly.

B. Analytical Modeling of AC Grid Currents
The analytical modeling of the AC grid currents is to only rely on the equivalent circuit of Fig. 8(a). The equivalent circuit of Fig. 8(b) for the circulating currents is not involved since the AC grid currents and the circulating currents are decoupled. Applying Kirchhoff's voltage law to the equivalent circuit yields with the state matrix A and input matrix B given by Applying the Laplace Transform to (24) yields with where i(0 + ) is the initial value of the state vector; E is the identity matrix; adj(sE − A) is the adjugate matrix; a 11 , a 12 , a 21 , and a 22 are the elements of the state matrix A.
The voltage sources v sa , v sb , e ta and e tb in the input vector v are sinusoidal quantities of angular frequency ω s . Inserting (28) into (27) where j is the imaginary unit, D could be positive or zero for the diverse topologies of the converter during the fault. When the circuit is asymmetrical, insertion of (17) and (18) (29) is performed for these two cases, respectively. In the case of D > 0, the four roots s 1 , s 2 , s 3 , and s 4 in (30) are different from each other. Application of the inverse Laplace Transform gives the AC grid currents where the coefficients C m = lim s→s m (s − s m )i(s), m = 1, 2, 3, 4; (C 1 − C 2 ) gives an imaginary value. In the case of D = 0, s 3 and s 4 in (30) are the same. Applying the inverse Laplace Transform to (29) yields the AC grid current where the coefficients C 1 and C 2 correspond to those of (31), C rp3 = lim

C. Analytical Modeling of Arm Currents
In accordance with (12), the arm currents are composed of the AC feeding currents i uj,Af (t), i lj,Af (t) and the circulating currents i j,cir (t). The AC feeding currents i uj,Af (t) and i lj,Af (t) in the upper and lower arms are attributed to the AC grid currents, taking into account the arm conducting states. When both the upper and lower arms of one leg are conductive, the AC grid current is equally split between the two arms. When one of the upper and lower arms of a leg is non-conductive, the AC grid current flows through the conductive arm. Based on this observation, the AC feeding currents i uj,Af (t) and i lj,Af (t) in the upper and lower arms of leg j ∈ {a, b, c} are calculated as where the AC grid current i sj is given by (31) and (32) involving i sa and i sb , while i sc is obtained as (−i sa − i sb ); ς uj and ς lj are the representations of the arm conducting states, as given by (15). Another contribution to the arm current is given by the circulating current i j,cir (t), which flows through the leg and the DC link, as shown in Fig. 8(b). Each leg is composed of the inductance 2L arm , the resistance 2R arm , the equivalent capacitance C/N , and the ideal switches representing operating states of the switching devices. According to the equivalent circuit, the dynamic response of the circulating current i j,cir is described by where N is the number of submodules per arm, C is the capacitance of each submodule; σ ej denotes the operating states of the submodules, as given by (14). Solving (34), the circulating current i j,cir (t) in the leg j ∈ {a, b, c} is expressed by where 0 + denotes the initial value at the beginning of the present fault stage. The initial value v j,leg (0 + ) is given by (20) and (21). Details on the formulation of the initial value of the circulating current i j,cir (0 + ) are formulated in Appendix C.
Referring to (12), the combination of (33) and (35) yields the upper and lower arm currents as with v j,leg given by (20) and (21); i sj (t) is given by (31)

D. Analytical Modeling of DC Grid Current
The DC grid current i dc (t) is calculated by summing up the upper arm currents of each phase: (39) Also, the DC grid current is seen to be composed of the AC feeding currents and the circulating currents. The sum of the AC feeding currents is non-zero only in the stage III due to the asymmetrical behavior of the converter, in which at least one arm is in non-conducting state. The circulating currents increase in stage I because of the discharging behavior of the inserted capacitors, and they decrease in the stages II to IV since the capacitors are being bypassed.

V. PARAMETER DESIGN OF ARM INDUCTOR AND SELECTION OF CIRCUIT BREAKER INTERRUPTING CAPABILITY
For a secure operation of the power system, the overload capability of the power electronic switching devices is an important parameter [7]. Furthermore, it must be possible to isolate a fault by opening the circuit breakers in order not to significantly disturb the healthy parts of the system [15]. With regard to those requirements, the parameter design of the arm inductor is considered in Section V-A. Section V-B is concerned with the determination of the circuit breaker interrupting capability.

A. Parameter Design of Arm Inductor
The arm inductor is known as one of the most critical parts of MMC converters, and it plays a dominant role in converter operation [26]. There are various principles of designing arm inductance based on different criteria, such as current ripple, capacitor energy variation, and short-circuit current. Taking into consideration the MMC under the pole-to-pole fault, the converter arms may suffer from overcurrent due to the capacitor discharging in stage I, as discussed in Section III-B1. The arm inductors limit the rise of fault currents involved. One principle of the arm inductance selection is to limit the maximum arm current within a preset critical value at time of blocking submodules at the end of stage I. To calculate the maximum arm current, a common practice is to employ an equivalent circuit consisting of DC voltage sources, arm inductors, and the DC-link fault path. Such an equivalent circuit neglects the AC feeding currents in the arms and the ripple voltages of the capacitors. These neglected factors are carefully considered in the proposed analytical model of the MMC under the pole-to-pole fault, resulting in better accuracy of the maximum arm current calculation.
For the analysis in (12) and (38), the maximum values of AC feeding currents and circulating currents at the time t bs of blocking submodules are defined as i Af,bs and i cir,bs hereafter. Taking into account these maximum values, the maximum arm current i arm,bs at t bs is formulated as: For the calculation of the maximum AC feeding current i Af,bs , (33) is useful. Depending on the arm conducting states, the AC feeding current is one half of the AC grid current in the stage I. Thus, the maximum AC feeding current i Af,bs is obtained as whereÎ s is the amplitude of the AC grid current, as given by (5). Referring to Fig. 8(b), the circulating current at the time t bs of blocking submodules is calculated with (35). The submodules are blocked shortly after the occurrence of the pole-to-pole short-circuit fault in practical application [17]. The voltage of the equivalent capacitance could so assumed to be constant, as given in assumption 5 of Appendix A. As such, the circulating current flows through the constant DC voltage source v j,leg , the inductance 2L arm and the resistance 2R arm . The circulating current i j,cir (t bs ) at the time t bs of blocking submodules is obtained as Focusing on the most severe condition, the maximum value of v j,leg in (21) at the time t bs of blocking submodules with random time t 0 of the fault occurrence is defined as v leg,bs . According to the details in Appendix D, the maximum value v leg,bs is expressed by v leg,bs = v dc,pre − NMÎ s 8ω s C sinϕ (43) where ϕ is the phase lag of the AC grid current with respect to the inner electromotive force of the converter. Substituting the maximum value v leg,bs for v j,leg in (42), the maximum circulating current i cir,bs at t bs is obtained as Insertion of (41) and (44) into (40), the maximum arm current i arm,bs at the time t bs of blocking submodules is formulated as Taking into account the overload capability of the IGBTs, the maximum arm current i arm,bs is required to be smaller than a critical value i arm,crit , that is Insertion of (45) into (46), the principle for the parameter design of the arm inductance is given by The converter may be overloaded up to 50% of its rated capacity for a short duration [6]. Thus, when applying (47), the critical arm current i arm,crit may be chosen as 150% of the maximum value of the arm current at rated output power.

B. Selection of Circuit Breaker Interrupting Capability
After blocking of the submodules, the fault currents continue to flow through the freewheeling diodes, as discussed in Section III. Those fault currents cannot be cleared until the circuit breakers are opened [27]. The interrupting capability of the AC circuit breaker is defined as i ac,rupt , which indicates the maximum current that can be successfully interrupted by the circuit breaker. This interrupting capability i ac,rupt is required to be larger than the maximum value of the AC grid currents at the time t ob of opening AC circuit breakers. Thus, to isolate the fault successfully, the interrupting capability of the AC circuit breaker is determined as where the AC grid current i sj is obtained from (31) and (32).

VI. VALIDATION
The performance of the developed analytical model is validated by application to a point-to-point MMC-HVDC of the   [28] CIGRE B4 DC test system [28]. The configuration of the test system is shown in Fig. 9 with a focus on the converter MMC-1. The main circuit parameters and the fault scenario are described in Section VI-A. In SectionVI-B, the analytical models of the fault currents and voltages are evaluated. The principle of the parameter design of the arm inductor is applied in Section VI-C.

A. Test System and Fault Scenario
The main circuit parameters of the point-to-point MMC-HVDC system are given in [17]. Each converter has one hundred half-bridge submodules per arm. The DC link voltage of the converter in prefault operation is at ±200 kV. The active power injected from the AC grid into the converter MMC-1 is set to 400 MW, while the reactive power is set to zero.
The events and time sequence of the fault scenario are described in Table II. A metallic pole-to-pole fault occurs at the DC terminal of the converter MMC-1 at 1 s. Due to overcurrent, the submodules of the MMC-1 are blocked at t bs = 0.62 ms after the disturbance. For the converter with half-bridge submodules, the fault currents are eventually interrupted by opening the AC circuit breakers at t ob = 62.26 ms.

B. Validation of Analytical Model of Fault Currents
The analytical result of the DC grid current in Fig. 9 is obtained from (39), while the AC grid currents are calculated by (31) and (32). The upper and lower arm currents in the three legs are obtained from (38). In Figs. 10 and 11, the fault currents are depicted in dotted lines. In order to get reference values, the test system is also implemented in the digital simulator PSCAD at a time step size of 1μ s. The numerical simulation results are depicted in solid lines in Figs. 10 and 11. The subscripts A and N are used to distinguish between the analytical and numerical results. The analytical results are shown to closely match the numerical results. The maximum deviation between the analytical and numerical results for the DC grid current is less than 0.05%. The maximum deviations of the AC grid currents and the arm currents are at less than 0.03% and 0.05%, respectively.   Fig. 10(a). It is shown that the durations of the stages I and II are short, while the durations of the stages III and IV are relatively long. In the stage I, the DC grid current is subject to a steep rise due to the discharging behavior of the capacitors of the submodules, as discussed in Section III-B1. No obvious increase in the AC grid currents is observed since the AC grid operates in quasi-steady state in this stage. In the stage II, the AC grid currents begin to increase since the submodule capacitors in the converter arms are bypassed, resulting in a shorted AC grid. The fault currents cannot be cleared by blocking the submodules for an MMC utilizing half-bridge submodules. Meanwhile, the DC grid current decreases since the submodule capacitors are bypassed, and the AC grid currents cannot feed into the DC grid. It is noticed that the DC grid current and arm currents reach maximum values in the stage III and decay slowly in the stage IV.

C. Validation of Parameter Design of Arm Inductor
The converter arms of the MMC under the pole-to-pole fault suffer from overcurrent, as shown in Fig. 11. The IGBTs may be damaged by overcurrent due to poor overload capability [6]. In order to turn off the IGBTs safely, the arm currents at the time of blocking submodules are required to be smaller than a critical value i arm,crit , as discussed in Section V-A. This critical arm current may be chosen as 150% of the maximum value of the arm current at the rated output power. For the given test system, i arm,crit is set to 4.454 kA. To respect the overload capability of the IGBTs, the minimum arm inductance is obtained as L arm = 0.057 H according to (47).
To demonstrate the capability of the arm inductors to limit fault currents, an MMC with the arm inductance of L arm = 0.057 H in Fig. 9 is considered. The active power is set to the rated value of 800 MW in the prefault operation, while the reactive power is set to zero. A pole-to-pole fault is applied to the DC terminal of the converter at 1 s. After t bs = 0.62 ms, the submodules are blocked due to overcurrent. The fault scenario is as given in Table II. In Fig. 12, the upper and lower arm currents of the three legs are shown. The critical arm current i arm,crit = 4.454 kA at the time of blocking submodules is marked by a black dot. At the time of blocking submodules, any arm current is shown not to exceed the critical value, while the arm currents i ua and i lb come close to the critical arm current. The other arm currents remain much smaller at this time of blocking submodules. The arm inductance may also be obtained from the commonly used analytical model in [29], [30], in which the capacitor voltage ripples and the AC feeding currents are neglected. The so obtained arm inductance is 0.037 H, which is smaller than 0.057 H. As such, the commonly used parameter design principle of the arm inductance is inaccurate, resulting in arm current exceeding its preset critical value.

VII. CONCLUSION
An analytical model for the MMC based on half-bridge submodules under the pole-to-pole fault was formulated, illustrated, and validated. The fault currents throughout the DC short-circuit fault were calculated analytically, taking into account the changing operating states of the switching devices and the resulting changing topologies of the converter.
The overall analytical modeling is distinguished by three contributions. Firstly, generic equivalent circuits of an MMC under the pole-to-pole fault were developed, involving the varying topologies of the converter. The equivalent circuits are applicable throughout the DC fault thanks to the defined binary variables denoting the operating states of the switching devices. Secondly, analytical solutions of the fault currents were formulated based on the proposed generic equivalent circuits. The analytical solutions are valid throughout the four stages of the pole-to-pole fault by updating the binary variables and initial values at the beginning of each stage. The ripple voltages of the submodule capacitors are taken into consideration, providing accurate initial values for the capacitor discharging behavior. The analytical formulas offer a deep insight into the main circuit parameters and the prefault operating point affecting the fault currents. Thirdly, as a promising application, an analytical equation for the design of the arm inductance was provided, taking into consideration the overload capability of the power electronic switching devices. As opposed to a numeric solution, the visibility of all the parameters affecting the design is fully given since the analytic solution was entirely derived through symbolic computations. Such visibility is interesting for follow-up investigation, leading to further advancements in system parameter design and protection configuration of the modular multilevel converter system. In sum, the contributions made offer an illustrative and accurate model of the MMC under the pole-to-pole fault.

A. Assumptions
To support the analytical modeling of the MMC under the pole-to-pole fault, the following assumptions are made: 1) In steady state, the harmonic components of the circulating current are well suppressed [18].
2) The higher-order harmonic components of the arm voltages are neglected.
3) The pole-to-pole fault is close to the DC terminal of the converter, and therefore R dc and L dc in the DC link are equal to zero, respectively. 4) For any topology as defined by the states of the switching devices, the corresponding equivalent circuit is linear. 5) Shortly after the pole-to-pole fault, the capacitor voltage remains at its predisturbance value due to short discharging period.

B. Ripple Voltages in Converter Arms
The capacitors of the submodules are either inserted or bypassed, depending on the switching actions of power electronic switching devices. The inserted capacitors may be charged or discharged depending on the arm current direction, resulting in ripple voltages. Due to the switching actions, the ripple voltages of the capacitors appear at the AC terminal of the submodule. According to [19], taking into consideration N submodules in one arm, the ripple voltages v uj,rip (t) and v lj,rip (t) of the upper and lower arms are given by where N is the number of submodules of one arm; M is the modulation index as in (8); and C is the capacitance of the submodule capacitor.

C. Initial Circulating Current
The initial circulating current i j,cir (0 + ) in leg j ∈ {a, b, c} is derived for three cases depending on the arm conducting states of the previous stage. In the first case, both upper and lower arms of leg j are conductive in the previous stage, that is ς uj (0 − ) = 1 and ς lj (0 − ) = 1. The initial value i j,cir (0 + ) is equal to the circulating current i j,cir (0 − ) at the end of the previous stage since the circulating current continues to flow in the leg and the DC link. The circulating current i j,cir (0 − ) is weighted by 2ς uj (0 − )ς lj (0 − )/(ς uj (0 − )+ς lj (0 − )). This weighting factor is equal to 1 when both the upper and lower arms of one leg are conductive in the previous stage, and it is equal to 0 when one of the upper and lower arms is non-conductive.
In the second case, just the upper arm in leg j is conductive in the previous stage, that is ς uj (0 − ) = 1 and ς lj (0 − ) = 0. The upper arm current at the end of that previous stage is given by i sj (0 − ). At the beginning of the present stage, according to (38), the upper arm current is given by i sj (0 − )/2+i j,cir (0 + ) when both the upper and lower arms in leg j are conductive. The arm currents cannot change suddenly because of the arm inductors. As such, the upper arm current at the beginning of the present stage is the same as at the end of the previous stage, that is i sj (0 − )/2+i j,cir (0 + ) = i sj (0 − ). The initial value i j,cir (0 + ) is then obtained as i sj (0 − )/2. The term i sj (0 − )/2 is then weighted by ς uj (0 − )(ς uj (0 − )−ς lj (0 − )), which is equal to 1 only in this case.
In the third case, only the lower arm in leg j is conductive. Similar to the second case, the initial value is obtained by weighting −i sj (0 − )/2 by ς lj (0 − )(ς lj (0 − )−ς uj (0 − )). The weighting factor is equal to 1 only in this case.

D. Maximum Voltage of Inserted Capacitors of one Arm
To obtain the maximum circulating current in (42), the maximum value of the total voltage v j,leg of the inserted capacitors of one arm is calculated. Referring to v a,leg in (21), the submodule state σ ea is equal to 1 according to Table I. The total voltage v a,leg of inserted capacitors in the leg a is rearranged as v a,leg = v dc,pre − NMÎ s 8ω s C sinϕ− 3NMÎ s 16ω s C sinϕ cos(2ω s t 0 ) − NM 2 i dc,pre 12ω s C − 3NMÎ s 16ω s C cosϕ sin(2ω s t 0 ) .
(52) The term (v dc,pre − NMÎ s 8ω s C sinϕ) is constant and independent of the time t 0 of fault occurrence. The remaining two terms of v a,leg rely on the random time t 0 . Focusing on the most severe condition, the maximum value of the sum of those cosine and sine terms is obtained as the root sum square of their amplitudes. Thus, the maximum value of the total voltage of the inserted capacitors of one arm is obtained as given by v leg,bs in (43).