L- and X-Band Dual-Frequency Synthesizer Utilizing Lithium Niobate RF-MEMS and Open-Loop Frequency Dividers

This article presents an 8.6-GHz oscillator utilizing the third-order antisymmetric overtone (<inline-formula> <tex-math notation="LaTeX">${A}_{{3}}$ </tex-math></inline-formula>) in a lithium niobate (LiNbO<sub>3</sub>) radio frequency microelectromechanical systems (RF-MEMS) resonator. The oscillator consists of an acoustic resonator in a closed loop with cascaded RF tuned amplifiers (TAs) built on Taiwan Semiconductor Manufacturing Company (TSMC) RF general purpose (GP) 65-nm complementary metal-oxide semiconductor (CMOS). The TAs bandpass response, set by on-chip inductors, satisfies Barkhausen’s oscillation conditions for <inline-formula> <tex-math notation="LaTeX">${A}_{{3}}$ </tex-math></inline-formula> while suppressing the fundamental and higher order resonances. Two circuit variations are implemented. The first is an 8.6-GHz standalone oscillator with a source-follower buffer for direct 50-<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula>-based measurements. The second is an oscillator-divider chain using an on-chip three-stage divide-by-two frequency divider for a ~1.1-GHz output. The standalone oscillator achieves a measured phase noise of −56, −113, and −135 dBc/Hz at 1 kHz, 100 kHz, and 1 MHz offsets from an 8.6-GHz output while consuming 10.2 mW of dc power. The oscillator also attains a figure-of-merit of 201.6 dB at 100-kHz offset, surpassing the state-of-the-art (SoA) oscillators-based electromagnetic (EM) and RF-MEMS. The oscillator-divider chain produces a phase noise of −69.4 and −147 dBc/Hz at 1 kHz and 1 MHz offsets from a 1075-MHz output while consuming 12 mW of dc power. Its phase noise performance also surpasses the SoA <inline-formula> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula>-band phase-locked loops (PLLs). With further optimization, this work can enable low-power multistandard wireless transceivers featuring high speed, high sensitivity, and high selectivity in small-form factors.

To achieve all the above, the heartbeat of a transceiver, namely the frequency synthesizer, must be revolutionized on architecture, circuit, and device levels. Otherwise, its noise directly adds to the transceiver noise figure and worsens the sensitivity, while any spurs considerably exacerbate the selectivity. Unfortunately, the lack of high-performance miniature resonators that can enable signal generation with minimal phase noise and power consumption has made it challenging to reduce phase noise for 5G chip-scale synthesizers beyond 6 GHz.
State-of-the-art (SoA) microwave oscillators are based on on-chip LC [1], microstrip [2], active [3], and dielectric resonators (DRs) [4]. On-chip LC tanks are compact but lossy, hence offering a low-cost but low-performance solution. Their low-quality factor (Q) at microwave frequencies translates to poor phase noise and high-power consumption. Quarter wavelength electromagnetic (EM) resonators have footprints on the order of 9 mm for an 8-GHz resonance, making them too bulky for handsets. Dielectric-resonator oscillators (DROs) offer superior phase noise performance, but they are bulky and consume a large amount of power.
With access to the above microwave resonators, the next challenge is to design the oscillator or the frequency synthesizer for generating different carrier frequencies.
The conventional frequency synthesis has been relying on a This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see ht. tps://creativecommons.org/licenses/by/4.0/ power-hungry phase-locked loop (PLL) referenced to a bulky high Q crystal oscillator (XO). XOs are hardly tunable and generate only low frequencies (<120 MHz), thus necessitating a PLL as a tunable frequency multiplier and leading to a larger footprint, higher power, more spurs, and greater cost [19]. To overcome these shortcomings, we develop a direct frequency synthesizer based on integrating an X-band LiNbO 3 RF-MEMS oscillator with complementary metaloxide semiconductor (CMOS) open-loop frequency dividers. Instead of generating the local oscillator (LO) frequencies from a low-frequency source and "bubble up" through a PLL, our work creates a low-power microwave low-noise source and then "trickle-down" to an LO frequency range from X to L bands via the frequency division. Our approach has the following vital benefits: 1) lower-power consumption; 2) a smaller footprint when compared to off-chip XOs/PLLs; 3) RF carriers with lower-phase noise/jitter for better receiver sensitivity; 4) spurs-free phase noise (unlike PLL) for enhancing receiver selectivity; and 5) a faster response and lower-energy dissipation from removing the overhead for XO startup or a PLL locked to an XO.
To this end, this article presents an X-band oscillator utilizing a third antisymmetric overtone ( A 3 ) in a LiNbO 3 RF-MEMS resonator and 65-nm CMOS. Two circuit variations have been realized. The first is an 8.6-GHz standalone oscillator with a source-follower buffer for direct 50--based measurements. The second is an oscillator-divider chain using on-chip frequency dividers for a 1075-MHz output. The standalone oscillator achieves a measured phase noise of −113 dBc/Hz at 100-kHz offset from an 8.6-GHz output while consuming 10.2 mW of dc power. Hence, surpassing the SoA X-band EM oscillators [1]- [4], RF-MEMS oscillators above 5 GHz [15], [20]- [23], and X-band PLLs [24]- [27]. The oscillator-divider chain is characterized by a phase noise of −147 dBc/Hz at 1-MHz offset from a 1075-MHz output while consuming 12 mW of dc power. Its noise performance also surpasses the SoA L-band PLLs [28], [29]. This study can enable low-power wireless transceivers with high speed, high sensitivity, and high selectivity in small-form factors with additional optimization.
The rest of this article is organized as follows. Section II reports on the design and measurements of the antisymmetric mode LiNbO 3 MEMS resonators employed to implement the oscillators in this work. Section III then focuses on the design, implementation, and measurement results of the 8.6-GHz oscillator. Section IV explains the design and the implementation of the oscillator-divider chain and reports the measurement results at 1.1 GHz. Finally, Section V compares the results with prior arts and concludes this article.

A. Overview
Antisymmetric Lamb-wave modes (A-modes) are characterized by their antisymmetric vibrational nature about the median plane of the plate. These modes have equal vertical but opposite longitudinal displacement components on the opposite sides of the median plane. The theory defining the resonant frequencies for the excited odd modes can be found in [12]. The resonance of an A-mode resonator is primarily set by the thickness of the LiNbO 3 film (T LN ) and the mode order (m). A smaller thickness would translate to a higher-fundamental frequency; however, this needs careful fabrication and a sophisticated deposition method for thin films to maintain high Q. Empirically, thinner films display worse crystallinity than thicker ones causing degradation in Q. Thinner films are also more susceptible to any fabrication-induced nonuniformity, causing meager yield and uncertainties in setting the center frequency precisely. The overmoding approach helps in achieving higher-resonant frequencies without thinning down the resonator and adding fabrication complexity. It also provides better linearity and power handling due to the larger volume of the device structure.
A high FoM RES is crucial for overmode resonances scaling toward microwave frequencies, as shown in Section II-B [12]. Hence, for a resonator using a 650-nm thick Z-cut LiNbO 3 film, λ l = 12 μm and m of 3, A 3 resonance rises beyond 6 GHz, which is desired for investigating microwave acoustic oscillators.
The resonator comprised of a three-electrode transducer on top of a mechanically suspended Z-cut LiNbO 3 thin-film is shown in Fig. 1(a) and (b). The electrodes connected to signal and ground induce lateral electric fields in the piezoelectric film, hence exciting the resonator into odd-order antisymmetric vibrations. Two identical resonators (A and B) were fabricated, with the dimensions given in the inset of Fig. 1, using a process described in [12]. A 180 nm of copper (Cu) is sputtered and lifted-off as top electrodes. Cu probing pads of 60 × 62 μm 2 are electroplated to 3-μm thickness with a 200-μm pitch to reduce the parasitics between the pads.

B. Resonator Measurements
Resonators A and B were measured and characterized using a Keysight N5230A PNA-L network analyzer. A thru-reflect-line (TRL) calibration is done in measurements using on-wafer standards. A multiresonance modified Butterworth-Van Dyke (MBVD) model shown in Fig. 1(c) is used to interpret the measured admittances of resonators A and B shown in Fig. 1(d) and (e), respectively. The MBVD model includes an additional series inductor (L s ) and a resistor (R s ) to model the nonnegligible inductance and the surface resistance of the electrodes at high frequencies, respectively. It also incorporates a capacitor of 7 fF and a resistor (R f ) to model the feedthrough capacitance (C f ) and the resistive substrate loss, respectively. The resonator also has a static capacitance of 7.5 fF from the interdigitated transducer (C o ) which is set by the size of the resonator. The loaded quality factor (Q l ) for each resonance is measured using the 3-dB bandwidth method, while the mechanical quality factor (Q m ) is extracted via the MBVD model by excluding the electrical loss. C f is not de-embedded for catching all the parasitic effects associated with the resonator. C f is almost equal to C o , and hence it is important to be included for accurate oscillator simulations and measurements. k 2 t for each resonance is extracted, considering all the device parasitics. The first five odd-order modes, namely A 1 , A 3 , A 5 , A 7 , and A 9 with resonances at 2.9, 8.6, 14.3, 20, and 25.7 GHz, are characterized. Key measured and extracted parameters, including Q l , Q m , and k 2 t , are shown in Fig. 1(d) and (e). For resonator A, Q l and Q m are 384 and 424 for A 3 , 12 and 300 for A 9 , respectively. For these modes, Q m varies from 1.1Q l at 8.6 GHz to 25Q l at 25.7 GHz, indicating that electrical loss mitigation is crucial at microwave and mm-wave frequencies.
While Q l · f product decreases with the frequency, Q m · f product increases with the frequency. As investigated in [30], higher order A-modes are better confined between electrodes due to the increasingly larger dispersion mismatch between metalized and un-metalized regions for higher order modes. This feature leads to less acoustic damping loss from the electrodes and less energy loss to the supporting substrate for the higher order modes. Hence, a higher-order mode displays higher Q m · f . Further investigation is needed to understand the dissipation mechanisms quantitatively. k 2 t decreases from 6.9% for A 1 to 0.98% for A 9 with a value of 2.2% for A 3 . The reason behind the degradation of k 2 t with an increasing mode order can be found in [12]. Higher-FoM RES resonances translate to a larger phase transition from capacitive to inductive regions which is preferred for stable oscillations. As the FoM RES degrade with the frequency, the phase transition becomes far from ideal (180 • ). Fig. 1(f) shows that modes A 5 -A 13 are capacitive as their phases do not cross the 0 • needed at resonance. To excite these higher order modes, extra inductors might be required to be added either in series or in parallel to the resonator hurting its Q. Resonator B has a very similar admittance to resonator A. A 3 of resonator B is characterized by a Q l of 370, a k 2 t of 2.1%, and a FoM RES of 7.7 at 8.6 GHz. Both resonators have an insertion loss of around 10 dB at 8.6 GHz, as shown in Fig. 1(g). This value defines the minimum gain required by a 50-matched oscillator to excite A 3 .
The series resonant frequency of the tank-the acoustic part of the resonator plus the reactive parasitic elements-(SRF RES ) can be deduced from the MBVD model. Accounting for L s , SRF RES is around 66 GHz for our device. This SRF value was not captured by our vector network analyzer (VNA) with an upper-frequency limit of 40 GHz. Careful codesign of the resonator, circuit, and integration solutions at microwave frequencies is required if a larger resonator is adopted for a smaller R m . For example, the SRF decreases to 20 GHz for a device with R m of 20 at A 3 and C o of 75 fF. More studies are required to fully understand the effect of the resonator size on microwave and mm-wave oscillator performance, including its power consumption, phase noise, and tuning range.

III. X-BAND OSCILLATOR
In this section, we introduce the X-band oscillator built on Taiwan Semiconductor Manufacturing Company (TSMC) RF general purpose (GP) 65-nm CMOS and derive circuit parameters for meeting Barkhausen's conditions. The oscillator is designed to excite A 3 of resonator A at 8.6 GHz. Phase noise measurements of the LiNbO 3 RF-MEMS oscillator are presented at the end of this section.

A. Architecture
The oscillator consists of an amplifier connected to an RF-MEMS resonator in a positive feedback loop, as shown in Fig. 2(a). The bandpass transfer function of the amplifier allows excitation of A 3 while suppressing A 1 and other higher order tones. The envisioned amplifier can be realized as an inductively loaded n-type metal-oxide semiconductor (NMOS) common source (CS) transistor. Connecting the resonator between the gate and drain creates a modified Pierce oscillator, as shown in Fig. 2(b).
Alignment of the gain peak frequency with A 3 , as shown in Fig. 3 (the dashed-line curves), serves to satisfy Barkhausen's gain condition with minimal power consumption. However, the phase condition is not met by such alignment. The amplifier phase at the peak frequency is around −180 • , as seen in Fig. 3(a) and the resonator phase at resonance is 0 • , resulting in a loop phase of −180 • . Placing the CS gain peak at a frequency between A 1 and A 3 satisfies both conditions, permitting oscillation at A 3 . Unfortunately, this solution would increase the power consumption due to the lower loop gain (LG) for A 3 , as the solid-line curves shown in Fig. 3(b). The gain peak frequency depends mainly on the inductor L and the loading capacitor C out . C in does not change the peak frequency but affects the LG.
The loading inductor has a set of target metrics, such as Q, inductance L, and the self-resonant frequency (SRF IND ). An inductor designed for a large Q at a frequency between A 1 and A 3 translates to the design for a small L and a large C out . Hence, lower LG at all frequencies. A high Q inductor provides a narrower bandpass response, thus producing a higher-gain suppression of the unwanted tones. For A 3 to be minimally affected, the high Q gain peak should be close to the A 3 frequency. A larger L and a smaller C out lead to lower Q, wider band response, higher LG at all frequencies, and a smaller gain suppression of the unwanted tones. With a lower Q inductor, the design is relaxed in terms of the precise  frequency of the gain peak as long as it is between A 1 and A 3 . Simulations anticipating two different sets of L and C out are shown in Fig 4. The modified Pierce LG response is shown in Figs. 3 and 4. It satisfies the oscillation conditions with a small gain and phase margins. Considering the fabrication, supply voltage, and temperature variations, in addition to post-layout parasitics, the single transistor oscillator would be unpractical. Cascading amplifiers are adopted to have more control over the LG response, such as achieving a wide range of gain and phase margins. The second stage of inductively loaded CS would satisfy the oscillation conditions for A 1 and the inductor gains peak frequencies while suppressing the targeted mode.
Three inverting stages are adopted for our oscillator to excite A 3 . The first and second stages are inductively loaded NMOS CS tuned amplifiers (TAs). The third is a wideband resistive loaded NMOS CS stage that can operate as an amplifier or an attenuator by varying the gate voltage. The last stage controls the voltage swing available at the resonator port, ensuring the linear operation of the resonator. All stages are ac coupled independently to provide the needed bias voltages for The inductance values are chosen for a gain peak at 5.7 GHz, a frequency between A 1 (2.9 GHz) and A 3 (8.6 GHz). This bandpass response excites A 3 and suppresses A 1 and higher order resonances. A low-power source-follower stage is used for 50--based measurements. The oscillator schematic is shown in Fig. 5.

B. Small-Signal Circuit Analysis
The circuit parameters for meeting Barkhausen's conditions are derived for fully understanding the oscillator. The process can identify the minimum dc power to start an oscillation and the exact frequency of oscillation. To this end, the oscillator loop is divided into four segments, as shown in Fig. 6, and the transfer function of each segment is analyzed. The loop can be divided at the drain node of M 3 shown in Fig. 5. The loading is represented by adding R load resistor in series to the resonator, as shown in Fig. 6. The LG can be expressed as where A v mems A v1 , A v2 , and A v3 are given below where R load is the loading resistance after breaking the loop. g m1 , g m2 , and g m3 are the transconductances of M 1 , M 2 , and M 3 , respectively. c gd1 , c gd2 , and c gd3 are the gate-drain capacitances of M 1 , M 2 , and M 3 , respectively. r out1 , r out2 , and r out3 are the output resistances of M 1 , M 2 , and M 3 , respectively. c ds1 , c ds2 , and c ds3 are the drain-source capacitances of M 1 , M 2 , and M 3 , respectively. R L is the loading resistance of the third stage. z ind1 and z ind2 are the input impedances of L 1 and L 2 , respectively, and are given as where L ind is the self-inductance from the spiral metallization. R ind is the ohmic loss from the finite conductance of the inductor metal. C ind is the capacitance due to spiral inductor metals overlap. C ox is the capacitance from the inductor metal to the substrate. R sub is the inductor ohmic losses due to eddy currents. C sub is a fitting parameter. The resonator input impedance z m is given as y in , y in2 , and y in3 are the input admittances of the first, second, and third stage, respectively, and are given as where R B1 , R B2 , and R B3 are the gate biasing resistances of M 1 , M 2 , and M 3 , respectively. C gs1 , C gs2 , and C gs3 are the gate-source capacitances of M 1 , M 2 , and M 3 , respectively. y out , y out2 , and y out1 are the output admittances of the third, second, and first stage, respectively, and are given as The interstage coupling capacitances are designed to be large enough from affecting the signal transmission at 8.6 GHz. Hence, they are neglected in the above analysis. By solving for abs(LG) = 1 (or 0 dB), the minimal power consumption for starting oscillations is estimated. Moreover, Fig. 6. Small-signal model of the oscillator core. Fig. 7. Circuit-simulated and equation-predicted LG for the oscillator. Amplifiers parameters used in these simulations: g m1 = 7.45 mS, g m2 = 16 mS, g m3 = 9.6 mS, r out1 = 4.4 kΩ, r out2 = 1.048 kΩ, r out3 = 128 Ω, C gs1 = 32 fF, C gs2 = 15 fF, C gs3 = 10 fF, C gd1 = 4.2 fF, C gd2 = 4 fF, C gd3 = 10 fF, C ds1 = 5 fF, C ds2 = 11 fF, C ds3 = 14 fF, R B1 = 10 kΩ, R B2 = R B3 = 2 kΩ, R L = 400 Ω, L ind1 = L ind2 = 6.35 nH.

C. Design for Phase Noise
The close-to-carrier noise adds directly to the system noise figure, while the far-from-carrier noise weakens the capability of a receiver to attenuate undesired adjacent channel signals. Both should be reduced in a sophisticated design.
From the resonator standpoint, maximizing power dissipation in the motional branch (P m = R m I 2 m ) of the resonator without exiting the linear regime (larger P m reduces farfrom-carrier phase noise) produces a better far-from-carrier noise. This can be guaranteed if most of the current passes through the motional arm at resonance (R m ) rather than the static arm (C o ). However, the oscillator should consume low power for battery-powered mobile applications, leading to the well-known tradeoff between phase noise and power consumption. Resonators with a smaller R m (thus, a larger resonator if FoM RES is fixed [16]) are preferable for lower far-from-carrier noise. Also, doubling Q m translates ideally to a lower-6-dB thermal phase noise.
The oscillator bias points, bias circuit design, and transistor flicker noise are all significant contributors to flicker noise. The amplifier should provide enough LG to satisfy Barkhausen's conditions only for A 3 while balancing noise performance and power consumption. To this end, M1, M2, and M3 have lengths of 240, 90, and 70 nm to reduce the impact of flicker noise. Bias voltages and transistor widths are optimized for both flicker and thermal noises with transconductance values given in Fig. 7. The dc currents in M1, M2, M3, and the buffer are 2, 3.2, 2, and 3 mA, respectively, from a 1-V supply. L 1 and L 2 minimally affect resonator Q l since their center frequencies are far from 8.6 GHz. Smaller loading resistance for M3 (R L ) translates to a better thermal phase noise yet more current consumption. Harmonic balance simulations show that M3 contributes to the noise at 1-kHz offset by 41%, M1 by 35%, and M2 by 20%. For the 1-MHz offset, the noise is dominated by R m with 24%, M1 with 21%, and M3 with 5% of the total noise.

D. Integration Effects
Figs. 8 and 9 show post-layout stability simulations for the oscillator without and with wire-bonds effects, respectively. A parametric analysis of the impact of the wire-bond length on the oscillator LG was done using the wire-bond model shown in the inset of Fig. 9(a). Apart from the wire inductances, the model includes three additional capacitances to the ground, C D that captures the distributed capacitances effect over the wire length, and the bonding pads from the MEMS (C MEMS_pad ) and CMOS dies (C CMOS_pad ). C MEMS_pad is captured in the standalone resonator measurements,  while the C CMOS_pad is simulated in the CMOS circuitry. Wire-bonds Q of 30 is assumed in the simulations with different lengths. Fig. 9(a) shows the effect of varying L WB on the LG, while Fig. 9(b) shows the impact of varying C D on the LG. Integration parasitics did not affect the parallel resonant frequency ( f p ) and only slightly lowered the series resonance frequency ( f s ). Simulations showed that wire-bonds   barely load the resonator, as long as the wire inductance gain peak happens far from 8.6 GHz. Phase noise can be recovered by increasing the gate voltage of M1, hence increasing the power consumption. Simulations showed an increase of less than 0.5 mW is needed for the 3-nH wire-bond case to retain the noise.
This parametric study shows that the 8.6-GHz oscillations are resilient to wide variations in wire-bond length.   Resonators are placed close to the edge of the MEMS chip to reduce the wire-bond lengths.

E. X-Band Measurements
The TSMC RF GP 65-nm CMOS chip (2 mm × 1 mm) is integrated with the MEMS chip (1.5 cm × 0.5 cm) on a glass substrate via wire bonding. The CMOS circuitry occupying an area of 700 μm × 625 μm is integrated with resonator A as shown in Fig. 10. The oscillator is tested on a probe station where the output is sensed using a 100-μm pitch GSG probe. dc probes with decoupling capacitors are used to deliver the transistor bias voltages. Probing was planned as the measurement method in the design stage to avoid complications from parasitic inductances added to L 1 and L 2 . Phase  Fig. 11. The oscillator achieves a measured phase noise of −56, −113, and −135 dBc/Hz at 1 kHz, 100 kHz, and 1 MHz offsets from an 8.6-GHz carrier while consuming 10.2 mW of dc power. From Fig. 11, Leeson frequency can be estimated to be around 12 MHz, suggesting a measured loaded Q of 358. This value is lower than the reported value in Fig. 1 due to the integration and circuit loading effects.

IV. L-BAND OUTPUT
The X-band oscillator wire-bonded to resonator B is followed by a single-ended-to-differential output stage for conditioning the signals before entering the frequency divider. The inputs to the frequency dividers can be level-shifted through the V CM input shown in Fig. 12(a). The frequency dividers used are simple current mode logic (CML) dividers that operate with moderate input and output swings and very high speeds in submicrometer CMOS [31]. A divideby-eight circuitry is needed to convert the 8.6-GHz RF-MEMS output to 1.1-GHz output. Hence, division-by-eight is achieved through three stages of divide-by-two circuitry. As shown in Fig. 12(b), the divide-by-two circuit is created by placing two D-latches in a negative feedback loop.
The frequency divider derives its speed from that a differential pair can be quickly enabled and disabled through its tail current source. The design has several metrics, such as the clocking speed that halves after each division, the power budget, and the phase noise. The close-in phase noise of the 1.1-GHz output is limited by the flicker noise generated by the 8.6-GHz oscillator transistors. In contrast, the far-out noise is limited by the last divider stage and the CMOS inverters following it. The total dc power consumption of the L-band circuitry is 12 mW, where the oscillator consumes 6.9 mW and the dividers consume 5.1 mW. In the current chip, the three divider cells are a replica. Power consumed in the divider can be greatly reduced by at least halving the power of each following stage as the clocking speed halves.
Simulations show that the oscillator-divider interface realized through the squarer (buffer inverters following the oscillator) and the single-to-differential circuitry are noisier than the first two high-speed divider stages. This signal preconditioning is crucial for a stable division. The far-from-carrier noise is limited by the last divider stage (lowest speed) and the following CMOS inverters. A noiseless divide-by-two circuit can enhance the phase noise by 6 dB. With a noiseless divide-by-eight, the noise at 1-kHz offset from a 1.1-GHz output should be ideally around −74 dBc/Hz, better than the measured value by 4.7 dB (extra noise from the three-stage dividers and oscillator-divider interstage circuitry). Table I shows the noise contribution of the interface circuitry and frequency dividers for the 1.1-GHz output.
The L-band measurement setup is identical to the X-band setup. The die photo of the oscillator-divider chain is shown in Fig. 12(c) with an active area of 600 × 700 μm. The measured L-band phase noise using resonator B is shown in Fig. 13. The synthesizer achieves a phase noise of −69.4 and −147 dBc/Hz at 1 kHz and 1 MHz offsets, respectively, from a 1.07-GHz output.

V. CONCLUSION
In comparison to the X-band oscillators in Tables II and III, the figure-of-merit (FoM OSC ) of our oscillator surpasses those of the SoA EM and RF-MEMS oscillators above 5 GHz. Moreover, the measured oscillation frequency is the highest reported to date for a MEMS oscillator wire-bonded to CMOS. In comparison to the SoA X-band PLLs in Table IV, the reported 8.6-GHz RF-MEMS oscillator surpasses their phase noise and FoM OSC results.
By tuning the inductive loads (L 1 and L 2 ) to smaller values, the same oscillator topology can be used to excite higher order resonances. Moreover, adding a switchable capacitor bank parallel to L 1 /L 2 or using a switchable inductor bank can enable the oscillator to hop among different overtones rather than generate a fixed frequency output. Hence, this approach also allows for a potentially ultrawideband tunable frequency generation.
In comparison to the SoA L-band PLLs in Table V, our synthesizer surpasses their phase noise and FoM OSC results. This proves our claim that a direct frequency synthesizer based on a high Q RF-MEMS oscillator and open-loop dividers can be beneficial over a PLL referenced to a low-frequency stable source.
In comparison to the L-band RF-MEMS oscillators [32]- [38] in Table VI, our synthesizer with two (potentially four) frequency outputs achieves competitive phase noise results at 1-MHz offset from a 1.1-GHz output. To improve the close-in phase noise for L-band and make it more competitive with prior arts, either increasing the resonator Q l or choosing a lower-flicker IC technology for integration (or both) should be considered. A resonator with a Q l of 4000 at 8.6 GHz would ideally result in a phase noise around −95 dBc/Hz at 1-kHz offset from 1.1-GHz output using the same active circuitry. Such higher Q l (11 times fold) would also decrease the resonator motional resistance, leading to better phase noise at 1-MHz offset and lower-power consumption. The higher Q can be potentially achieved by improving the resonator thin-film quality, using metals with lower-mechanical losses for electrodes or SiC or sapphire as a substrate to reduce dielectric loss. For our previous discrete version that uses a similar resonator at the Ku-band [15], increasing the resonator Q l from 270 to 432 (1.6 times) at 12.9 GHz would surpass the −95 dBc/Hz phase noise level at 1-kHz offset from a 1.1-GHz output. Thus, it is more practical to use a lowflicker transistor technology like SiGe rather than improving the resonator Q l solely. Moreover, injection-locked dividers can minimize the power consumption and the phase noise of the high-frequency dividers, despite trading off the form factor. Other topologies for building the core oscillator, such as cross-coupled differential pairs, might be considered to reduce the power consumption further.