A 1.42-mm2 0.45–0.49 THz Monostatic FMCW Radar Transceiver in 90-nm SiGe BiCMOS

Terahertz frequency-modulated continuous-wave (FMCW) radars operating close to and beyond <inline-formula><tex-math notation="LaTeX">$f_{\max}$</tex-math></inline-formula> often use gain-enhancing lenses to improve the signal-to-noise ratio. A compact single-chip transceiver benefits a lot from the alignment of the lens to the single on-chip antenna in a monostatic system. The typically required coupler for monostatic operation adds an insertion loss. The proposed multiply-by-24 frequency multiplier-based FMCW radar transceiver removes the coupler and integrates both the final 0.48-THz doubler and subharmonic downconverter into a single common collector push–push doubler. The common emitter is the only port at 0.48 THz in this monostatic system, feeding the top-metal on-chip patch antenna using a direct via stack. The 1.42-mm<sup>2</sup> monostatic FMCW radar transceiver, manufactured in a 90-nm SiGe bipolar CMOS (BiCMOS) technology with an <inline-formula><tex-math notation="LaTeX">$f_\text{T}$</tex-math></inline-formula>/<inline-formula><tex-math notation="LaTeX">$f_{\max}$</tex-math></inline-formula> of 300/480 GHz consumes 85 mA when connected to a 3.3-V supply. At 0.48 THz, the output power is <inline-formula><tex-math notation="LaTeX">$-$</tex-math></inline-formula>12 dBm and the single-sideband noise figure is measured as 36.3 dB. FMCW radar measurements with operating bandwidths of up to 55 GHz, corresponding to a theoretical range resolution of 2.73 mm are performed using an on-board frequency source of a credit card sized demonstrator.

the number of yearly silicon-based THz publications listed on IEEE Xplore during the past decade [2]. Current research has been able to maximize the f T /f max of CMOS technologies [3] to around 0.3/0.45 THz and SiGe BiCMOS [4] to 0.3/0.5 THz with individual SiGe HBTs achieving f T /f max of 0.505/0.72 THz [5].
Frequency-modulated continuous-wave (FMCW) radar operation at 0.48 THz, close to the f max of current silicon-integrated technologies is limited by the achievable output powers and receiver noise figures. The output signal is typically generated using push-push doublers [6], as power amplifiers are not feasible at frequencies of 0.48 THz. Similarly, the receive mixer [7] operates at a subharmonic local oscillator (LO) frequency where larger driving amplitudes are achievable.
THz radar operation has been recently presented using vector network analyzer (VNA) measurements with the relevant frequency extender modules at 0.85-1.1 THz [8] and at 1.1-1.5 THz [9]. Above 0.4 THz, split-block radars have been realized at 0.58 [10] and 0.675 THz [11] using GaAs Schottky-diode multipliers, with system sizes similar to the VNA extender modules.
Compound semiconductors such as indium phosphide HEMTs are able to achieve power amplification at 1 THz [12] with f T /f max of 0.61/1.5 THz and individual transmitter and receiver circuits are demonstrated at 0.85 THz [13] but lack the integration levels and mass-market opportunities of siliconintegrated technologies. Metamorphic high-electron-mobility transistors with f T /f max exceeding 0.5 and 1 THz, respectively, have enabled separate transmitter and receiver chips intended for radar operation at up to 0.44 THz [14] as well as a bistatic FMCW transceiver reaching 0.423 THz [15].
Methods to improve the transmit and receive performance of silicon-integrated single-chip THz FMCW radar transceivers operating close to f max have included the use of lenses in monostatic radars at 240 GHz [16], 270 GHz [17], and 0.32 THz [18]. Typically, monostatic designs are formed with a coupler before the antenna to achieve receive and transmit separation, which reduces the signal-to-noise ratio (SNR) by 3-5 dB, resulting from 3 dB due to power division and by an additional insertion loss of up to 2 dB. Furthermore, impedance mismatch at the interfaces of the four coupler ports at THz frequencies due to layout parasitics, device model discrepancies, and antenna mismatch can considerably reduce the transmit-receive isolation, limiting acceptable output powers.
A circularly polarized slot antenna is presented in a 270-GHz FMCW radar [17] to reduce the losses associated with the This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ coupler to the insertion losses of the 90 • -hybrids and the antenna feeding network. Lately, several solutions have been proposed for monostatic operation without the use of a coupler, similar to the "blow-through mixer" concept employed in the 77-GHz long range radar [19]. In [20] and [21], a diode-connected transistor is located between the 157-GHz oscillator and the on-chip antenna. Similarly, in [22], a common base buffer stage is placed after the 240-GHz oscillator. In the FMCW frequency-comb radar, operating at up to 0.32 THz [18], the square-law mixer input and final doubler output are connected together to the on-chip antenna. Alternatively, a power-combined on-chip antenna is proposed in [23] with separate transmit and receive ports for a 0.31-THz orbital-angular-momentum wave transceiver.
In this work, a monostatic 0.48-THz FMCW radar transceiver is presented, manufactured in a 90-nm SiGe BiCMOS technology with f T /f max of 300/480 GHz. 0.48 THz was chosen as a design frequency by simply doubling the frequency of the previous ISM-band 240-GHz transceiver's [24] frequency source to remain compatible with the demonstrator platform. Moreover, it is worth mentioning that the atmospheric attenuation demonstrates a local minimum around 0.48 THz [25], relevant for future long-range applications. The proposed 0.48-THz common collector push-push doubler, located at the final stage of the multiply-by-24 frequency multiplier chain also functions as a subharmonic receive mixer, comparable to the combined doubler and subharmonic mixing device demonstrated in a 240-GHz split-block radar using Schottky diodes [26], removing the need for an impedance-sensitive coupler and an additional downconversion mixer circuit. Furthermore, the proposed design only requires a single 0.48-THz connection and is placed directly below the antenna feeding edge. In comparison, four 0.48-THz interfaces are necessary in a coupler-based monostatic system, while at least two 0.48-THz interfaces are used for the previously mentioned state-of-the-art coupler-free solutions.
In Section II, the implemented architecture is discussed, while in Section III, the individual circuits are presented. Section IV illustrates the characterized transceiver transmit and receive performance as well as FMCW radar measurements. Finally, Section V concludes this article.

II. TRANSCEIVER DESIGN: SYSTEM ARCHITECTURE
The radar SNR is given as with transmit power P T , antenna gain G, which is identical in the receive and transmit direction for monostatic systems and assumed equal in bistatic systems, wavelength λ, target radar cross section σ, target distance R, Boltzmann constant k B , temperature T 0 , noise bandwidth B, noise figure F N , and loss L. When doubling the frequency of our previous 240-GHz radar [24] to 0.48-THz operation, from (1) and using the same trihedral corner reflector target and the same B, the overall SNR would remain constant, as the radar cross section is proportional to 1/λ 2 . This assumes that all other parameters, including P T , G, and F N , remain unchanged at 0.48 THz. Typical output powers at 0.48 THz only reach 0 dBm [6] with the cost of extensive power combination of four power-combined quadrature push-push doublers or equivalently −8.5 dBm from a single doubler, considering 6 dB due to four-way power combining, another 3 dB from quadrature operation, and 0.5 dB insertion losses, compared to 7.2 dBm at 240 GHz with a single push-push doubler [27]. Moreover, downconversion mixer noise figures are 33 dB [7] at 0.48 THz, typically 10-15 dB higher than counterparts at 240 GHz [28], [29]. On the other hand, a given on-chip antenna, constrained by a fixed size, frequently implemented as a patch antenna [16], [24] using the metal stack for top-side radiation, will see an increase in gain from the frequency increase from 240 GHz to 0.48 THz. For the aforementioned state-of-the-art transmitter and receiver parameters, the SNR is 20 dB lower at 0.48 THz, compared to 240 GHz, assuming identical G at both frequencies and the same trihedral corner reflector target. This difference increases to 28.5 dB if only a single pushpush doubler is considered at 0.48 THz. Monostatic single-chip transceiver architectures benefit from the alignment of external gain-enhancing lenses to the single common antenna, allowing for significant SNR improvements as demonstrated by the G 2 term in (1). G can be increased by typically 15-20 dB using external lenses as reported at 0.32 THz in a monostatic radar [18] or using separate transmitter and receiver chips [30] and even 35 dB as described in the 240-GHz monostatic radar [16]. The conventional silicon-integrated monostatic FMCW radar architecture, illustrated in Fig. 1(a), involves a coupler to separate the fundamental-frequency transmitter and receiver signals before the common single antenna. This topology will introduce a combined loss of 8 dB, with an expected 3-dB loss due to power division and at least 1 dB of additional loss in both the coupler's transmitter and receiver paths. The coupler requires some additional area and driving the mixer with sufficient LO-amplitude through the coupler may become difficult at 0.48 THz. In this work, a combined subharmonic receiver and doubler device is proposed, consisting of a common collector push-push doubler, as shown in Fig. 1(b). The operating principle is comparable to the conventional fundamental FMCW radar, with the beat frequency f beat given as dependent on the transmitted LO bandwidth B sw , ramp duration T sw , and target distance R. The proposed design effectively shares both the last frequency doubler and the subharmonic downconverter circuit in a single common collector push-push doubler. Both the doubled subharmonic LO signal and the target-reflected radio frequency (RF) signal are present at the common emitter, with the base-emitter junctions of the two transistors performing the mixing process. The summation of the collector currents generated by the differential subharmonic LO signal suppresses the odd-valued LO-mixing terms as well as the subharmonic LO-signal, detailed in the analysis in Section III-D.
To evaluate the individual transceiver architectures, Table I is presented. The bistatic 2-chip solution, as demonstrated in a 0.32-THz FMCW radar [30], benefits from excellent transmitter-receiver isolation, although roughly twice the area and dc power consumption P dc is required. In the circularly polarized system at 270 GHz [17], the losses of around 2 dB are estimated from the insertion losses expected of the 90 •hybrids and the antenna feed network. The losses in a monostatic "blow-through mixer" system are reduced to less than 1 dB at 157 GHz [21] with the additional benefit of removing the coupler, although no measurement of the insertion losses has been performed at higher frequencies. Antenna sharing, implemented by connecting transmitter and a zero dc-power square-law mixer to the same antenna port in [18] or as a power-combined antenna in [23], is a further option for removing the coupler in monostatic designs; however, both still require two interfaces to be matched at 0.48 THz and insertion losses are expected from power-combined antennas. The common base topology from [22] would require a technology offering gain close to 0.48 THz. The proposed design, consisting of a push-push doubler with integrated subharmonic downconversion capability The transceiver consists of an LC balun which interfaces the single-ended external 20-GHz LO signal with the differential 60-GHz frequency tripler. A set of two cascaded bootstrapped Gilbert-cell frequency doublers are employed to achieve a 240-GHz signal. The final block, labeled TRX, consists of the 0.48-THz integrated subharmonic receiver doubler, which directly connects to the on-chip antenna. In this section, the implemented circuits will be described, ordered by ascending frequency. Metal insulator metal (MIM) capacitors C MIM of around 500 fF are used for dc blocking. The input impedance is 50 Ω, whilst the balanced output impedance is chosen as 100 Ω. The inductance L = 563 pH and capacitance C = 113 fF have been calculated using [31]. The simulated S-parameters are presented in Fig. 3(b) for the LC balun. The simulated phase imbalance is approximately 9 • around the intended design frequency of 20 GHz. The spiral inductors with approximately four turns are generated using the Keysight ADS coilsys tool and simulated with the finite element method.    circuit, employed in all proceeding designs, has been placed on either sides of the differential frequency tripler circuit, achieving a highly symmetrical layout. Furthermore, this technique allows for the creation of half-circuits, halving the overall layout effort. Fig. 5(a) shows the simulated frequency behavior of the frequency tripler at the third harmonic with a fundamental input power P in of 0 dBm. A maximum output power P out of around −6 dBm has been simulated at an output frequency f out of 60 GHz. In Fig. 5(b), the simulated input-output power characteristic is depicted for a 20-GHz input.  Fig. 6 introduces the schematic diagram of the 60-to-120-GHz and 120-to-240-GHz frequency doublers. The topology was first described in [32] as a bootstrapped Gilbert cell frequency doubler. Transmission lines TL 2 are quarter wavelength long, resulting in lengths of 312 and 156 μm at the 120-and 240-GHz frequency doublers, respectively. Transistors Q1-Q6 are biased near the maximum f T collector current, at around 8.6 mA. Furthermore, 50-fF interdigitated metal-oxide-metal (MOM) capacitors have been designed to improve the coupling between the collectors of Q1 and Q2 to the bases of Q3, Q6 and Q4, Q5. The use of MOM capacitors located in the bottom four thin-metal layers removes the necessity of traveling up to the MIM capacitor, located between the topmost thick-metal layers, and back down to the transistor, using hard-to-model via stacks. Fig. 7 depicts both the simulated (a) output power of the second harmonic relative to output frequency and (b) the inputoutput power characteristic of the 120-GHz frequency doubler. The 120-GHz frequency doubler is able to reach a 5-dBm output power at an input power as low as −10 dBm, which fits very well with the −6 dBm output power of the preceding 60-GHz frequency tripler. Similarly, in Fig. 7, the simulated (c) output

D. Integrated 0.48-THz Subharmonic Receiver Doubler
The proposed 0.48-THz subharmonic receiver doubler is depicted in Fig. 8. This circuit, consisting of a common collector Fig. 9. Integrated 0.48-THz subharmonic receiver doubler layout demonstrating LO input matching network and direct feeding from emitters of Q1 and Q2 located below the antenna. push-push doubler, as presented in [27] and [33], has been enhanced to also work as a receiver, similar to the stand-alone 44-GHz subharmonic mixer in [34]. The emitters of Q1 and Q2, placed underneath the antenna, form a single direct connection to the 0.48 THz on-chip antenna, reducing the required interconnection at 0.48 THz to a via stack, as illustrated in Fig. 9. The collector current can be represented as where I S is the saturation current, V T ≈ 26 mV at room temperature, and v be (t) is given as with dc base-emitter voltage V be , RF amplitude V RF , RF angular frequency ω RF , LO amplitude V LO , and LO angular frequency ω LO . Thus using the approximation e x ≈ 1 + x for the RF small signal. We now consider that Q1 will be excited by a positive LO signal, while Q2 will be excited by a negative LO signal, when Q1 and  Q2 are driven differentially; thus and From [35, (9.6.34)], it is possible to rewrite the exponential term with the cosine LO-signal as a series of modified Bessel functions of the first kind, Using [35, (9.6.34, 9.6.38) Once the currents i C 1 (t) and i C 2 (t) are summed, the odd-valued LO-terms in the modified Bessel series cancel out and the even terms are doubled. Therefore up to the second order, where the cosine product identity has been employed to rewrite the multiplication of the LO and RF cosine functions. In (10), the desired subharmonic mixing product 2ω LO ± ω RF is visible as well as the suppression of the fundamental LO signal. In Fig. 10(a), the simulated voltage conversion gain (CG) G v and single-sideband noise figure NF SSB are illustrated for subharmonic LO input powers between 0 and 10 dBm. The voltage CG and single-sideband noise figure have been simulated with the output power profile of Fig. 7(c). Between 430 and 500 GHz, G v varies by less than 0.2 dB, with a peak value of −2.2 dB at around 467 GHz. NF SSB varies only by 0.7 dB between 430 and 500 GHz, with a minimum of 22.2 dB at around 430 GHz. The simulated input-referred 1-dB compression point of the receiver occurs at an input RF power of −5 dBm at 0.48 THz. The input referred third-order intercept point was simulated to be around 4.5 dBm at 0.48 THz. Fig. 10(b) demonstrates the simulated 20-to-480-GHz multiplier chain output power relative to output frequency as well as the 480-GHz doubler output power versus the 240-GHz input power. A simulated wideband response of at least −10 dBm output power can be achieved in the range of 465-500 GHz. As the output power is lower than the input-referred 1-dB compression point, reflected signals due to antenna mismatch will not affect the receiver. Simulations reveal that the S 11 of the RF port is below −10 dB from 390 to 560 GHz, achieved using a current matching scheme at the emitters of Q1 and Q2.

E. 0.48-THz on-Chip Antenna
In Fig. 11(a), the metal stack is presented. The patch antenna is formed using the top-most pad layer and uses a medium-thick metal 5 ground plane, as illustrated in Fig. 11(b). The ratio of substrate height to resonant wavelength is doubled compared to previous designs at 240 GHz [24], which directly improves the achievable gain and bandwidth. The dimensions of the proposed parasitic patch antenna are represented in Fig. 11(c). CST Studio Fig. 13. Illustration of (a) 0.48-THz transceiver-receiver gain measurement and (b) 0.48-THz transceiver EIRP measurement with 26-dBi standard gain horn (SGH) antenna. The wire-bonded transceiver, labeled chip, is connected to a R&S SMBV100A external LO source (not drawn).  Suite from Dassault Systèmes is used to create a fully parameterizable antenna cell. A particle swarm optimization has been implemented to determine antenna dimensions of the main and parasitic patches, while keeping the separation at a minimum of 12 μm. The layers below metal 5 are free to be used for other purposes, and, thus, the antenna can effectively share its area with other circuitry. Examples may include simple biasing blocks or small digital or analog circuitry which are able to cope with using the bottom four metal layers only. In this design, the implemented 0.48-THz subharmonic receiver doubler sits exactly below the wider edge of the antenna, as shown in Fig. 9. Fig. 12(a) depicts the simulated input matching and the realized gain G ant frequency dependence of the implemented patch antenna. A −10 dB input matching bandwidth has been simulated between 465 and 490 GHz. The 3-dB realized gain bandwidth is approximately from 457 to 489 GHz, with a peak realized gain of 5.4 dBi at 477 GHz. In Fig. 12(b) and (c), the simulated E-plane and H-plane of the antenna realized gain is depicted for a frequency of 0.48 THz.

IV. MEASUREMENT RESULTS
In the first part, over-the-air measurements of the 0.48-THz transceiver chip, obtained using an optical bench setup, are presented. In the second part, the 0.48-THz transceiver is applied in an FMCW radar measurement.

A. Transceiver Characterization
A diagram of the measurement procedure is shown in Fig. 13. First, one of the R&S ZC500 frequency converters is characterized using an Erickson PM4 for output power over frequency. A R&S ZVT-20 is used to generate the RF signal for the converter. In the second step, the second R&S ZC500 frequency converter is characterized for receiver CG using the aforementioned characterized converter as the RF input. An Agilent E8257D is utilized as the LO signal for the R&S ZC500 frequency converter in receiver mode with the IF output connected to the R&S FSW-85 signal analyzer. In Fig. 13(a), the measurement setup is demonstrated for receiver gain characterization of the transceiver chip, using the characterized converter as a transmitter. Finally, in Fig. 13(b), it is possible to observe the effective isotropic radiated power (EIRP) characterization setup of the transceiver chip using the characterized converter as a receiver. For E-plane and H-plane measurements of the EIRP and receiver CG, the transceiver is mounted on a turntable.
The measured and simulated EIRP and receiver gain G RX are depicted over frequency in Fig. 14(a) and (b), respectively. In Fig. 15(a) and (c), the measured and simulated E-plane and H-plane of the EIRP are illustrated, while in Fig. 15(b) and (d), the measured and simulated E-plane and H-plane of the receiver gain are shown. Fig. 16(a) illustrates the harmonic content close to the 480-GHz main carrier. At 440 GHz, the measurement indicates a 10-dB higher harmonic content. In a similar method to Fig. 13(a) and using a R&S ZC330 as the source, the CG at 240 GHz was measured to be 35 dB below the CG at 480 GHz, without lens. Additionally, the radiated fundamental 240-GHz signal was measured using a RPG ZRX330 in a similar setup to Fig. 13(b), revealing an EIRP of −45 dBm without lens, 37 dB below the 480-GHz signal. Thus, considering both transmitter and receiver, an attenuation of 72 dB is achieved for the unwanted 240-GHz signal relative to the desired 0.48-THz signal. In Fig. 16(b), the measured phase noise translation ΔL was investigated using the EIRP setup from Fig. 13(b). First, the 20-GHz signal from a APSIN26G source was directly connected to the R&S FSW-85. In a second measurement, the downconverted IF signal from the receiving R&S ZC500, transmitted by the transceiver-multiplied APSIN26G 20-GHz input signal, was connected to the R&S FSW-85. ΔL is theoretically given as 20 log 10 (N = 24) = 27.6 dB, compared to the measurement ranging from 24.5 to 30.5 dB between frequency offsets of 1 kHz and 10 MHz, expected from the circumstance of the two-step measurement. The NF SSB and CG peak in Fig. 16(d) has shifted to around 450 GHz, in line with measurements in Fig. 16(c) that demonstrate that the 20-to-240-GHz frequency multiplier peak output power of 2.45 dBm is centered at 222 GHz and the 20to-480-GHz frequency multiplier peak output power, calculated from the measured EIRP and simulated realized antenna gain, is −8.5 dBm at 450 GHz. The measured frequency shift and reduced output power of the 20-to-240-GHz frequency multiplier when compared to simulations in Fig. 7(c) can be used to explain the reduction of up to 5 dB in the measured EIRP and receiver gain in Fig. 14(a) and (b). The limited subharmonic output power driving the combined subharmonic receiver doubler will result in a simulated 3-dB lower CG when the 240-GHz input power is reduced from 6 to 0 dBm, as illustrated in Fig. 10(a). With a measured output power of 0.4 dBm at 240 GHz from Fig. 16(c), a simulated output power of only −16 dBm is expected at 0.48 THz, using Fig. 10(b). A power amplifier at 240 GHz [36] could be included in future designs after the 240-GHz doubler. Similarly, the measurement of Fig. 15 indicates typical deviations of 5 dB, although larger discrepancies of more than 10 dB can be observed between simulation and measurement in

B. FMCW Radar Measurement
The photograph of the wire-bonded 0.48-THz transceiver is shown in Fig. 17(a). The transceiver is attached to an interposer printed circuit board (PCB) of 2.0×2.4 cm 2 , which in turn is connected to the demonstrator front-end PCB with an area of 5.5×8.5 cm 2 , as illustrated in Fig. 17(b). More details on the similar radar demonstrator can be found in our 240-GHz FMCW radar [24]. The FMCW radar measurement is depicted in Fig. 17(c). The radar demonstrator is set up on a linear rail and targets such as a metal plate can be moved. The first FMCW radar measurement in Fig. 18(a) investigates the range resolution using a similar setup to [18]. Averaging is performed to improve the SNR in this measurement, performed without a gain-enhancing lens. Two 2.1-cm trihedral corner reflectors are separated in range by 5.8 mm. Increasing the bandwidth (BW) from 48 to 55 GHz allows the two targets to be distinguished. A 48-GHz bandwidth should in theory result in a range resolution of 3.1 mm. The minimum four-sample Blackman-Harris window used in this measurement is able to suppress the sidelobe leakage of a box-car window at the cost of a 2.25 times wider −6 dB mainlobe full-width [38]. Fig. 18(b) illustrates the measurement of a 16×10 cm 2 metal plate target at 1.37 m, as depicted in Fig. 17(d), with a plano-convex LAT100 lens from Thorlabs, comparable to the setup found in [16] at 240 GHz. An external Keysight M8195A arbitrary waveform generator is used to generate a linear ramp from 18.75 to 20.42 GHz, resulting in a 40-GHz bandwidth with a ramp duration of 1 ms. In this measurement, no averaging is performed and the large metal plate, illuminated by the focused beam, acts like an electrical mirror, simplifying the SNR equation from (1) to a transmitted signal traveling 2R, governed by the Friis transmission equation At 0.48 THz, a noise figure of 36.3 dB, a combined G of 22.2 dBi of the on-chip antenna and lens, P T of −12 dBm, T 0 of 300 K, B of 1 kHz, related to the ramp duration of 1 ms when using a fast Fourier transform-based matched-filter approach, reveals an SNR of around 40 dB, agreeing with the measurement in Fig. 18(b). The range resolution of the measurement in Fig. 18(b) can be determined from the Rayleigh range resolution, as the distance from the peak to the first null [39]. The distance from the peak to the first null is around 8 mm in Fig. 18(b), and considering a widening factor of 2 by the Hanning window used for improved sidelobe suppression compared to the box-car window [38], the estimated range resolution is very close to the theoretical range resolution of 3.75 mm.
In Table II, current state-of-the-art silicon-integrated FMCW radars have been summarized for operation frequencies above 0.3 THz. To the authors' best knowledge, the proposed 0.48-THz monostatic transceiver is the first demonstration of a siliconintegrated FMCW radar at frequencies above 0.4 THz, whilst also offering the lowest chip area and power consumption when compared to silicon-integrated FMCW radar transceivers above 0.3 THz.
V. CONCLUSION A 1.42-mm 2 FMCW radar transceiver operating at 0.48 THz was implemented in a 90-nm SiGe BiCMOS technology with f T /f max of 300/480 GHz. A common collector push-push doubler generates the 0.48-THz signal at the common emitter port as well as performing subharmonic downconversion of the received signal at the same port. A monostatic system is formed, which removes the typically required lossy and impedance variationsensitive coupler before the antenna. The proposed topology, placed below the feeding edge of the on-chip antenna, only requires a single 0.48-THz connection, with the separation minimized to the height of the via stack between the bottom-metal emitters of the 0.48-THz subharmonic receiver doubler and the top-metal antenna patch. The transceiver achieves a current consumption of 85 mA when connected to a 3.3-V supply. FMCW radar measurements are performed and reveal detection of targets such as corner reflectors and metal plates using the on-board frequency source of the credit card sized demonstrator or an external arbitrary waveform generator, respectively, at a bandwidth of up to 55 GHz. This work is an optimal candidate for a future terahertz frequency-comb radar [18] with submillimeter range resolution. The recent demonstration [41] of a power amplifier with more than 6 dBm of output power at 0.3 THz in a SiGe BiCMOS technology with f T /f max of 470/650 GHz will further increase the operating frequency of THz siliconintegrated FMCW transceivers using the proposed topology.