RF Waveguide Pattern Engineering to Mitigate Bonding Surface Nonuniformities in CMOS Compatible Fabrication Processes

Heterogeneously integrating silicon photonic devices and circuits with other optical materials (III/V semiconductors, LiNbO3, and so on) is a promising approach toward bolstering the capabilities of silicon photonics and improving the manufacturability of other photonic platforms. An approach to heterogeneous integration is to directly bond an optical material to the surface oxide of a silicon photonic circuit or device, which requires locally and globally smooth bonding surfaces to facilitate sufficient bonding quality. However, embedded silicon photonic metal structures, such as RF waveguides for high-speed photonic devices and electrical interconnects, can impact the surface topography during planarization, resulting in nonideal bonding surfaces. In this article, we discuss and demonstrate a method of patterning the ground planes of RF waveguides to achieve a more uniform distribution of embedded metal density, in turn, providing more constant planarization rates. This provides a more uniform bonding surface which is a requirement for the high-volume manufacturing of these technologies.


I. INTRODUCTION
S ILICON photonics (SiP) is an enabling technology for dense optical networks which relies on the mature manufacturing environment used to build CMOS electronics. However, the indirect bandgap of silicon makes the fabrication of semiconductor lasers on this platform nontrivial, and the centrosymmetric nature of silicon prohibits its use as a linear electrooptic material. Typically integrated lasers are fabricated using III/V compound semiconductors, and linear modulators are fabricated using noncentrosymmetric materials, such as lithium niobate (LiNbO 3 ), but neither of these platforms has the mature process development SiP features.
An attractive approach to utilizing the benefits of SiP while simultaneously using materials to realize high-performance, high-speed, efficient photonic devices, and systems is heterogeneous integration [1], [2], [3]. This approach offers all the manufacturing benefits of SiP and removes the manufacturing emphasis from other materials by fabricating the optical waveguides, RF waveguides, and high-speed electrical interconnects in the CMOS foundry. In this architecture, the optical waveguides defined in the CMOS foundry must be spatially near the other integrated material in order to allow optical interaction with those materials. Heterogeneous integration can be achieved through the application of adhesives, such as benzocyclobutene (BCB); however, this generally increases the distance between the lithographically formed waveguides and bonded photonic material [4], which can reduce the amount of optical interaction with the bonded materials.
To ensure that the lithographically defined waveguide cores are as close to the integrated material as possible, there should a minimal amount of oxide between the bonded layer and the waveguide strip. For this reason, direct bonding is the preferred method of integration, which relies on van der Waals forces. The minimum distance between these layers is desirable as this forms a more well-defined waveguide and ensures the mode has maximum overlap with the integrated optical material while also remaining guided. For successful and strong oxide bonding (using van der Waals forces), the two surfaces must be smooth (typically having a root mean square (RMS) roughness of less than one nanometer) and globally flat. These requirements ensure that there are no voids in the bond and that large pieces of material can be bonded for large photonic integrated circuits (PICs) or wafer-scale bonding. Minimum material above the SiP waveguides and sufficient global flatness is achieved inside of the CMOS foundry through the implementation of a chemical-mechanical planarization (CMP) step, in which the planarized SiO 2 becomes the bonding surface of the SiP sample.
RF waveguides, such as coplanar waveguides (CPWs) are required for high-speed elements in modulation devices and as electrical interconnects between components. In general, CPWs are highly suitable for integrated high-speed devices because they only require a single-metal layer and are required in order to realize any type of high-speed operation. Typical integrated CPWs consist of two ground planes and a center electrode, as depicted in Fig. 1, and result in very dense metal regions in the final PIC.
After polishing, there should be as little variation in SiO 2 thickness as possible throughout the PIC. It can be difficult to achieve planarity and avoid bowing and dishing when a multi-layer wafer that contains metal electrodes undergoes CMP in preparation for bonding.
In this article, we address the effect of nonuniform planarization during the CMP step [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [38], [39] as it relates the underlying metal pattern density. Aluminum CPW devices are fabricated and characterized using Sandia's SiP process with both solid and patterned ground planes. We show that the implementation of large metal regions in a chip will result in a systematic variation in the thickness of the planarized SiO 2 , which limits the size of the bonding area. We also discuss and implement a mitigation method for this thickness variation by engineering the metal density in our samples. We experimentally show that this has virtually no impact on CPW operation and performance up to 40 GHz and show that this design methodology can be used to improve the global surface uniformity of the bonding surfaces in heterogeneously integrated photonic platforms. These techniques are applicable broadly in both electronics and photonics where  [5] consisting of a diced TFLN sample bonded to a diced SiP chip, (b)crosssectional schematic of the modulation region of the same bonded modulator from [5], and (c) top-down schematic of the modulator. The fabricated device is bonded to a 200-nm x-cut TFLN piece, which has a LiNbO 3 handle wafer. The circular fringes in (a) arise from variation in the polished SiO 2 thickness due to the nonuniform distribution of buried metal structures (CPWs), and the fringes on the bottom left of the TFLN chip in (a) indicate the surfaces are not properly bonded in that region. globally smooth surfaces are required. CPW performance is explored up to 100 GHz in a simulation where a very slight difference in the loss characteristics is observed.

II. EXPERIMENT AND RESULTS
Two CPW designs, which are depicted schematically in Fig. 2, are fabricated using Sandia's CMOS fabrication facilities, whose design parameters are listed in Table I. These CPWs consist of the 0.87-μm-thick aluminum layer with a dc sheet resistance of 42 m /sq. The aluminum layer is fabricated above a 3-μm-thick layer of thermally grown oxide. Both of the CPW designs are fabricated with two  different lengths (0.52 and 1.02 cm) using both a standard, solid ground plane design and a patterned ground plane design. The silicon handle resistivity for the CPWs with solid ground plane designs is specified to be greater than 10 k × cm, while the silicon handle wafer used for the CPWs with patterned ground plane designs is specified to be 450 ×cm-620 ×cm. The resistivity for these wafers is different due to the availability of materials for these experiments. However, simulation results show that the dielectric loss is constant above 100 × cm, making the discrepancy in resistivity inconsequential. The pattered ground plane features "holes," which are 8 μm × 8 μm and have a center-to-center spacing of 10 μm from each other in both directions along the length of the CPWs. The total metal density [or FF, as defined in Fig. 2(c)] of the patterned ground plane samples is 34.92 %, while the standard, solid ground plane samples have a metal density of 40.231 %. As an ad hoc rule, this pattern begins at a distance of at least three times the signal conductor width (w sig ) from the edge of the ground plane nearest the center conductor, such that an integer number of the patterned holes will fit in the total ground plane width. During fabrication, these holes become filled with SiO 2 .  Fig. 4. These data are collected using a 3-D surface characterization instrument (FRT MicroProf 200), which is a routine tool to perform total thickness variation (TTV) measurements. The variations in the SiO 2 thickness in Figs. 3 and 4 are due to varying planarization speeds during CMP. The planarization speed is faster over less dense patterns (i.e., sparse metal) and slower over dense patterns. Again, for the purpose of direct bonding to achieve heterogeneous integration, the final polished SiO 2 surface will be the bonding interface for the final device. Globally smooth surfaces are necessary in order to improve the bonding quality of integrated devices. The fringes seen in Figs. 3(a) and 4(a) are Moirè patterns and arise from sampling errors in the measurement. The fill pattern used in these designs is an array or checkerboard pattern in both the horizontal and vertical direction with a spatial frequency of 10 μm (present in both the solid ground plane and patterned ground plane samples). The maximum resolution in the instrument's camera image is 50 μm, and thus, the Nyquist sampling criterion is not satisfied, creating false spatial frequencies (i.e., aliasing) that manifest as the measurement artifacts in Figs. 3(a) and 4(a). In theory, these artifacts can be removed through image processing, but this removes information from the data and is not implemented in this study. Regardless of the presence of these measurement artifacts, the distribution of thicknesses in Figs. 3(b) and 4(b) shows that not only the distribution of thickness narrows when using the patterned ground planes but also that thickness distribution in the solid ground plane sample is bimodal, while the distribution in the patterned ground plane sample is unimodal. The effect of having thicker polished oxide above the CPWs causes interference fringes under the illumination of visual light, which can be observed as the rings seen in the chip using the solid ground planes [ Fig. 3(c)]. When the patterned ground plane architecture is utilized, the density of metal is much more uniform throughout the entire chip. In contrast with the solid ground planes, the interference fringes visually disappear, demonstrating that the polished oxide thickness is much more uniform across the chip.
The scattering parameters are measured for all devices using a two-port vector network analyzer (VNA). Due to the fact that the solid ground plane devices and the patterned ground plane devices have different substrate resistivities, there will be different charge accumulations at the interface between the SiO 2 and silicon [40], [41], [42]. To remove any loss dependence on this sheet charge, transmission is maximized (i.e., attenuation is minimized) as a function of applied dc voltage at a frequency of 1 GHz before the scattering parameters are measured while biased at the optimal voltage. This ensures that there is no charge accumulation at the SiO 2 /Si interface (i.e., the flat-band voltage) [40], [41]. The flat-band voltage is found here by measuring the minimum propagation loss at 1 GHz as a function of dc bias by using a high-speed bias tee. All measured parameters are in acceptable agreement with each other, indicating that RF performance is not altered when implementing this ground plane patterning.
The propagation loss α and effective index n eff of the guided RF mode on a transmission line of length L is extracted at frequency f from the measured scattering parameters using (1), where c is the speed of light. The characteristic impedance is extracted using (2), where Z ref is the reference impedance and is 50 in this study and in general. These expressions are derived from the relationship between the transmission matrix and scattering matrix for a reciprocal two-port network [43], [44], which is the case for the CPWs here. In other words, the transmission from port 1 to port 2 (S 21 ) is the same as the transmission from port 2 to port 1 (S 12 ), and the reflection into port 1 (S 11 ) is the same as the reflection into port 2 (S 22 ) The loss mechanisms for these CPWs arise from conductive losses and dielectric losses. In theory, the conductive losses are proportional to the square root of the frequency, while dielectric losses are linear with frequency. However, this is overly simplistic and does not accurately describe the experimentally extracted loss because this model does not consider the frequency-dependent nature of other parameters, such as the dielectric permittivity. The dc-dependent losses due to charge accumulation at the SiO 2 /Si interface are a consequence of band bending in the semiconductor when the two materials are joined together. The amount of band bending (and charge accumulation) depends on the doping (resistivity) of the semiconductor. However, during thermal processing of the silicon (e.g., growing thermal oxide), the sheet charge characteristics are altered [40], which makes it appropriate to bias the CPWs such that the bias-dependent loss does not  Table I. contribute to the overall loss in this study in order to compare the effects of the patterned ground plane designs. Another strategy to mitigate this effect is to deposit a thin layer of amorphous silicon between the SiO 2 and Si layers [42], which passivates charges at the interface. The frequency-dependent modal parameters are measured for the CPW 1 and CPW 2 designs using both ground plane architectures and plotted in Figs. 5 and 6 where no appreciable difference in modal characteristic was measured up to 40 GHz between the solid and patterned ground plane architectures. The relatively high attenuation in these devices is attributed to a narrow electrode gap, which can be used in the design of an electrooptic modulator as a method of increasing the modulation efficiency. The slight instability measured above roughly 10 GHz is attributed to imperfections present in the S-parameter measurement calibration. Particularly, the phase in the measurement can be difficult to calibrate accurately, which is required to extract the modal parameters.
The scattering parameters are measured from 50 MHz to 40 GHz using a VNA (Agilent E8364B) at RF powers of −17 dBm at each port. The CPWs are probed using Formfactor GSG Z probes rated for operation up to 40 GHz. A high-speed bias tee (Picosecond Pulse Labs 5542-202) was placed between port 1 of the VNA and the probe in order to apply the dc bias previously mentioned to remove any bias-dependent losses. To calibrate the measurement link, an impedance standard substrate was used which contains calibrated broadband 50-loads, open circuits, and calibrated throughput waveguides. The dc bias was provided using a Keithley 2400 source meter.

III. BONDING RESULTS
To assess the bonding quality, one of the CPW samples was bonded to a diced piece of TFLN, which consists of a  Table I. nominal 200-nm X-cut LiNbO 3 film on top of a 2-μ layer of SiO 2 , all on top of a nominally 400-μm-thick silicon handle wafer. This is in contrast to the bonded TFLN sample in [5] and Fig. 1(a), which feature TFLN atop a LiNbO 3 handle wafer. The size of the TFLN chip is 5 × 11 mm 2 , and the size of the CPW sample is 8.1 × 12.5 mm 2 . The TFLN sample is cleaned using an SC1 clean, and the patterned CPW sample is cleaned with solvents. SC1 is avoided for the CPW sample it contains exposed metal pads, which can become corroded when using an SC1 clean. Following this cleaning step, both samples receive an O 2 plasma activation for 60 s, followed by a final cleaning step (the same SC1/solvent clean for the TFLN/CPW samples, respectively). After preparation, the bond is initiated by pressing the two samples together with a force of 500 N at a temperature of 150 • C for two hours. The sample is then annealed at 350 • for ten hours while being under 500 N of force, translating to an applied pressure 9.09 × 10 6 Pa between the samples being bonded. The second anneal step was implemented to improve bonding quality, as the first bond and anneal did not sufficiently adhere. A description of both bonding steps is included here for completeness. The bonding quality was then assessed by submerging this bonded sample in water and using a confocal scanning acoustic microscopy (CSAM) instrument, whose results are presented in Fig. 7. In Fig. 7, the dark regions indicate successful bonding, and the lighter regions show voids. The boundary of the smaller TFLN sample is seen as the sharp edges of the black rectangle within the light rectangle, which is the CPW sample itself. This result shows that nearly the entire TFLN chip is successfully bonded. Some of the voids here are systematic (i.e., the straight lines in Fig. 7), which correspond to the solid center conductor of the CPWs. Unfortunately, a comparison between the bonding quality when using the patterned ground planes and the solid ground planes cannot be made using CSAM, as the CPW samples with solid ground planes debond when submerged in water, attributed to poorness in the bond quality.
As discussed previously, the surface roughness and large-scale smoothness impact the bonding quality. In general, the samples to be bonded together should be as smooth and flat as possible. It can be seen from Figs. 3 and 4 that patterning the ground plane significantly improves the large-scale surface planarity of the sample. This can also be characterized by using a profilometer, which is presented in Fig. 8. A profilometer stylus is dragged across the long dimension of both the solid and patterned ground plane samples, which reveals topography toward the center of the chips, which is where the CPW array is located. Patterning the ground plane improves the magnitude of this topography by nearly a factor of four. Ideally, the entire chip surface should be completely flat, indicating that further optimization of the metal patterning can be pursued to further improve topography. Surface roughness on a small scale is measured using atomic force microscopy (AFM) and is also presented in Fig. 8. The AFM measurement is performed in a 1-μm 2 area in the bonding region above the CPW array. The roughness here is defined as the arithmetic average of the difference between the mean height and measured height and is found to be 2.21 nm for the solid ground plane sample and 2.28 nm for the patterned ground plane sample. The change in metal pattern design is not expected to affect this surface roughness, which is largely determined by the CMP process. Notably, there is not a sharp height difference in the area between the CPW array and the rest of the chip, which is due to the CMP step smoothing such features.
The same surface characterization may be performed on the material that is being bonded to, which, in this case, is TFLN. The same profilometer and AFM measurements are repeated on a representative TFLN sample and presented in Fig. 9. The range of the profilometer is substantially smaller than those in Fig. 8, which is an expected result as no patterning is performed on the TFLN sample. The measurement is, however, quite noisy, which is due to noise in the measurement combined with the small deviations in the surface topology. The roughness is again measured via AFM and found to be 0.208 nm. The TFLN surface is expected to be very smooth due to the fact that it does not experience any patterning.

IV. MODELED EFFECTS OF GROUND PLANE PATTERNING
To explore the effects that patterning the ground plane of CPWs may have on the RF characteristics, 3-D finite-element method (FEM) simulations using EMPro were performed from 0.04 GHz to 100 GHz. Fig. 10 shows the EMPro simulation results of both CPW 1 and CPW 2 with and without the patterning described in Fig. 2 and shows a strong correlation to the measured data in Figs. 5 and 6. Discrepancy between the CPW modal characteristics in the model and experiment is attributed to an imperfect calibration of the VNA prior to the measurement, particularly the phase calibration, which impacts the extracted values of interest. Patterning the ground plane has the largest effect on the RF attenuation of the propagating coplanar mode. The holes in the ground plane have nearly Fig. 9. The profilometer results for a TFLN sample illustrate (a) surface profile and (b) AFM results. The surface roughness is derived from these results and found to be 0.208 nm. no effect on the RF effective index and impedance (with simulated changes <1% from 1 to 100 GHz), as the coplanar mode is primarily confined to the electrode gap between signal and ground planes. Since the hole pattern is at least 3 × w sig μm away from the inner ground plane edge, the electric field weakly interacts with the hole pattern. Although there is no change in the effective index, the propagation loss of the RF mode increases with the introduction of SiO 2 filled holes. This 0.05-1 dB/cm increase in attenuation at high frequencies is due to the surface current flowing along the ground plane being perturbed by the periodic oxide obstructions in the conductor. The propagation loss experienced by a CPW mode is proportional to the surface resistance of the conductors and the integrated surface current density around the conductors [45], [46]. Patterning the ground electrodes with oxide-filled squares alters the resistivity of the electrode, and thus the attenuation. This is evident from looking at the simulated surface current density flowing through the CPW (Fig. 11).
A simulation study was also performed to understand the effect that the fill factor (FF) and the edge factor (EF) have on CPW performance. F F is defined as the ratio of metal  Table I. in a unit cell to the total unit cell area [see Fig. 2(c)], while E F is defined as the ratio of the width of the solid section of the ground plane to the width of the CPW signal trace width [see Fig. 2(b)]. The parameter FF for the devices fabricated in this study is 36%, and the parameter EF is 3.42 and 3.05, respectively, for CPW 1 and CPW 2. Fig. 12 shows the simulated RF index, loss, and impedance of CPW 2 as a function of EF with different metal densities. Here, an FF of 100% corresponds to a ground plane with no patterning (i.e., completely solid), whereas an FF of 0% corresponds to a ground electrode that is only EF × w sig μm wide (i.e., the "patterned" region only consists of SiO 2 ). The size of the holes that are patterned into the electrodes has a negligible effect on the RF index and impedance; however, in the limit, as F F goes to zero, the unit cell of the pattern in Fig. 2 is only SiO 2 . This effectively narrows the ground plane from 124.5 μm to EF × w sig μm wide. The narrower ground planes, while generously reducing the metal density of the CPW, also cause variations in the microwave effective index and impedance of the line [ Fig. 12(b) and (c), respectively] which will eventually limit the high-speed performance of the CPWs. Although the effective index and impedance of the mode are minimally affected by the metal reduction, the RF attenuation can increase depending on the EF and FF [ Fig. 12(a)]. If the metal density is heavily reduced (FF < 36%) then the surface current density becomes disrupted by the periodic oxide fill, increasing the attenuation. For the same reason, if the patterning begins closer to the coplanar mode, the loss will increase. This effect is further explained by Fig. 11, which shows a top view of the buried electrode (CPW 2) simulated in EMPro with the ground plane patterned with different EF and FF combinations, overlaid with the simulated surface current through the electrodes (magnitude of which is given in the color bar). By comparing these surface current distributions with the simulated results from Fig. 12, it can be deduced that the attenuation of the CPW mode can be lessened by designing the ground plane pattern with an appropriate EF and FF, such that the pattern does not interact with the well-confined CPW mode. Thus, depending on the metal fill outside of the CPW structure, an appropriate EF can be chosen that mitigates the effect that patterning the ground plane has on attenuating the propagating mode while maintaining a specified required metal density for planarity. 4-μm-thick HDP CVD oxide is deposited on top of the patterned CPWs followed by a CMP step to achieve a nominal 350-nm thick layer of oxide above the metal. A 300-nm-thick film of SiN x is (e) deposited (f) and patterned, followed by the same oxide deposition and (g) CMP step to achieve a nominal 375-nm-thick oxide layer above the nitride film. A second SiN x film is (h) deposited and (i) patterned. (j) Final oxide deposition and CMP step is performed to achieve minimal oxide thickness between this nitride layer and bonding surface. This topmost waveguide forms part of the modulation region of this device, and the bottom waveguide layer is used to reduce optical loss at the air/TFLN interface [5].

V. CONCLUSION
This work has demonstrated an improvement in the uniformity of planarized surfaces through CMP processes when buried electrodes are implemented. This is significant for the heterogeneous integration of photonic materials, particularly for SiP which uses a CMOS-compatible metal encased in SiO 2 . By engineering the metal density of the embedded structures, the local metal density is made to be more uniform throughout the chip layout, reducing systematic thickness variations from the CMP process. Although CMP has been demonstrated to provide local planarity, PICs requiring larger interaction lengths demand global planarity to achieve sufficient bond quality.
We experimentally show that this patterning does not detrimentally affect the performance of RF waveguides using patterned and nonpatterned ground planes, indicating no tradeoff in performance and bond quality at least up to 40 GHz and show that in simulation there is a minimal amount of additional attenuation (less than 1 dB/cm) at 100 GHz when using the patterned ground plane architecture. We also show that the ground plane patterning can be modified without significantly affecting performance, implying that many different patterns may be used to achieve our results. This is an important characteristic when applying these methods to other foundries which may have different requirements for minimum metal densities.
This showcases a capability to improve global thickness uniformity through the engineering of embedded metal structures, which is a necessity for high-speed electrical interconnects and high-speed devices. Improvement in global uniformity of planarized oxide thicknesses can have the effect of improving the yield of heterogeneously integrated optical components as more devices can be manufactured with the same structures because the planarized SiO 2 will be more constant throughout the chip. Therefore the ground plane design methodology discussed in this article can allow more devices to be manufactured with the same performance metrics (i.e., improved yield) through the removal of systematic variations within the bonding surface of the sample prepared in the CMOS foundry. Because this method can only improve the uniformity of optical devices and minimally affects the RF performance of CPWs, we can infer that electrooptic and optoelectronic devices manufactured using the patterned ground plane architecture will have nearly equivalent performance compared with devices built using the solid ground plane designs, albeit with a higher yield.

APPENDIX FABRICATION PROCESS FLOW
The devices described in this article were fabricated following the flow presented in Fig. 13. The starting material is a silicon wafer, with 3 μm of thermally grown oxide on top. The metal layer is deposited and patterned, followed by a high-density plasma deposition (HDP) chemical vapor deposition (CVD) oxide deposition. The thickness of this oxide is nominally 2.4 μm. A CMP step is employed to reach the target oxide thickness above the top of the metal, which in this step is targeted to be 350 nm. The deposition of 2.4 μm thick oxide followed by the CMP step is used throughout device processing. The authors note that the surface topography is not expected to change as the metal thickness changes, predicted by the models described [24], [25], [27], [29], [31], [33], [34], [35], [39]. However, typically the deposited oxide will generally need to be thicker as the metal thickness increases in order to still achieve planarity. A plasma-enhanced CVD (PECVD) silicon nitride layer is deposited and patterned to form optical waveguides, followed by an oxide deposition and CMP step to reach an oxide thickness of 375 nm above the PECVD nitride film. A second PECVD silicon nitride film is deposited and patterned, followed by the same deposition/CMP step to achieve a minimal amount of oxide (<100 nm) between the bonding surface and nitride material.