Cryogenic-Aware Forward Body Biasing in Bulk CMOS

Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in bulk CMOS is proposed, which can operate up to the nominal supply without problematic leakage currents, thanks to the larger diode turn-on voltage at cryogenic temperatures. As a result, traditional circuits, such as pass-gates, can operate down to 4.2 K, and their performance is augmented, e.g., digital circuits speeding up by <inline-formula> <tex-math notation="LaTeX">$1.62\times $ </tex-math></inline-formula> or lowering their energy per transition and energy-delay product by <inline-formula> <tex-math notation="LaTeX">$4.24\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$2.33\times $ </tex-math></inline-formula>, respectively. Unlike back biasing in FD-SOI, here all FBB voltages remain within the supplies, hence enabling on-chip and device-specific biasing. The proposed FBB technique thus represents a valuable design tool for bulk cryo-CMOS circuits.


I. INTRODUCTION
F OR several low-temperature applications, such as quan- tum computing, space exploration, and cryogenic computing, CMOS electronics operating at cryogenic temperatures (cryo-CMOS) have been proposed as an enabling technology [1], [2], [3], [4].The development of the high-performance, low-power circuits required in these applications favors its unrivaled VLSI capability combined with improved device performance at cryogenic temperatures, e.g., the increased carrier mobility [5], the lower thermal noise [6], the steeper subthreshold slope (SS) [5], the reduced metal resistances and the higher quality factor of passives [7].Despite these advantages, the significant increase in threshold voltage V th (up to 180 mV at 4.2 K [8]) constitutes a big obstacle for circuit design, for instance, heavily hindering the increase in drive current induced by the enhanced mobility, and limiting the allowed voltage swing in commonly adopted circuits, such as sample-and-hold [9], [10].Designers can counteract the increased V th using more complex circuits, inevitably costing performance and/or power.To alleviate these setbacks, the MOS channel doping could be optimized for cryogenic operation, thus precluding wide-temperature operation and adding fabrication costs.Adopting an FD-SOI technology in combination with back-biasing to tune the V th can drastically improve cryogenic performance [11].However, in addition to the higher cost of FD-SOI with respect to bulk CMOS, tuning the V th back to its room-temperature value requires biasing the back gate well beyond the process nominal supply due to the low body factor in FD-SOI technologies, e.g., requiring beyond 2 V for the back gate to compensate the V th shift for a body-factor of 0.085 V/V [11], [12], [13].As a consequence, either high-voltage on-chip generators would be required, increasing power consumption and complexity, or the back-bias voltages need to be delivered from off-chip.As an alternative, we propose using cryogenic-aware forward body biasing (FBB) in bulk CMOS.As the body factor in bulk CMOS is significantly larger, the required body bias voltage is lower [14].However, a large body-source voltage could turn on the source-bulk diodes, leading to massive unwanted leakage currents.While this is a known hard limit at room temperature, the diode turn-on voltage increases beyond the supply rails at cryogenic temperatures [15], [16], thus potentially preventing the leakage.Recent work [17] has already shown an improvement in reliability down to 80 K and FBB voltages only up to 0.5 V.However, the proposed technique demonstrates, for the first time, the full potential of FBB for cryogenic low-power and high-performance bulk CMOS designs by presenting its experimental characterization and validation for both devices and circuits.

II. CRYOGENIC-AWARE FBB CHARACTERIZATION
A 40-nm LP triple-well CMOS test chip has been fabricated, comprising both standard-and low-V th (SVT/LVT) transistors, and ring oscillators (ROs) to test the performance of digital circuits.All 384 transistors are connected in parallel and share the Kelvin-connected source and drain connections, but their gates are individually switchable to V g or V s by a thick-oxide switch.They have been characterized with Keysight 2636B SMUs and their threshold is extracted using the maximum g m method at V DS = 50 mV [18].Each RO consists of N = 1025 inverters and an enabling thick-oxide switch in series.Of the 144 ROs, 116 have varying widths and minimum length (40 nm).The others have minimum width (120 nm) and lengths between 45 nm and 120 nm.The oscillators' output frequency is measured with a Rigol DSA815 spectrum analyzer, while simultaneously measuring their supply and body bias currents using the SMUs.The transition time of a single stage t d = 1/(2N f ) is computed from the frequency, and is combined with the total RO power (P = V dd • I ) to obtain the energy per transition (EPT = P • t d ) and energy-delay product (EDP = P • t 2 d ).The 4.2-K data was obtained by submerging the chip into liquid helium inside a dewar using a dipstick.

A. Transistor Static Characteristics
Figure 1a and b show the I ds /V g curves of a single minimum-length NMOS and PMOS device.To improve the readability of Fig. 1, the leakage current of all parallel transistors with V gs = 0 V is subtracted in the plots.As expected and highlighted in Fig. 2a, the V th increases when cooling down.FBB can reduce the 4.2-K V th even below its roomtemperature value, although it is less effective for the PMOS due to its larger V th shift [8].The body-factor, η = ∂ V th /∂ V bs in Fig. 2b, only depends on V bs and the doping level, but it is approximately independent of temperature.A similar invariance was found for longer devices (L = 2µm).This indicates that a relatively high room-temperature body-factor is a good predictor of the suitability of the proposed technique for a given technology.For longer devices, however, the thresholds remain higher (Fig. 1c) due to the reduced DIBL effect and the ratio between the bulk diode leakage and drain current will be larger.The transistor |I ds | leakage at 4.2 K is lower than room temperature (see Fig. 1b and c) due to the steeper SS even for full FBB |V bs | = V dd , i.e., the N-well (P-well) to V ss (V dd ), while the maximum current at V gs = V dd is always higher at 4.2 K thanks to the higher mobility (see Fig. 1a).

B. Pass Gates
Pass gates, i.e., switches consisting of a PMOS and an NMOS in parallel, are problematic at cryogenic temperatures, as they exhibit high resistance around mid-rail due to the steeper SS and higher V th [10].Fig. 1d shows that with FBB, the pass-gate resistance is returned to levels similar to 300 K, thus proving its restored functionality.At 4.2 K, the curves are shifted to the right compared to 300 K, confirming that the NMOS threshold is less affected by cooling than the PMOS.

C. Ring Oscillators
In cryogenic digital circuits, FBB brings the opportunity to significantly reduce the dynamic power by simultaneously reducing both the V th and V dd .In addition, the steep SS  at cryogenic temperature mitigates the leakage induced by this lower V th .A second improvement is the logic speed-up induced by the increased mobility at cryogenic temperature compared to room temperature.While older technologies achieve > 1.6× speed-up when cooled down, the speed-up for modern technologies is limited by the increased V th constraining the drive current [10].FBB should alleviate this limitation, thus bringing back the traditional speed-up.The logic performance is assessed by characterizing a ring oscillator with standard drive-1 (D1) LVT inverters (Fig. 3).For these measurements, we focus mostly on full FBB (|V bs | = V dd ) as this is a very practical case not requiring any additional biasing/supply voltage other than V dd and V ss .However, it is important to note that V dd is now being swept.In Fig. 3a, the RO frequency shows a speed-up of 1.16× when cooling down, which increases to 1.87× when applying full FBB, thus aligning with the expectations based on [10].The plot also clearly shows that FBB lowers the minimum V dd at which the oscillator still works.Figure 3b shows two interesting findings for the power consumed by the ROs.First, a large reduction in static power is induced by the lower leakage at 4.2 K, which significantly increases with FBB.Second, the power consumption with FBB has a step-like increase above V dd = 0.8 V. Since this also corresponds to an increase of the EPT and EDP (Fig. 3c,d), the power increases more than the frequency.This is likely due to the lower V th causing an increase in the inverter short-circuit current when both NMOS and PMOS conduct.Next, Fig. 3c shows that the EPT does not benefit from FBB.This is expected as the EPT is limited by C V 2 dd when neglecting the short-circuit current.FBB does however increase the frequency, causing the minimum EDP in Fig. 3d to lower from 10.1 fJ•ps without FBB to 7.7 fJ•ps with FBB.While this is similar to the results for 28-nm FD-SOI [11], the proposed technique avoids the backbias voltages exceeding 4 V in prior works.An interesting difference appears in Fig. 3d above and below V dd = 0.9 V when applying FBB.Above 0.9 V, FBB increases the EDP, while it lowers it below 0.9 V.This is mainly attributed to the optimal V dd point shifting to lower V dd for increasing FBB.A summary of the RO results mentioned above is shown in Table I.

D. Bulk Diode Leakage
Although FBB forces parasitic diodes in forward conduction (Fig. 4a,b), the diode built-in voltage increases well beyond 1.1 V due to the increase in the bandgap E g and lower k B T /q at cryogenic temperatures [19].This, in combination with the steeper Fermi function, which requires the applied voltage to be closer to V bi before conduction starts, makes the leakage via the body terminals negligible at 4.2 K. To verify this, Fig. 4c,d show the combined bulk leakage of the 144 1025-stage on-chip ring oscillators for various FBB voltages at V dd = 1.1 V.If the well-to-well leakage were dominant (white diodes in Fig. 4a,b), the N and P bulk currents should be similar.However, since the NMOS and PMOS body current shows a dominant exponential dependence on their respective body voltage, the leakage is mainly attributed to the source/drain-to-well diodes (black diodes in Fig. 4a,b).Interestingly, the leakage changes sign for FBB around mid-supply and shows dependence on the opposite voltage.This may be due to gate leakage being affected by the FBB-tuned threshold.Normalizing the bulk at full FBB for 1.1 V supply to the total combined transistor widths results in 64.1 pA/µm (1.32 nA/µm) for NMOS (PMOS).This difference is ascribed to the difference in doping.Using those factors and the sizing of the D1 LVT RO and V dd = 1.1V, results in a bulk leakage power of 632.6 nW at 1.1 V, which is negligible as it is almost 5000 times lower than the total power (2844 µW).Even for much lower dynamic power, e.g.lower activity factor or longer devices, the bulk leakage would be negligible.Still, it might be preferable to switch the body voltage for inactive Additionally, at a lower supply, leakage will further decrease due to the exponential dependence on the bias voltages.

E. Cryogenic Design Guidelines
Based on our results, we suggest adopting cryogenic-aware FBB to LVT devices from a bulk CMOS technology with sufficiently high room-temperature body-factor.For pass-gates and high-performance or low-power digital, we suggest applying full FBB.High-performance digital circuits should remain at nominal supply, however, lowering the supply in low-power digital circuits contributes to reducing the EDP.For the LVT D1 RO in our specific technology, this means that for low-power designs the supply should be lowered to 0.725 V with full FBB, yielding an EPT / EDP reduction of 4.24 × / 2.33×, while only reducing speed by 1.82× compared to V dd = 1.1 V without FBB at 4.2 K.For high-performance designs, at V dd = 1.1 V applying full FBB results in a frequency increase of 1.62× with an EDP comparable to 300 K. Here, the leakage increases mainly due to the short circuit current, the bulk leakage power is only 0.02% of the total power.

III. CONCLUSION
The presented experimental validation shows that FBB can be applied in bulk cryo-CMOS devices and circuits with negligible leakage, even with full FBB, i.e., the N-well (P-well) to V ss (V dd ).The proposed cryogenic-aware FBB technique can compensate for the cryogenic V th shift without requiring beyond-supply voltages, thus enabling the operation of circuit topologies otherwise unusable at cryogenic temperatures, such as pass gates.In digital circuits, applying FBB can increase the speed of high-performance circuits by 1.62× or reduce the EPT by 4.24× and the EDP by 2.32× for low-power circuits.
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Fig. 1 .
Fig.1.DC measurements of LVT NMOS/PMOS devices at 300 K (red line) and 4.2 K (green to blue lines).For the 4.2-K results, the body-biasing |V bs | is swept from 0 V to 1.1 V in steps of 0.1 V (shades).To improve readability, the leakage is subtracted.The NMOS source is grounded, and the PMOS source is connected to V dd = 1.1 V. (a-b) I ds /V g at |V ds | = 1.1 V for W/L = 2µm/40nm in linear and semi-logarithmic scale.(c) W/L = 2µm/2µm in semi-logarithmic scale.(d) Small-signal resistance of the pass gate vs. the voltage applied on the drain/source, obtained by numerically combining in parallel the individually measured NMOS and PMOS resistance of (a-b).

Fig. 2 .
Fig. 2. (a) Threshold voltage at 4.2 K and 300 K of both an NMOS and PMOS LVT W/L = 2µm/40nm device at |V ds | = 50 mV when applying body biasing.The dashed line indicates the 300-K threshold without body biasing.(b) The extracted body factor.At 300 K, |V bs | is limited to 0.7 V due to the bulk diodes turning on.

Fig. 4 .
Fig. 4. (a) Simplified cross-section of a body-biased inverter in a triplewell process; the well-to-well diodes and drain/source-to-well diodes are drawn in white and black, respectively.(b) Inverter schematic.(c) NMOS and (d) PMOS body currents for all 144 ROs for V dd = 1.1 V at 4.2K.

TABLE I A
SUMMARY OF THE IMPORTANT QUANTITATIVE METRICS FOR THE RO