Analytical Modeling of Source-to-Drain Tunneling Current Down to Cryogenic Temperatures

The subthreshold swing (SS) of MOSFETs decreases with temperature and then saturates below a critical temperature. Hopping conduction via the band tail has been proposed as the possible cause for the SS saturation. On the other hand, numerical simulations have shown the source-to-drain tunneling (SDT) current limits the SS at low temperatures. It has been argued which transport mechanism dominates the cryogenic subthreshold current. Hence, for the first time, this letter presents an analytical model of the SDT current and the corresponding SS, which is validated by cryogenic measurement on devices from an advanced 16 nm FinFET technology.


I. INTRODUCTION
T HE study on transistors operating at low temperatures has been getting more attention due to quantum computing applications [1], [2], [3]. Subthreshold swing (SS) is the figure of merit that characterizes the switching efficiency between on-off states for a transistor. In MOSFETs, the thermionic SS should follow the Boltzmann limit, SS th = k B T ln (10)/q (Boltzmann constant k B , temperature T , and elementary charge q) and reach 0.83 mV/dec at 4.2 K. In reality, SS does not improve that much at cryogenic temperatures due to the SS saturation at the range from sub-10 to 30 mV/dec at 4 K [4], [5], [6], [7], [8]. The physical mechanism that limits SS at extremely low temperatures is being argued. Bohuslavskyi et al. [5] and Beckers et al. [6], [9] claimed that the band tail leads to the SS saturation at cryogenic temperatures. In particular, the hopping transport happens in the localized states just below the conduction band or right above the valance band. Consequently, the localized states in the band tail result in insufficient SS. Another transport mechanism degrading SS at cryogenic temperatures is the source-to-drain tunneling (SDT), which is an intraband tunneling from the source to the drain side. In 2002, J. Wang and M. Lundstrom, using Non-Equilibrium Green Function (NEGF) simulation, showed that SDT sets an ultimate scaling limit due to large SS, and SDT makes SS saturate below a critical temperature [10]. Recently, many groups using NEGF simulations have investigated the influence of SDT on Cryo-CMOS in terms of doping concentration, channel length, and temperature [11], [12]. However, a rigorous experimental study has not been performed yet to evidence the SDT manifesting in a down-scaled channel. This work experimentally and theoretically presents the SDT in a 16 nm FinFET technology.

II. ANALYTICAL SOURCE-TO-DRAIN TUNNELING MODEL
In a short-channel device, the gate barrier gets thinned and lowered by a strong drain voltage electrostatically due to the short-channel effects, i.e., drain-induced barrier thinning (DIBT) and lowering (DIBL). A carrier with energy lower than the barrier peak has a higher chance of tunneling through the barrier. It leads to the SDT current in the subthreshold regime, which flows in parallel with the thermionic current. To model the SDT current, we adopt Landauer formalism [13] is used for the 2-dimensional electron gas with m * the effective mass, g v the valley degeneracy, W the channel width, E cs the conduction band edge at the source, andh the reduced Planck constant [14]. The gate barrier of a short-channel device can be described by a quadratic expression [15], which yields a closed-form expression of the transmission probability with the Wentzel-Kramers-Brillouin (WKB) approximation. Hence, as shown in Fig. 1, the gate barrier energy along the y-axis is given by with coefficient V a , location of barrier peak y pk , and potential of barrier peak V pk . The term V pk is a function of the gate voltage V G and the drain-to-source voltage V DS [16]. The boundary condition of U (y) is given by with conduction potential at source V cs and channel length L b . Therefore, V a is given by The transmission probability T r (E) is therefore defined as [16] T r (E) = exp E + q V pk W sdt , where is the characteristic decay of T r (E). Because of (5) and (6), the situations such as a small m * , energy close to −q V pk , or a short L b , lead to a high T r (E). When high V DS is The term E f is equal to E fs for the LDD region.
applied, V a gets larger due to (4). Also, the tunneling distance for carriers at −q V cs is much shorter than L b , as shown in Fig. 1. On top of that, the term f d (E) in (1) can be neglected due to V DS larger than a few k B T . Hence, we can get the current density 2q h M(E)T r (E) f s (E) at each energy as shown in Fig. 1(a). Although T r (E) exponentially increases and reaches T r (E = −q V pk ) = 1, most of the tunneling carriers have energy close to −q V cs because f s (E) at low temperatures decays faster than the increase of T r (E).
In modern MOSFETs, the implementation of the lightly doped drain-source (LDD) structure is often used between the heavily doped contact and the channel [17]. Since LDD is close to the channel, it defines the position of the Fermi level close to the source E f s . For the n-type LDD region, it has a doping level (N D ) around 10 18 cm −3 . Accounting for incomplete dopant ionization and assuming the non-degenerate semiconductor give the Fermi level (E f ) referring to the conduction band (E c ) as [18] with N c the effective density of states and E D the dopant ionization energy. Fig. 3 shows the T dependency of (7), where E c − E f > 3k B T validates the use of the Boltzmann approximation. As T → 0 K, (7) can be simplified to Consequently, E f locates at (E D + E c )/2 for few Kelvins [19]. Hence, Fig. 1(b) shows the product of M(E)T r (E) f s (E) using Boltzmann approximation, which is close to expression calculated by Fermi-Dirac distribution. Finally, integrating (1) from −q V cs to −q V pk results in a closed-form expression for the SDT current as where U b = −q(V pk − V cs ), 1 W c = 1 W sdt − 1 k B T , and erf is the error function. The term U b is the energy barrier height controlled by the gate and drain voltages; the latter is due to Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. the DIBL effect. Using (8), SS sdt = ∂ V G /∂ log I sdt can then be expressed as . (9) The terms W c and U b , in the second line of (8), are functions of V G . However, their contribution to SS sdt is negligible, compared to exp (−U b /W sdt ) in the RHS of (8). Hence, SS sdt is simplified to (9), where ∂ V a /∂ V pk is analytical thanks to (4). The term n is the slope factor defined by ∂ V G /∂ V pk , which is affected by depletion, interface states, and short-channel effects [20], [21]. Eq. (9) further shows that SS sdt is temperature-independent, which leads to the SS saturation at cryogenic temperatures for extremely shortchannel devices. Additionally, SS sdt is a function of U b , V DS , and L b , because of V a and V pk − V cs . As shown in Fig. 2(a), the increase in V DS leads to a higher SS sdt . Also, a device biased in deep subthreshold regime, i.e., high U b , has the worse SS sdt . The red line shown in Fig. 2(a) accounts for the first-order DIBL effect, where U b is lowered by σ d V DS (DIBL parameter, σ d ∼ 70 mV/V [7]). Particularly, the DIBL effect compensates for the degradation from SDT, where the SS sdt accounting for the DIBL effect (red triangle line) shows a lower value than SS sdt without DIBL effect (black triangle line). In addition, Fig. 2(b) shows that SS sdt exponentially degrades as L b gets shorter. A critical temperature can be defined as SS th becomes equal to SS sdt , it yields As T < T crit , the SS saturates at the value given by (9) for a short-channel device in the presence of SDT. Fig. 4 evidences the SDT manifesting in the extremely short-channel devices at low temperatures by presenting SS(T ) for 16 nm and 36 nm FinFET. Because of (9), SS slightly changes over the whole subthreshold region. Hence, SS is extracted by taking the average from where the normalized drain current ranges from 10 −3 to 10 −2 µA/µm. As reported in the literature [5], [6], SS tends to deviate from the Boltzmann limit below a critical temperature and then saturates at 10 ∼ 30 mV/dec. In most cases, the SS saturation at low temperatures is attributed to the hopping conduction in the band tail. However, in Fig. 4(a, b), the 16 nm devices show the worse SS when |V DS | = 1.1 V, such phenomenon does not happen in the 36 nm devices. This degradation in SS is due to the SDT current that takes over the thermionic and hopping currents. In other words, the W sdt is larger than the characteristic decay of the exponential band tail (W t ≃ 4 meV) in [6]. Consequently, SS at T < T crit is dominated by SS sdt , which has a more inefficient swing than that of the thermionic and hopping currents. Finally, the model proposed in (9) is in excellent agreement with the measurement, as shown in Fig. 4(a, b). The experimental SS starts to saturate to SS sdt as T < T crit (T crit = 72 K for nMOS and 54 K for pMOS). Fig. 5 highlights the subthreshold behavior of a short pMOS at 3 K in linear and saturation regimes. Because of the short gate length, the resonant tunneling through the ionized dopant appears at low V S D [7]. The SS ascribed to the band tail can then be defined at the ultra-low current level, far from the event of resonant tunneling. Conversely, the resonant tunneling is eliminated as the device is biased at V S D = 1.1 V. Additionally, the experiment shows that the SS increases at the lower current level due to SDT; this phenomenon is well captured by the proposed model in (8) and the NEGF simulation in [11].

IV. CONCLUSION
This letter presents an analytical expression of the SDT current and its impact on the subthreshold swing SS saturation of MOSFETs at cryogenic temperatures. It is shown that for extremely short-channel MOSFETs at high V DS and for T < T crit , the subthreshold SDT current is taking over the thermionic and hopping currents. Moreover, the model highlights that SS sdt is temperature-independent but depends on the characteristic decay energy W sdt of the tunneling probability. When W sdt is larger than the characteristic energy of the band tail W t , then SS sdt becomes dominant. The proposed analytical model is successfully validated against the experimental data from a 16 nm FinFET technology.