Hybrid Pixels With Si Photodiode and 4H-SiC MOSFETs Using Direct Heterogeneous Bonding Toward Radiation Hardened CMOS Image Sensors

For radiation hardened image sensors, a Silicon-On-Insulator (SOI) -Si/ 4H-SiC hybrid pixel device was developed. The hybrid pixel device consists of one Si photodiode and three 4H-SiC nMOSFETs. At fabrication, SOI substrate was directly bonded on 4H-SiC substrate via SiO2. After bonding, the base silicon substrate and Buried Oxide (BOX) were removed by TMAH wet-etching. By using this SOI-Si/ 4H-SiC substrate, the SOI-Si photodiodes and 4H-SiC nMOSFETs were integrated in the same substrate. As a result, a response of the SOI-Si/ 4H-SiC hybrid pixel device to light illumination was successfully demonstrated.

4H-SiC (Silicon Carbide) is a wide bandgap semiconductor 27 and has excellent properties for harsh environment applica-28 tions. Thus, 4H-SiC has a wide bandgap of 3.26 eV with a 29 very low intrinsic carrier density. This can be applied to high 30 temperature applications. In addition, 4H-SiC has high atomic 31 displacement threshold energy [2], and high radiation ioniza-32 tion energy for electron-hole pair creation [3]. These properties 33 mean SiC crystal has a hardness to radiation and has potential 34 for electronic devices with low soft errors. Operation of 35 4H-SiC bipolar junction transistors (BJTs), junction field effect 36 transistors (JFETs), and metal-oxide-semiconductor transistors 37 (MOSFETs) [11], [12], [13], [14]. 39 In terms of the image sensor, 4H-SiC has already demonstrated 40 operation as a UV imaging system with 256 pixels at 400 • C 41 [15]. However, 4H-SiC does not have sufficient absorbance 42 at visible light [16]. For a pixel device in a conventional 43 Si CMOS image sensor, Si MOSFETs used as the reset 44 (RST), source follower (SF), and row selector (RS) are more 45 sensitive and vulnerable to radiation than Si photodiodes (PD). 46 Therefore a combination of SiC MOSFET and Si PD would be 47 a candidate for a pixel device using radiation-hardened CMOS 48 image sensors. 49 We have already demonstrated total ionizing dose effect 50 (TID) resistance of 4H-SiC MOSFETs and some reports also 51 showed that the MOSFETs work even after high irradiation 52 doses exceeding 100 Mrad [12, [13], [14]. The thick embedded 53 oxide film makes SOI devices relatively vulnerable to TID, 54 however, we suggest that TID effects can be reduced by 55 thinning the BOX layer to the same thickness as the gate oxide 56 film. Takeuchi et al. reported that in the case of discrete Si-PD, 57 dark current was within the acceptable range even after gamma 58 irradiation with a dose of 1000 kGy [17].

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In this work, SOI-Si PD and 4H-SiC MOSFETs were 60 integrated by applying direct bonding of SOI and 4H-SiC 61 substrates, and the fabrication and optical response of the 62 SOI-Si/ 4H-SiC hybrid pixel device for radiation hardened 63 image sensors were demonstrated. SF, RS and BIAS transistors. The pixel device was designed 69 based on the characteristics of the 4H-SiC nMOSFETs [12].

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The pixel device circuits with the nMOSFETs are shown in  The thick Si handle substrate of the SOI was removed using 101 a wet-etching process. by sputtering. The sample was annealed at a temperature of 115 930 • C in N 2 ambient for 5 minutes. After silicidation, contact-116 vias to SOI-Si PDs were formed. Subsequently, an Al metal 117 layer was formed by sputtering and was patterned with a 118 lithography process and Al etching process. After forming the 119 Al metal layer, SiO 2 interlayer dielectric film was formed with 120 atmospheric pressure chemical vapor deposition (APCVD).  Figure 2 shows the micrograph of the hybrid pixel 124 devices with the integration of SOI-Si PDs and 4H-SiC 125 nMOSFETs. The typical feature size of SOI-Si PDs 126 was 300 μm × 300 μm and the feature size of 4H-SiC 127 nMOSFETs was channel length/width = 10 μm /10 μm.

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The SOI-Si active layer had a resistivity of 8 ·cm to 129 12 ·cm, and in the photosensitive area we didn't apply 130 additional doping. The SOI-Si thickness was limited to 500 nm 131 in this study because of the step coverage of the Al intercon-132 nects and the etching process of the SOI-Si layer. A lateral 133 junction structure was used for the photodiode in the pixel 134 to achieve sufficient quantum efficiency values with a thin Si 135 film. Inside the photodiode, n+ regions with a width of 5 μm 136 were patterned in stripes. As a result, 28 line PN junctions 137 were formed. The total PN junctions width is 5.8 mm.

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A square Al metal line was formed around the SOI-Si 139 photodiode. This metal line was connected to the GND metal 140 pad electrode through a p+-SiC body contact. The Al metal 141 line in the center of the SOI-Si photodiode was connected to 142 the n+-Si region of the SOI-Si photodiode. This metal line 143 was extended to the 4H-SiC SF transistor and was directly 144 connected to the gate electrode of the SF transistor. The current-voltage characteristics of the photodiode in 151 the dark condition are shown in Fig. 3. The ideality factor 152 indicating the quality of the PN junction is 1.5 at a cathode 153 voltage of −0.55 V, suggesting that the Si layer contains defect 154 levels that contribute to the diffusion current. During device 155 fabrication, several thermal processes after wafer bonding may 156 cause serious defect formation in the bulk. The ideality factor 157 value suggests that some defects are formed in the photodiode, 158 both at the interface and in the bulk, but under sufficient light 159  The maximum swing of the output voltage was limited by 193 the voltage drop (0.5 V) at the PD node immediately after the 194 reset operation. This voltage drop (reset feedthrough) is due to 195 the ratio of the gate-to-source overlap capacitance of the RST 196 MOSFET to the PD node capacitance, which is estimated to 197 be about 5% assuming an SF gain value 1 [18]. The value is 198 one order of magnitude higher than the designed value. As for 199 the PD capacitance, the cause of the capacitance mismatch 200 was considered to be the presence of a low concentration 201 carrier layer in the Si film at the bonding oxide film interface, 202 or an unexpected drop in capacitance due to the growth of the 203 bonding oxide layer. * -

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The saturation of the output voltage swing is determined 205 by the threshold voltage of the SF MOSFETs as well as the 206 PD node capacitance. The MOSFETs in this study has its 207 threshold voltage at approximately half of VDD, so this effect 208 is expected to be significant.

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IV. CONCLUSION 210 We developed a SOI-Si/ 4H-SiC hybrid pixel device, 211 in which a Si photodiode and a 4H-SiC MOSFET are inte-212 grated on a single chip by direct heterojunction of SOI 213 and 4H-SiC substrates. In the pixel part, the relationship 214 between the irradiance and the output voltage swing at 550 nm 215 visible light wavelength is shown. In SOI-Si PDs, the linear 216 characteristics, its irradiance range, and quantum efficiency at 217 550 nm visible light wavelength are shown. The operation of 218 the pixel was examined at an operating frequency of 60 Hz. 219 The reset period should be kept small enough compared to 220 the integration period. This 60 Hz operating speed remains a 221 challenge. However, we have successfully demonstrated the 222 reset and integration operation of the pixel and shown its 223 feasibility. By employing a preamplifier in the output stage 224 of the pixel or pixel array, a higher operating frequency is 225 expected to be achieved.