Improved Soft-Aided Decoding of Product Codes With Dynamic Reliability Scores

Products codes (PCs) are conventionally decoded with efficient iterative bounded-distance decoding (iBDD) based on hard-decision channel outputs which entails a performance loss compared to a soft-decision decoder. Recently, several hybrid algorithms have been proposed aimed to improve the performance of iBDD decoders via the aid of a certain amount of soft information while keeping the decoding complexity similarly low as in iBDD. We propose a novel hybrid low-complexity decoder for PCs based on error-and-erasure (EaE) decoding and dynamic reliability scores (DRSs). This decoder is based on a novel EaE component code decoder, which is able to decode beyond the designed distance of the component code but suffers from an increased miscorrection probability. The DRSs, reflecting the reliability of a codeword bit, are used to detect and avoid miscorrections. Simulation results show that this policy can reduce the miscorrection rate significantly and improves the decoding performance. The decoder requires only ternary message passing and a slight increase of computational complexity compared to iBDD, which makes it suitable for high-speed communication systems. Coding gains of up to 1.2 dB compared to the conventional iBDD decoder are observed.


I. INTRODUCTION
Product codes (PCs) [2] are powerful code constructions with high net coding gains (NCGs) that can be obtained with low-complexity decoders suitable for e.g., high-speed optical fiber communications.A PC codeword is a 2-D array where every row and column is protected by a component code, which is typically a Reed-Solomon (RS) code or a Bose-Chaudhuri-Hocquenghem (BCH) code.In high-throughput applications, PCs are typically decoded with iterative boundeddistance decoding (iBDD) where the component code is decoded by an efficient algebraic component code decoder based on the hard-decision channel output.iBDD is also often referred to as hard decision decoding (HDD) of PCs.
Soft decision decoding (SDD) of PCs, also known as turbo product decoding (TPD) [3] improves the error-correcting This work was supported by the European Research Council under the European Union's Horizon 2020 Research and Innovation Programme under Grant 101001899.Parts of this paper have been presented at the Optical Fiber Communication Conference (OFC), 2022 [1].(Corresponding author: Sisi Miao.) The authors are with the Karlsruhe Institute of Technology (KIT), Communications Engineering Lab (CEL), 76187 Karlsruhe, Germany (email: {sisi.miao@kit.edu,lukas.rapp3@student.kit.edu,schmalen@kit.edu}.
Color versions of one or more figures in this article are available at https://doi.org/10.1109/JLT.2022.3201951.
Digital Object Identifier 10.1109/JLT.2022.3201951ability of PCs by exploiting soft channel information and listbased decoding.Typically, a 1-2 dB coding gain improvement can be observed compared to HDD/iBDD [4].However, the high internal decoder data flow required by the soft-message passing in TPD makes it challenging to adapt for ultrahigh-speed optical fiber communication systems operating at throughputs of 800 Gbit/s and beyond [5].In contrast, HDD provides a significant reduction in internal decoder data flow by only passing hard messages.Recently, several hybrid SDD/HDD schemes have been proposed which provide a performance/complexity trade-off.The unifying idea of these algorithms is to use soft channel information to aid the harddecision decoder while keeping the complexity similarly low as in iBDD.
One promising approach for hybrid SDD/HDD is to use ternary messages and error-and-erasure (EaE) decoding.EaE decoding with a stall pattern analysis was studied in [6], assuming miscorrection-free decoding.In [7], a thorough analysis of iterative error-and-erasure decoding (iEaED) with extrinsic message passing (EMP) based on density evolution (DE) takes miscorrections into account.The results show that iEaED without miscorrection detection yields only small coding gains compared to HDD.The binary message passing based on EaE decoding for PCs (BEE-PC) proposed in [8] uses EaE decoding with a relatively high-cost miscorrection control and yields the best performance of hybrid SDD/HDD PC decoding so far.BEE-PC is also based on the idea of combining properly scaled soft channel reliability with the component code decoding decision, which was proposed and developed in [9], [10], [11], [12], [13].
Soft-aided bit marking (SABM) decoder was proposed in [14] and later improved to SABM with scaled reliabilities (SABM-SR) in [15] for PCs.The bits with high channel loglikelihood ratios (LLRs) are marked as highly reliable bits (HRBs) and used for miscorrection detection based on the principle that a BDD output is considered as miscorrection if it conflicts with any HRBs.However, the effect of erroneous HRBs are difficult to be eliminated without an effective update mechanism for the HRBs.
In [16], anchor decoding (AD) was proposed.Unlike the above-mentioned hybrid decoders, AD requires no soft channel output but instead operates purely on the hard-decision channel output.The anchor bits are dynamically set during decoding and used for miscorrection detection as in SABM.However, the achievable coding gain is limited due to wrongly marked anchor bits, especially in the first decoding iterations.AD has also been shown to be useful in reducing the decoding complexity and improving the decoding performance when combined with list decoding for low rate PCs [17], [18].
In this paper, we propose a novel hybrid decoding scheme for PCs.We first propose a modified EaE decoder able to decode beyond the minimum distance of the component codes, at the cost of an increased miscorrection rate.The miscorrection problem is then solved with a novel miscorrection detection scheme which resembles a combination of AD and SABM.We introduce a new reliability measurement called dynamic reliability score (DRS) that is initialized with the soft channel output and updated during iterative decoding.The DRSs are then used to identify the anchor bits and to detect miscorrections.We present the decoder and a detailed analysis of the decoding behavior.
The remainder of the paper is organized as follows.In Sec.II, the preliminaries are given.In Sec.III, we introduce the proposed EaE decoder used as the component code decoder for PCs and calculate the decoding ability of such decoder assuming no miscorrections.In Sec.IV, we introduce the DRS and describe the architecture of the proposed decoding algorithm.The simulation results in Sec.V shows that the proposed decoder yields improved decoding performance and approaches miscorrection-free decoding.The reason of the decoding performance gain is heuristically illustrated in Sec.VI with an example.In Sec.VII, we analyze the computational and storage overhead.The last section concludes the paper.
Notation: We use boldface letters to denote vectors and matrices, e.g., y and Y .The i-th component of vector y is denoted by y i , and the element at the i-th row and j-th column of Y is denoted by Y i,j .Let y i be the i-th row of a matrix Y .Z 32 stands for the set {0, 1, . . ., 31}.R stands for the set of real numbers and R ≥0 for the set of non-negative real numbers.For x ∈ R, x is the floor function that gives the greatest integer less than or equal to x.We use a superscript to denote the maximum number of iterations carried out by an iterative decoder, e.g., iBDD 10 .

II. PRELIMINARIES
A PC codeword is a two-dimensional rectangular array where every row and every column is a codeword of a component code chosen to be same (n, k, t) code C 1 .We consider C being either a (2 ν − 1, k 0 , t) binary BCH code or its (2 ν −1, k 0 −1, t) even-weight subcode, both able to correct t errors with standard bounded distance decoding (BDD).Let d des be the design distance of C (d des ≤ d min , with d min the minimum Hamming distance of C) and t = (d des − 1)/2 .The rate of the constructed PC is r = k 2 /n 2 .
We consider a binary phase shift keying (BPSK) modulation and assume that the codewords are transmitted over a binary input additive white Gaussian noise (BI-AWGN) channel.For any transmitted bit x i , the channel output is where n i is (real-valued) AWGN with noise variance σ 2 n = (2rE b /N 0 ) −1 . 1 We only consider PCs with identical row and column codes in this paper.However, the proposed decoding scheme naturally extends to general PCs where the row and column code are not necessarily the same.0 1 proportional to the magnitude of the channel output.Therefore, when performing a hard-decision at the channel output, a received value ỹi with small magnitude is considered to be unreliable.We define T , a configurable threshold, such that values ỹi ∈ [−T, +T ] are declared as erasures "?".For |ỹ i | > T , y i = sign(ỹ i ) by the usual HDD rule.Therefore, the channel outputs are mapped to three discrete values as depicted in Fig. 1 where is the error probability and is the erasure probability.When T = 0, the EaE channel reduces to a binary symmetric channel (BSC).An error-only BDD succeeds when its input word is in a Hamming sphere S t (c) = {y ∈ {0, 1} n : d(y, c) ≤ t} of radius t around a codeword c ∈ C where d(y, c) is the Hamming distance between y and c.
We define the BDD decoding rule for a binary vector y ∈ {0, 1} n as BDD(y) = c ∃c ∈ C such that y ∈ S t (c) y otherwise.

III. ERROR-AND-ERASURE DECODING
A. Error-and-erasure Decoder (EaED) In this paper, we propose the following EaED, which is a modification of [21,Sec. 3.8.1].Let y ∈ {0, ?, 1} n be the received row/column vector, and let w := EaED(y) be the decoding result.
If E(y) ≥ d des , the EaED does not decode and declares a failure, returning w = y, as a large number of erasures cannot be handled by the decoder.
Then, two BDD steps are performed.Let for i ∈ {1, 2}.The EaED output is determined based on the two BDD outputs using the following rules: Case 1: If both BDD steps fail, set w = y.Case 2: If w (i) ∈ C for exactly one w (i) , set w = w (i) .Case 3: If both BDD steps succeed, let The EaED algorithm is summarized in Algorithm 2. Note that the EaED reduces to a conventional BDD decoder when there are no erasures, i.e., E(y) = 0.
Another commonly-used EaE decoder is a one-step EaE decoding algorithm2 proposed by Forney in [22].It extends the Gorenstein-Zierler algorithm [23,Ch. 6] and resolves errors and erasures at the same time by solving the key equation.It requires some modifications in the key equation solver inside the decoder while EaED uses two legacy BDDs for the BSC with some additional operations and control logic.Let w denote the decoding result.Forney's EaE decoder follows the decoding rule given by w = c ∃c ∈ C such that y ∈ S  (y, c) + E(y) ≥ d des because all (or large enough number) of the erasures may possibly be filled with a correct transmit value when generating y (1) and y (2) .Thus, the EaED has potentially higher error-correcting capabilities than the one-step EaE decoder (see also Sec.III-B) but is also more prone to miscorrections without the constraint that w ∈ S 3 t (y).Consequently, in our previous work, the EaED did not yield a satisfying decoding performance gain for PCs due to the lack of miscorrection control [7].In this paper, we deal with the miscorrection problem to fully exploit the error-correcting potential of the EaED.

B. Failure Analysis of EaED with Ideal Miscorrection Detection
In this section, we analyze the error-correcting ability of a genie-aided ideal EaED following the decoding rule given by ideal EaED(y) = x if EaED(y) = x y otherwise, Fig. 2. Graphical illustration of the number of EaEs with a filling pattern (p (1) , p (2) ) assuming the zero codeword was transmitted.
where x is the transmit codeword.It can be seen as an EaED followed by an ideal miscorrection detection that discards all miscorrections.Although such a decoder may be impossible to realize, our simulation results in Sec.VI show that our proposed novel decoder approaches its performance when the number of erasures is moderate.
If no miscorrections happen, the success rate of one component code decoding by ideal EaED can be calculated combinatorically.Let P s (D, E) denote the ideal EaED success probability when decoding with D errors and E erasures.
Case 2: Assume D ≤ t, E < d des , the ideal EaED succeeds if and only if Let e denote the number of positions in p (1) that differ from the transmit codeword x.Fig. 2 illustrates the received word y and both y (1) and y (2) where the erasures have been replaced by the filling patterns.Under the assumption that x = 0 was transmitted, e denotes the number of "1"s in p (1) .Then, the number of such positions in p (2) is E − e because p (1) and p (2) are complementary.The number of errors in y (1) is D +e and the number of errors in y (2) is D + E − e.Therefore, the condition for correctability reduces to D+e ≤ t or D+E−e ≤ t, i.e., e ∈ [0, Case 2.1:  , E) by counting the number of cases where (1) holds.We first show that it is impossible that e ≤ t − D and e ≥ E + D − t are true at the same time.Assume that both conditions are fulfilled, then E + D − t ≤ e ≤ t − D for some e.This leads to 2D + E ≤ 2t.As d des > 2t, this is impossible.Therefore, either y (1) or y (2)   Therefore, we summarize For example, Tab.I gives the success rate of EaED when decoding with various numbers of EaEs for a t = 2, d des = 6 component code.When 2D+E ≥ d des , the success probability decreases with an increasing number of EaEs.However, the values are not zero as for the one-step EaE decoder by Forney (Tab.II).The advantage of ideal EaED becomes larger during iterative decoding, where new, independent filling patterns are chosen each time a codeword is decoded.With ideal miscorrection detection, if the success probability of one EaED step is P s , the probability of success after decoding trials is 1 − (1 − P s ) .For example, Tab.III shows the success probability after = 5 decoding trials for EaED with ideal miscorrection detection.This also proves that random filling patterns (p (1) , p (2) ) are crucial for the performance of the proposed decoder.As the number of EaEs is reduced during the PC decoding process, the actual success rate can be potentially even higher.Moreover, the decoding success probability 1 − (1 − P s ) approaches 1 with a sufficiently large number of iterations, which is not realistic in practice.Thus, Algorithm 3: Initialization of the Dynamic Reliability Scores (DRSs) // Eq. (2) 3 z ← sort | z| ascendingly 4 σ(•) ← permutation function of the indices 5 S ← assign DRS according to z // Eq. (3) 6 Output: S ∈ {9, 10, . . ., 24} n×n we only use 10 decoding iterations of the ideal EaED when using it as a benchmark.

IV. DYNAMIC RELIABILITY SCORE (DRS) DECODING
To represent and update the reliability of a bit in the PC block, we introduce a reliability measure called DRS, which is stored in an additional register separately from the PC codeword.The DRS reflects the reliability of a bit from both its channel LLR and its behavior during decoding.We propose to represent the DRSs by 5-bit integers in the range [0, 31] (as we observe that further increasing the number of representation levels does not improve the performance of the proposed decoder significantly).We introduce an anchor threshold T a .All bits with a DRS > T a are classified as anchor bits (following [16]) during decoding and are not allowed to be flipped by a component code decoder.Note that the DRS is not a fully-accurate measurement of the reliability, i.e., we cannot say that a bit with higher DRS must be more reliable than a bit with lower DRS.However, we can say that bits with DRS above the threshold T a can be considered as correct with high confidence.The DRS is used for miscorrection detection in iterative decoding with EaED.
The block diagram and workflow of the proposed dynamic reliability score decoder (DRSD) is shown in Fig. 3.
At the initialization, the received unquantized real-valued channel output of the PC block Ỹ ∈ R n×n is fed to two paths.In the upper path, the initial value of the DRSs S is calculated for the PC block.To do this, we first reshape Ỹ into a vector z = (z 1 , z2 , . . ., zn 2 ) ∈ R n 2 where Then the absolute value of z is taken and sorted ascendingly, resulting in a vector z such that the initial DRSs are in the range of [9,24].This process is summarized in Algorithm 3.This initial DRS value is stored in the DRS register.The anchor threshold T a is set as the optimal value found during simulation (see Sec. V).In the lower branch, erasures are marked, i.e., Y i,j = ?if | Ỹi,j | < T , with T (defined in Sec.II) being an optimizable threshold.For non-erased bits, a usual hard-decision is performed.The initial block Y ∈ {0, ?, 1} n×n is passed to the iterative row and column decoder.
During iterative decoding, the rows and columns are decoded alternately until the maximal number of iterations L is reached, as in a conventional iBDD decoder.We replace the BDD decoder by an EaED.Moreover, every EaED decoding step is followed by the miscorrection detection step evaluating whether an anchor bit is flipped by the EaED output.In this case, this decoder output is discarded and the DRS for all the anchor bits in conflict with this EaED output is reduced by 1.If a decoding step does not flip any anchor bit, this EaED output will be accepted while the DRS of all flipped bits is reduced by 1.If a vector is already a codeword and thus no decoding is performed, the DRS of every bit in it    is increased by 1.This is based on the observation that the longer a bit stays constant during iterative decoding, the more reliable it is.A similar idea has been exploited in AD [16].The messages used for updating the DRS are all set to 1 to enable a simple hardware implementation of the DRS register avoiding the need for full adders.The DRS values will be clipped to 0 and 31, respectively.In the case of an EaED decoding failure, neither the codeword nor the DRS is changed.In addition, the anchor threshold T a is increased by 1 after every five decoding iterations, such that a small penalty is given for words that fail to decode consistently.With the update of the DRSs, the anchor bits are reevaluated every iteration.For DRSD L , the last L/5 iterations are performed with plain iEaED.This is to eliminate the effect of erroneous anchor bits with high DRS.
After L iterations, the erased values which have not been resolved are replaced with a random binary value.We call the proposed decoder DRSD and the complete algorithm of the proposed decoding scheme is summarized in Algorithm 4. Furthermore, when L is sufficiently large, (e.g.L = 20), we propose an alternative termination option where the few final decoding iterations are no longer plain iEaED but DRSD with a very high and constant but optimizable anchor threshold T * a (see Algorithm 4, lines 37-38).We call the resulting algorithm DRSD+.The DRSD+ is motivated by the observation that most of the correct bits will have very high DRSs after a sufficiently large number of iterations (see Sec. VI).Consequently, when a large T * a is used, the erroneous anchor bits are removed while a relatively large set of correct anchor bits are still preserved, resulting in a decoding performance improvement.

A. Preparation
We verify and demonstrate the performance of DRS decoding using numerical examples.For the proposed DRSD, we consider both L = 10 and L = 20 as 10 iterations are often used in the literature for soft-aided PC codewords, but we observe that DRSD can benefit from more than 10 iterations.
We determine the noise threshold as the minimal E b /N 0 with which the target bit error rate (BER) of 10 −4 after a fixed number of iterations is achieved.For two decoders, we compare their performance by calculating the noise threshold difference (gain) ∆(E b /N 0 ) * .The noise thresholds are calculated numerically by a Monte Carlo approach along with a binary search and both the optimal erasure threshold T (T opt ) and the optimal initial anchor threshold T a are found during the search.As the initial DRSs are in the range of [9,24], the initial T a is also in this range.Moreover, as a too small number of anchor bits does not contribute to the miscorrection detection significantly, we narrow down the search space for T a to [9,15].Then, the parameter optimization for both T and T a can be carried out by a grid search.The anchor threshold T a depends mostly on t.For L = 20, the estimated optimal initial value of the anchor threshold is T a = 9 for t = 2, T a = 10 for t = 3, and T a = 12 for t = 4.For the (127, k, 4) component codes, we exceptionally find T a = 14.For L = 10, the initial anchor threshold T a is reduced by 1 for all component codes.
The optimal erasure thresholds T opt are as shown in Fig. 4. We observe that slightly varying T (within ±10%) does not degrade the performance severely.

B. Noise Threshold Gain
* that a DRSD 20   achieves compared to an iBDD 20 decoder is calculated and shown in Fig. 4 with the non-transparent markers.We additional show the noise threshold gain of EaED with ideal miscorrection detection and L = 16 iterations compared to iBDD 20 with the transparent markers (the optimal threshold T may differ slightly but is not plotted for the sake of clarity).We use L = 16 for EaED with ideal miscorrection detection as it does not require the final 4 iterations of EaED to mitigate the risk of erroneous anchor bits.The dotted line depicts the capacity gain of the BI-AWGN channel compared to the hard-decision BSC.Note that when a data point exceeds the dotted line, the code does not operate beyond capacity.This simply means that the noise threshold gain of DRSD compared to iBDD is larger than the capacity gain of the BI-AWGN channel compared to the BSC.In general, for PCs with various component codes, the noise threshold gain of DRSD is similarly large as the noise threshold gain of EaED with ideal miscorrection detection.This means that our proposed decoder is nearly miscorrection-free.For larger t and higher code rate, the gap between DRSD and the ideal case becomes even smaller.

C. BER Results
In Fig. 5, we compare the residual post-decoding BER for different decoders.We construct two PCs from evenweight subcodes of BCH codes denoted by C 1 (127, 112, 2) and C 2 (255, 238, 2) with PC rates of 0.78 (28% overhead) and 0.87 (15% overhead), respectively.For reference, we show the results of TPD [3], SABM-SR [15], BEE-PC [8], and AD [16] with the data points provided in [8] and [15] where the component codes are singly-extended BCH codes with parameters (128, 113, 2) and (256, 239, 2) (hence with a small, negligible rate difference compared to our codes).For iBDD, we observe that the decoding results of L = 10 and L = 20 do not have a noticeable difference.Thus, we only show the results of iBDD 10 .For both PCs, an obvious gain compared to iBDD can be observed with DRSD and the performance is further improved by running 20 iterations.With twice the number of iterations, our decoder behaves very closely to an EaED with ideal miscorrection detection (denoted as "ideal EaED L " in the figure) and has only a small gap to the significantly more complex TPD.For the rate 0.78 PC, we estimate, at a residual BER of 10 −15 , an NCG of 10.88 dB (DRSD 10 ) and 11.03 dB (DRSD 20 ).The NCGs are obtained by extrapolating the simulation results from Fig. 5 using berfit in MATLAB ® assuming no error floor.For the rate 0.87 PC, the conjectured NCGs are 10.51 dB and 10.59 dB respectively.The modified DRSD+ 20 provides an additional 0.05 dB coding gain compared to DRSD 20 without extra complexity.The optimal erasure threshold for DRSD+ 20 is T opt + 0.2 with T opt the optimal erasure threshold of DRSD 20 and the optimized T * a = 24.Compared to a plain iBDD decoder, the DRSD+ 20 yields 1.14 dB and 0.89 dB decoding gain for the rate 0.78 and rate 0.87 PCs, respectively.(As DRSD+ 10 does not improve the decoding performance significantly, its results are not shown).
We observe that DRSD yields significantly better performance when 20 iterations are used.The reason behind this is that: first, the decoder needs to obtain a both large and reliable set of anchor bits in the first few iterations of decoding as we will show in Sec.VI.Second, assuming no miscorrections, the use of random filling of the erasures ensures that the probability of correctly decoding words with erasures rises with the number of iterations as shown in Sec.III.Moreover, as Sec.VII will show, using 20 iterations does not increase the decoding complexity significantly.We conclude that it is much more beneficial to use 20 decoding iterations.

D. The Importance of Random Filling Patterns
In Fig. 6, additionally to the BER results after decoding with the proposed decoding scheme, we show the performance when using deterministic filling vectors for the erased positions within the EaED.The purple curves depict the decoding performance using a DRSD but we replace the random filling pattern p (1) , p (2) in Algorithm 2 (line 5) with (0, 1) as in [21,Sec. 3.8.1].This degrades the decoding performance by more than 0.1 dB for both PCs.Moreover, we observe that when using a deterministic value for p (1) and p (2) , allowing 20 iterations does not yield performance gains as large as we observe with DRSD.This is due to the fact that with identical filling patterns, row/column words which cause a decoding failure in early iterations will still cause a decoding failure if its EaEs are not corrected by the corresponding column/row code.

E. Choice of Parameters
In Sec.IV, we gave the algorithm description with a predefined number of 32 DRS representation levels and an initial DRS range of [9,24].In this section, we provide some intuition and numerical simulation results which support this choice of parameters.
Figure 7 shows the decoding performance of DRSD 20 with different DRS representation levels.We consider the number of levels in terms of the number of bits required for storage.All thresholds inside the algorithm are scaled relatively to the number of representation levels.If the number of representation levels is smaller than 32, we observe a degradation of the decoding performance.However, if a smaller storage space is preferred, the DRSD algorithm can still be used with some loss in decoding performance.As using 64 levels does not improve upon 32 levels significantly, we choose 32 levels for the proposed DRSD throughout this paper.
Next, we consider the range into which the initial DRS are distributed: first, the range should not be too small so that the channel output reliability information can be fully exploited.Second, it should not be too big either, otherwise, the updating mechanism during iterative decoding would have too little impact on the scores and thus cannot efficiently update the  anchor bits.We exemplarily show the performance for some ranges [a, b] in Fig. 8 for 32 DRS representation levels.We observe that an initial range that is too big or too small degrades the decoding performance.Hence, we choose to use the initial range of [9,24], as it is a good compromise between representing the soft channel output and leaving sufficient room for increasing and decreasing the scores.

VI. HEURISTIC PERFORMANCE ANALYSIS
In this section, we investigate the iterative decoding process to show the connection between anchor bits and miscorrections.This also illustrates the advantage of the DRSD+ termination variant.Figure 9 shows the fraction of anchor bits, erroneous anchor bits, and miscorrections during the decoding of a PC with component code C 2 and L = 20 iterations.The quantities are provided for each half iteration which is defined as the processing of decoding all the rows or all the columns of a PC block once.The values are calculated by averaging the respective quantities during the Monte-Carlo simulations which produced Fig. 5.The leftmost subfigure depicts the fraction of anchors in each iteration and the middle subfigure depicts the fraction of wrongly marked anchor bits for different values of E b /N 0 (the 0-th half iteration stands for the state after initialization and before iterative decoding).According to Sec.V, we set the initial anchor threshold to T a = 9.Since there are 16 representation levels (in the interval [9,24]) for the initial DRSs, the initial fraction of anchor bits (DRS > T a ) is always around 15/16 ≈ 93.8%.The number of erroneous anchor bits decreases as E b /N 0 increases.The ratio of anchor bits increases during iterative decoding due to the raise of DRSs for the bits that are successfully decoded.At the same time, the DRS of the bits where the row and column decoders disagree is reduced.This reduces the number of erroneous anchor bits.T a is increased by 1 after every 10 half-iterations, corresponding to the drop in both overall and erroneous anchor bits.As the last 4 iterations of DRSD are plain iEaED and the DRSs are not used, the solid lines stops after 32 half-iterations.
The rightmost subfigure in Fig. 9 shows the number of miscorrections in each half iteration.For a poor E b /N 0 with a high post-decoding BER, the DRS updates fail to raise the ratio of anchor bits and decrease the ratio of erroneous anchor bits sufficiently.Consequently, the number of miscorrections is high and even increases during decoding (due to error propagation).However, in the waterfall region, our decoder effectively prevents miscorrections.When E b /N 0 ≥ 4.29 dB, nearly all decoded bits are marked correctly as anchor bits after a few iterations, resulting in almost no miscorrections, whereas a plain iEaED without miscorrection detection will have more than a hundred miscorrections in each iteration given the same E b /N 0 value, as we observed during experiments.
As shown in Fig. 9, the number of miscorrections in the last few plain iEaED decoding iterations is relatively high.However, we observe that without these termination iterations, the decoding performance suffers from a high error floor due to erroneous anchor bits.The DRSD+ termination option removes almost all erroneous anchors with the high anchor threshold T * a .This reduces the number of miscorrections in the last iterations while also eliminating the effect of erroneous anchor bits, leading to the improved decoding performance.

VII. COMPLEXITY ANALYSIS
The proposed decoder does not require soft message passing.The DRS register sends a binary message to the EaED indicating whether a bit is an anchor or not.The EaED signals to the DRS register if DRSs should be increased or decreased.During EaE decoding, ternary messages are passed.The major computational overhead of the proposed DRSD compared to iBDD is the usage of EaED, where the presence of erasures in a component word entails two BDD steps.This increases the overall number of BDD steps, especially in the first few iterations, before the erasures are resolved.Words without erasures can be decoded with simple BDD.The additional storage for DRSs is relatively small as the DRSs are stored using 5-bit integers.
As the main cause of the computational overhead is the increase in the number of BDD steps, we show in Fig. 10 an exemplary comparison of the BDD steps in the decoding of a PC with component code C 2 .See Fig. 5 for the decoding performance of this code.We record the number of BDD steps used in three decoding schemes.One is the conventional iBDD 10 , which serves as a baseline.Then we plot the results of DRSD 10 and DRSD 20 respectively.All the results are normalized by (255 • 20), which is the total number of BDD steps in the iBDD 10 decoding process.Two facts cause the normalized value to be less than 1: one is early termination due to the decoding success of the entire PC block.Another one is that we do not count the decoding of words with zerosyndrome, as the actual decoding algorithm does not need to be carried out.In the low E b /N 0 region, the DRSD decoder requires a relatively large number of BDD steps.However, for larger E b /N 0 , the number of decodings steps is within the same order of magnitude as for iBDD.We also observe that the effective number of BDD steps in the DRSD 20 scheme increases only slightly compared to DRSD 10 .Other soft-aided decoding schemes such as the SABM-SR decoder [15] also require a number of BDD steps that is likely within the same order of magnitude than DRSD.

VIII. CONCLUSION
We proposed a novel hybrid decoding scheme for PCs and simulation results show that the proposed DRS decoder significantly improves the decoding performance of the conventional hard decision iBDD for PCs with near miscorrection-free EaE decoding.For two exemplary PCs of rate 0.87 and rate 0.78, DRSD closes roughly 80% of the gap between hard-decision iBDD and soft-decision TPD which outperforms other softaided HDD schemes.Complexity analysis shows that the decoding complexity is similarly low as for conventional HDD iBDD decoder.The high NCGs make this scheme a promising candidate for future low-complexity optical communication systems.
One of the open questions is the error floor of the proposed DRSD.With a proper choice of the parameters, we conjecture that the proposed DRSD should not have a worse error floor than a plain iterative EaE decoder, which has been investigated in [6] for PCs with relatively small block lengths.The reason is that DRSD does not introduce additional miscorrections compared with the plain iterative EaE decoder.However, the EaE decoder used in this work is different from the EaE decoder studied in [6].Therefore, accurately calculating the error floor for decoding the PCs with large block lengths that are used in this work remains difficult and is left as future work.

Fig. 1 .
Fig. 1.Channel model of the EaE channel

}
16 Output: w ∈ C ∪ y conventional iBDD decoding scheme described in Algorithm 1 D C is a BDD decoder.In this paper, we replace D C by an EaE decoder described later in Sec.III.Throughout this paper, we always let the result of a component decoder D C be w := D C (y) ∈ C ∪ y where w = y in case of a decoding failure.
where z σ(i) = |z i | and σ(•) is a permutation of the indices corresponding to the sorting operation.Then, the initial DRSs S ∈ Z n×n 32 are assigned by

Fig. 4 .
Fig. 4. Simulation results of the parameter analysis: The optimal erasure threshold Topt for DRSD20 found during numerical simulation is plotted in the left subplot.The noise threshold gain that the DRSD 20 achieves compared to iBDD 20 is plotted in the right subplot with the non-transparent markers.The component codes are (n, k, t)−BCH codes with n ∈ {127, 255, 511} and t ∈ {2, 3, 4} or their even-weight subcodes.The abscissa corresponds to the rate r of the constructed PCs.Additionally on the right subplot, the transparent markers corresponds to the respective EaED with ideal miscorrection detection and L = 16 iterations (denoted as "ideal EaED").The dotted curve marks the capacity gain due to SDD on the binary-input AWGN channel.

Fig. 6 .
Fig. 6.BER vs. E b /N 0 (in dB) curve for product codes with component code C 1 and C 2 when decoded with various modifications of DRSD.The superscript of the labels denotes the maximum number of decoding iterations L.

EFig. 9 .
Fig. 9. Percentage of marked anchor bits, percentage of wrongly marked anchor bits, and average number of miscorrections in every iteration in the decoding of a (255, 238, 2) even-weight BCH subcode for various E b /N 0 .The solid oranges lines stand for DRSD20 and the dashed pink lines for DRSD+20 .

TABLE I EAED
SUCCESS RATE FOR DIFFERENT EAE PATTERN FOR A t = 2, d des = 6 COMPONENT CODE e ≥ E + D − t, there are e=0 E e cases where decoding will succeed.In total, there are 2 E possible filling patterns for the E erasures and each pattern is equally likely.Thus, P s (D, E) = 2