TCAD-Assisted Progress on the Cisco Platform Toward Low-Bias 200 Gbit/s vertical-pin Ge- on-Si Waveguide Photodetectors

We discuss the characterization and numerical simulation of vertical Ge-on-Si waveguide photodetectors (VPIN WPDs) of the Cisco platform for data communications in the O-band (<inline-formula><tex-math notation="LaTeX">$1.31 \,\mu \mathrm{m}$</tex-math></inline-formula>), with the goal of optimizing their frequency response while integrating them into low-power systems. In a large set of WPDs belonging to 6 different structural variants, at a standard bias voltage of <inline-formula><tex-math notation="LaTeX">$-2 \,\mathrm{V}$</tex-math></inline-formula> the best specimens exhibit an intrinsic electro-optic bandwidth of more than <inline-formula><tex-math notation="LaTeX">$40 \,\mathrm{G}\mathrm{Hz}$</tex-math></inline-formula>, which is reduced to about <inline-formula><tex-math notation="LaTeX">$10 \,\mathrm{G}\mathrm{Hz}$</tex-math></inline-formula> at zero bias. A comprehensive 3D multiphysics model, validated through the characterization campaign, provides design guidelines towards intrinsic bandwidths not only wider than <inline-formula><tex-math notation="LaTeX">$60 \,\mathrm{G}\mathrm{Hz}$</tex-math></inline-formula> at <inline-formula><tex-math notation="LaTeX">$-2 \,\mathrm{V}$</tex-math></inline-formula>, directly suitable for application in 200 Gbit/s systems, but also wider than <inline-formula><tex-math notation="LaTeX">$40 \,\mathrm{G}\mathrm{Hz}$</tex-math></inline-formula> at zero bias, not including the possible recourse to extrinsic parameter engineering.


TABLE I RESPONSIVITY AND CUTOFF FREQUENCY OF REPRESENTATIVE VPIN AND
LPIN DEVICES [8] is made more challenging by the constraint of limiting the power consumption of the data communication systems [9], [10].Ge-on-Si waveguide photodetectors (WPDs) are essential components of SiPh platforms, and it is urgent to assess the potential of competing WPD solutions in terms of their performance under low-bias operation.Comprehensive reviews of the state of the art of WPDs are provided, e.g., in [3], [8], [11], [12], [13]; the main figures of merit of a representative set of devices are reported in Table I.Ge-on-Si pin WPDs are based on either vertical (VPIN) or lateral (LPIN) heterojunctions.In the LPIN configuration, the Ge absorption region is located between two highly doped Si regions, n-and p-type, respectively [14], [15], [16], [17], [18], [19]; in the innovative approach presented in [20], thin FinFETlike LPIN WPDs have been shown to allow bandwidths f cutoff in excess of 200 GHz, though at the expense of the responsivity R.
For the more immediate future, however, it is important to fully exploit the potential of the widely used VPIN configuration, presently adopted also in the Cisco SiPh platform (see Fig. 1 for an example).VPIN WPDs having bandwidths larger than 50 GHz in the C-band have been already reported [21], [22], [23], [24], [25], [26], where this performance has been achieved mostly thanks to extrinsic parameter engineering, i.e., inductive gain peaking [27], [28], that may enhance the intrinsic frequency response of the WPD by 40% or more.
Fig. 1.Transverse (xy, top) and longitudinal (yz, bottom) cross sections of the VPIN WPD structure under study with its most significant geometrical parameters.The Ge absorber is grown on top of the Si substrate; top and lateral metallic contacts are placed on the absorber and on the substrate, respectively.Ge is considered to be intrinsic (green), with the exception of a n + layer resulting from ion implantation below the Ge-metal contact (yellow), while Si is heavily p-doped (blue).A 40 µm-long tapered waveguide (not shown) injects light into the substrate.
The present study is focused on the O-band, where Ge exhibits higher absorption with respect to the C-band.This results in a larger O-band responsivity, but also makes more challenging to achieve high-speed operation there, chiefly because of the stronger electric field screening caused by photogenerated carriers.Accurately describing this kind of three-dimensional (3D) multiphysics interaction requires a fully coupled analysis of electromagnetic and carrier transport phenomena.To our best knowledge, the intricacy and computational demands of such integrated 3D models have been addressed by only a few research groups so far [29], [30].
Extensive multiphysics simulations combined with experimental characterization of selected WPD variants can offer a deep understanding of the underlying physical processes, critical to develop guidelines for the design and optimization of integrated optical trasceivers that fulfill the demand of wide bandwidth and high power efficiency.Building upon our previous work [31], [32], [33], [34], [35], we demonstrate here that a multiphysics simulation framework is able to accurately describe the experimental dynamic behavior of the VPIN WPDs of the Cisco platform over a wide range of reverse voltage down to zero bias, and we use this numerical tool towards two goals: first, we propose an optimized design for a VPIN WPD that could be a promising candidate for a 200 Gbit/s receiver at a standard bias voltage of −2 V even without gain peaking; second, always focusing on the intrinsic electro-optic frequency response, we explore the device performance under low power consumption.
The paper is structured as follows.In Section II we discuss the nominal geometry of the WPD used as a reference structure, the experimental characterization techniques, and the multiphysics modeling approach.Considering the intrinsic electro-optic frequency response as the main figure of merit, the model is validated against experimental data in Section III, and is used in Section IV to identify design guidelines in order to achieve optimal performance.Last, Section V outlines future work and possible developments.

II. VPIN WPD GEOMETRY, CHARACTERISATION AND MODELING
We describe first the VPIN geometry taken as reference (Section II-A) and a set of its variants (Section II-B) whose properties will be studied in Section III.Then, we present our experimental setup and characterization techniques (Section II-C).Finally, we introduce the multiphysics CAD environment (Section II-D) whose validation and results will be discussed in next two Sections.

A. Nominal Geometry and Technology
All the VPIN WPDs considered in the present work consist of a Si substrate on which a Ge absorber having length L Ge , width W Ge and thickness H Ge is grown at low temperature [38].Fig. 1 provides transverse (xy) and longitudinal (yz) cross sections of the device, where the input optical signal propagates along z, highlighting the key dimensions and materials.Given the mismatch between the lattice constants of Ge and Si, the growth technique results in a thin defective layer at the Si-Ge interface.Above this layer, Ge can be considered as bulk.Since the defective layer thickness is small with respect to the total Ge thickness, the non-ideal Si-Ge interface can be treated according to [32].On top of and next to the absorber are metal contacts that reach Ge and Si, respectively.High dopant concentrations are present both in the substrate and at the metal-Ge contact, but most of the Ge absorber remains intrinsic.The n + layer in Ge is the result of an ion implantation process, determining a donor density 1 × 10 19 cm −3 in a region about 50 nm thick.The acceptor density in silicon decreases from 1 × 10 20 cm −3 at the metal contacts to 1 × 10 19 cm −3 under the Ge layer.This vertical configuration allows for a large contact area between Si and Ge.The absorber thickness H Ge plays a critical role in determining the transit time of the photogenerated carriers in the absorber [39], and therefore the frequency response of the detector.Compared to the lateral configuration, this arrangement makes the device speed generally less sensitive to other figures of merit such as the responsivity,1 so that vertical WPDs are ideal case studies for electro-optic bandwidth optimization (see also the discussion in Section IV).
For the structure taken here as reference, the Ge layer dimensions are L Ge = 15 µm, W Ge = 4 µm, and H Ge = 0.8 µm, whereas W doping = 3 µm is the lateral extension of the n + Ge implantation area.The Si layers, Ge implantation region, and metals are centered with respect to the Ge absorber.The cladding material is SiO 2 , and light is injected into the Si substrate through a 40 µm-long tapered waveguide.The resulting evanescent coupling between Si and Ge distributes light in the absorber more evenly than direct (butt) coupling, reducing the screening effects in the front section of germanium and enhancing the performance at high input optical power, albeit at the cost of a more complex electromagnetic design.

B. Variants
In addition to the reference structure, we analyzed different variants obtained by changing the absorber and doping implantation widths (W Ge and W doping , respectively) while keeping constant all the other parameters.Both reference and variants are referred to as Device n, where the reference is Device 2. In total, we characterized 28 devices belonging to 6 different design variants, thus comparing several nominally identical devices for each variant.A summary of all parameter combinations considered can be found in Table II, where the devices are sorted by W Ge and then by W doping .
Let us examine Table II.From Device 1 to Device 6, the Ge layer width W Ge varies from 4 µm to 1 µm.Device 1 and Device 2 (reference) have the same W Ge but a different lateral extent of the highly doped Ge region, W doping , and the same can be said for Device 3 and Device 4. Considering Device 5 and Device 6, they have comparable W doping /W Ge ratios but the latter has narrower W Ge and W doping .For all configurations, the width of the top metallic contact W metal and the maximum (final) width of the optical taper W taper are also reported.

C. Characterization
Static current-voltage characteristics I(V ) were measured on all devices under study, to determine the current both in dark (I d ) and under the same illumination conditions used in the ensuing radio-frequency (RF) characterization (I p ).As a representative example, Fig. 2 reports the static I d (V ) and I p (V ) curves for Device 2 (reference); in general, the dark current will not be a concern affecting our investigation of the design guidelines meant to optimize the frequency response.A 50 GHz Keysight Lightwave Component Analyzer (LCA) and a Keysight network analyzer [40] were used for the smallsignal RF device characterization, that began with measurements of the S-parameters in dark using the SOL method [41].This allowed to de-embed the contributions from the measurement pads, shifting the reference plane of the measurement from the pads to the metal contacts of the WPD.After this step, the characterization exploited the LCA to obtain the optical measurements of the S-parameters under monochromatic illumination with wavelength λ = 1310 nm.The performance of the waveguide in our system is described by its coupling losses and intrinsic waveguide losses.Coupling losses, indicating the efficiency at which light is transferred from the source to the waveguide, have been estimated between −2.7 dB and −2.2 dB.Waveguide losses, representing the attenuation of light as it propagates through the waveguide, range from −0.23 dB to −0.09 dB.
For each device geometry, measurements were made on four (or in some variants, five) nominally identical samples taken from different regions of the wafer under test, to explore unintentional deviations in the manufacturing process.Measured S-parameter data were normalized with respect to their lowfrequency value after Savitzky-Golay filtering [42].2Fig. 3 is an example of the electro-optic response on Device 2 (reference).The black curves are the unfiltered experimental values for each of five nominally identical devices at a bias voltage of −3 V, while the dashed blue curve is the result of the multiphysics simulation under the same conditions.A circuit with a resistive load of 50 Ω is considered in both simulation and measurements, and the electro-optic cutoff frequency f cutoff is defined as the frequency where the amplitude of the transfer function is reduced Fig. 3. Simulation (dashed blue curve) and measurements (black curves) of five nominally identical samples of Device 2 (reference), for a bias voltage of −3 V. by 3 dB vs. the low-frequency value.The measured curves are well reproduced by the simulation, whose f cutoff falls midway between the measured curves.A similar agreement is observed for all the device variants reported in Table II.
As the input waveguide mode propagates along a tapered waveguide and enters the photodetector, where the Ge absorber converts the light into electron-hole pairs, FDTD allows to compute the spatial distribution of the optical generation rate G opt (x, y, z) from the time-averaged divergence of the Poynting vector.As an example, Fig. 4 reports G opt in the Ge absorber of Device 2 (reference) for an input optical power 200 µW.Due to the multimode nature of the absorber, G opt displays an intricate interference pattern that results in pronounced local variations.It is evident that these 3D features cannot be captured by approximate propagation models, as they are not adequately represented by a simple exponential decay of the generation term along the absorber length.
G opt enters as a source term in the continuity equations of electrons and holes, which are solved self-consistently with the Poisson equation taking into account Fermi-Dirac statistics and incomplete dopant ionization.The gradual saturation of electron and hole velocities v n , v p for increasing electric field is described according to the Canali model [46], with a saturation velocity in Ge v sat ≈ 0.75 × 10 7 cm/s.As an example, the velocity of electrons (mostly photogenerated, under an input optical power 200 µW) is mapped in Fig. 5 for two values of the bias voltage.
As expected, the average velocity rises with increasing reverse bias.However, it's worth noting that, even in this scenario, the velocity displays a complex distribution that can be accurately captured only by a comprehensive 3D model.With the adopted approach, both the steady-state solution of the transport problem at equilibrium and under reverse bias, in dark and under illumination, as well as the small-signal electro-optic frequency response may be determined.

III. VALIDATION OF THE DESIGN ENVIRONMENT
Voltage scaling is mandatory to reduce both the static and dynamic power consumption in low-power applications.However, reducing the supply voltage may lead to a deterioration of the device performance.As a preliminary critical step towards addressing this issue with the help of multiphysics modeling, an extensive validation of the model against experimental data has been performed.
After calibrating the input optical power P tot as described in [47], we plotted the experimental f cutoff as a function of the bias voltage for all variants (Device 1...6) with P tot = 200 µW.As discussed in [47], this optical power level does not induce significant screening effects, that in general could affect the frequency response by reducing the velocity of photogenerated carriers.
We used then the multiphysics model to obtain the corresponding simulated f cutoff for all geometries and operating conditions.The results, collected in Fig. 6, show the accuracy of the description provided by the model.Each of the six boxes corresponds to a different Device as described in Table II and reports several experimental curves corresponding to nominally identical devices.In all six cases, the experimental value of f cutoff increases monotonically with reverse voltage, reaching an electro-optic cutoff frequency of about 40 GHz or higher.The same behavior is reproduced by simulations, that always follow within 2 GHz one of the experimental curves of the considered group.
By reducing the bias voltage from −1.5 V to −0.8 V, a decrease of f cutoff between 5 GHz and 10 GHz is observed depending on the geometry, but f cutoff never becomes lower than 30 GHz.When the bias voltage is set to zero, f cutoff drops more significantly, but even at zero bias all devices have a cutoff frequency close to 10 GHz.Our multiphysics approach is able to reproduce with very good accuracy the behavior of the frequency response for decreasing bias, difficult to predict with approximate models not based on a detailed 3D description of the device.

IV. DESIGN GUIDELINES
From the results of our simulation campaign, we summarize in this Section some design guidelines that can lead to the development of Ge-on-Si VPIN WPDs compatible with 200 Gbit/s communication systems, i.e., with a bandwidth in excess of 60 GHz, even without recourse to extrinsic parameter engineering.
The first guideline regards the width of the doping implantation region at the metal-Ge contact.From Fig. 6

one may
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.observe that Device 1 has a wider bandwidth than Device 2, and the same can be said for Device 3 with respect to Device 4. Each pair has the same W Ge but a different W doping , as reported in Table II, and a better performance is observed when the ratio W doping /W Ge is closer to 1.In general, one should aim at a dopant implantation area which extends as much as possible to the whole upper surface of the absorber, since in the ideal case W doping ≈ W Ge one would observe an almost vertical electric field everywhere in Ge, favorably impacting the carrier velocity distribution.
Additional recommendations come from a set of simulations focused on the effects of W Ge and H Ge on f cutoff and R, for different values of the bias voltage in the interval [−2, 0] V. Fig. 7(a) shows the variation of f cutoff for W Ge ∈ [1,6] µm, while all other dimensions are given the values of Device 2 with the exception of W doping , which is changed in order to keep the ratio W doping /W Ge constant.The bandwidth dependence on W Ge observed in Fig. 7(a) is weakly non-monotonic, and f cutoff reaches a maximum for W Ge ≈ 3 µm.
The effect of H Ge is more significant, as shown in Fig. 7(b), where f cutoff is reported for H Ge ∈ [0.2, 1.2] µm, while keeping all other dimensions as in Device 2. Fig. 7(b) suggests that reducing H Ge should prove convenient, since an electro-optic cutoff frequency above 60 GHz is obtained for H Ge = 0.3 µm at a bias voltage of −2 V.
The behavior of f cutoff as a function of W Ge and H Ge in Fig. 7 is qualitatively consistent with the closed-form study in [39], where the transit time and the parasitic RC product are presented as the two main elements that limit the bandwidth.For the device under study, when H Ge is decreased from 1.2 µm to 0.3 µm, the Fig. 6.Experimental values of f cutoff as a function of the bias voltage for the six device variants whose geometry is reported in Table II (dashed lines), compared with the corresponding simulated curves obtained with calibrated P tot (black solid lines).The horizontal red dashed lines correspond to the (bias-independent) transit-time limit according to the closed-form model of [39,Sec. 4.10.1].
bandwidth becomes wider according to f cutoff ∝ v sat /H Ge as a result of a reduction of the transit time, which is the limiting factor in this region of the parameter space [39, Sec.4.9.3].Conversely, when H Ge is further decreased below 0.3 µm, the observed bandwidth reduction can be attributed to the RC product, since f cutoff ∝ H Ge /S [39, Sec.4.9.4],where S is the Ge detector area in the xy plane.
The detector geometry corresponding to the maximum value of f cutoff is determined by the interplay between transit time and RC limits.However, when aiming at an overall device optimization, a careful balance is required to achieve high-speed operation while preserving light detection efficiency, a critical requirement for limiting the power consumption of SOI platforms.For this purpose, Fig. 8 allows to assess the impact of W Ge and H Ge on the detector responsivity. 3From Fig. 8(a) one may observe that the nominal H Ge of Device 2 is near-optimal, since the marginal increase in f cutoff that could be achieved by reducing the absorber width would be accompanied by a 12-15% decrease of R. Conversely, Fig. 8(b) shows that halving the absorber thickness from 0.8 µm to 0.4 µm would provide an increase of about 25 GHz to f cutoff at the cost of a 9% penalty on R. Remarkably, a device with W Ge ≈ 4 µm and H Ge ≈ 0.4 µm should have an intrinsic bandwidth larger than 40GHz even at very low or zero bias, which promises the possibility for an optimized device to operate at high speed with very low power consumption.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

V. CONCLUSION
We have discussed the characterization and modeling of Geon-Si VPIN WPDs for data communications with the aim of maximizing their intrinsic frequency response in the O-band.Six device variants were manufactured, and their characterization showed that, with two exceptions, all variants achieved an electro-optic bandwidth of 40 GHz or more at λ = 1310 nm for a reverse bias of −2 V.
The experimental results were used to validate a numerical model combining 3D electromagnetic and electrical transport simulations.Since the multiphysics model was able to reproduce the experimental behavior with good accuracy, an extensive simulation campaign was carried our to identify design guidelines leading to maximum bandwidth with minimum power consumption.This campaign enabled the determination of values for W Ge , W doping , H Ge that should provide the best performance from a trade-off between transit time and capacitive effects.The model predicts, at zero bias, a maximum intrinsic bandwidth close to the remarkable value of 45 GHz, allowing to employ Ge-on-Si VPIN WPDs in SOI platforms with reduced power consumption.Using a higher but moderate bias voltage (e.g., −2 V), a cutoff frequency larger than 60 GHz is expected, and the 4-level Pulse Amplitude Modulation (PAM-4) coding scheme should enable data transmission in excess of 200 Gbit/s.
The validated model will be employed to extend the investigation of the detailed behavior of microscopic quantities, such as the velocities of photogenerated carriers, and will support further performance improvements also by including a microscopic description of carrier transport through direct full-band Monte Carlo simulation [49].

Fig. 2 .
Fig. 2. Experimental I(V ) characteristics of a sample of Device 2 (reference) in dark (blue line) and under 0 dBm illumination (orange line).

Fig. 4 .
Fig. 4. Optical generation rate G opt (x, y, z) (cm −3 s −1 ) in the Ge absorber of Device 2 for an input optical power 200 µW.(Left) Transverse (xy) cross section for z = 1.8 µm, where z is measured from the beginning of the absorber.(Right) Longitudinal (yz) cross section for x = 0 (corresponding to the device center) and z ∈ [0, 5] µm.

Fig. 5 .
Fig. 5. Magnitude of the electron drift velocity normalized with respect to the saturation velocity, |v n (x, y, z)|/v sat , in the transverse (xy) cross section of the Ge absorber of Device 2 at z = 1.8 µm for an input optical power 200 µW.(Left) −2 V bias voltage.(Right) Zero bias voltage.

Fig. 8 .
Fig. 8. Dependence of R on (a) W Ge and (b) H Ge , starting from Device 2 (vertical dashed-dotted line), for input optical power 200 µW and bias voltage −2 V. On the present plot, the values of R at lower bias (−1 V and 0 V) would be superimposed to the reported data points.

TABLE II GEOMETRICAL
PARAMETERS OF THE DEVICES UNDER STUDY (SEE FIG. 1).DEVICE 2 CORRESPONDS TO THE NOMINAL GEOMETRY (REFERENCE).FOR ALL DEVICES, L GE = 15 µm AND H GE = 0.8 µm, EXCEPT FOR DEVICE 6 WHERE L GE = 18.5 µm.THE LAST COLUMN REPORTS THE SIMULATED RESPONSIVITY AT A BIAS VOLTAGE OF −3 V AND INPUT OPTICAL POWER 200 µW