Crosstalk-Free 32-ch DWDM Demultiplexer On Standard Si Pic Platform Enabled By Fully-Integrated Cascaded AMZ Triplet

Enabled by an autonomous calibration mechanism, crosstalk-free (−38.5 dB) fabrication-tolerant 32-ch DWDM demultiplexer on a standard Si PIC platform is demonstrated for the first time. On this platform, due to its nano-sized waveguide core dimensions, extremely precise fabrication control of waveguides has been required so far to suppress the crosstalk of demultiplexers for large-channel-count DWDM systems. This requirement made this platform impractical for such systems. To exclude this requirement, we have proposed a calibration mechanism which can be fully integrated into an assembly composed of an electric IC (EIC) and a standard Si PIC. The Si PIC has a structure of cascaded asymmetric Mach-Zehnder (AMZ) triplet consisting of AMZ interferometers designed to function as a demultiplexer. This structure enables monitoring the errors in the optical lengths of waveguides composing itself. Based on the monitored values, the controller implemented on the EIC determines the driving conditions of waveguide heaters to eliminate the errors. This feature excludes the necessity to strictly control the optical lengths in the fabrication process, making it possible to realize a crosstalk-free 32-ch DWDM demultiplexer on a standard Si PIC platform. Compatible with the vast component libraries of standard Si PIC platform, this device provides a path to ultrahigh-capacity integrated DWDM transceivers.

systems and intra-data center networks as well as communication networks in wider ranges, importance of increasing transceiver capacity density is growing rapidly. For high density integration to meet the demand in several years, applying Si nano-waveguide (NW) photonic integrated circuits (PICs) having high waveguide index contrast and small core thickness of a few hundreds of nanometers is crucial. Furthermore, to accommodate such high capacity demand against limited space allocated for optical fibers around the PICs, increasing per-fiber capacity is essential. Considering the end of CMOS scaling and energy efficiency, resolving on increasing per-λ capacity is approaching the limit. Thus, increasing WDM channels has a potential to become one of the most effective ways for this purpose.
Furthermore, co-packaging Si PIC transceivers with heatgenerating electric integrated circuits (EICs) such as graphics processing units (GPUs), switches, and digital signal processors (DSPs), also expected to become crucial to satisfy the capacity demand in several years, inevitably causes dynamic temperature changes of WDM components, making DWDM even more impractical. An approach to these challenges is correcting fabrication-and temperature-induced errors with phase shifters. It was introduced to demultiplexers using rings [20], [21], [22], cascaded asymmetric Mach-Zehnder (AMZ) [23], [23], and arrayed waveguide grating (AWG) [24]. Rings have calibration algorithm simple enough to be implemented in a compact EIC, and recently 8-ch demultiplexer was successfully demonstrated [22]. This would be a good choice for WDM signals having a moderate frequency range, N ch Δf (N ch : channel count, Δf: channel spacing). When N ch Δf is increased, however, it causes a reliability issue; required tuning range of >N ch Δf causes a temperature rise of e.g., >190 K for 50 GHz-spaced 32-ch WDM. This is far beyond the common reliability limit, causing controversy over practicality in such high capacity WDM applications. Coupled rings with different radii exploiting Vernier effect can avoid this problem as well as increase the channel isolation [25], where the calibration was performed based on a pre-calibrated look-up table with elaborate care for thermal crosstalk. This scheme successfully achieved channel isolation of >35 dB with a 1-ch add-drop filter [25]. While it has not yet been demonstrated, this could be a potential candidate once shown to be scalable. Although cascaded AMZ and AWG are also candidates for these applications, any practical way has not been demonstrated to automatically correct errors so far. Therefore, WDM channel counts available on Si NW PICs were limited so far. To overcome this, we proposed a novel demultiplexer having cascaded AMZ triplet (CAT), where errors are corrected autonomously with a simple and power efficient electric circuit [26], [27], [28], which had been impossible with conventional cascaded AMZ demultiplexers due to lack of ways to monitor the errors [26]. With a 4-ch CAT, we have demonstrated zero power penalty [27] and error-free demultiplexing under a dynamic temperature change as occurring in co-packaged transceivers [28].
High degree of scalability is another notable advantage of CAT; because an AMZ triplet functions as a WDM deinterleaver, CAT can increase channel count simply by adding stages of AMZ triplets without complexifying the control circuit [26]. In this paper, we demonstrate this feature as the first ever demonstration of 32-ch DWDM demultiplexer on standard Si PIC platform.

II. CROSSTALK-FREE 32-CH DWDM DEMULTIPLEXER ON
STANDARD SI PIC PLATFORM Fig. 1 shows a schematic of CAT demultiplexer implemented in a PIC+EIC assembly shown in Fig. 2. PIC and EIC were fabricated using 200-nm SOI PIC and TSMC 180 nm CMOS technologies, respectively. PIC consists of circuits using Si waveguides having a core size of 350 × 200 nm. It has 31 AMZ triplets connected in a binary tree structure of depth 5, each consisting of 3 identical AMZs, thus having 93 AMZs in total. The periods of the sinusoidal transmissivity spectra were designed to be 100, 200, 400, 800, and 1600 GHz for the AMZs of the depth-1, −2, −3, −4, and −5 nodes in the binary tree, respectively. To obtain these periods, the arm length differences were set at 665.6, 332.8, 166.4, 83.2, and 41.6 μm, respectively. Because AMZs have zero dispersion of group delay, that for the entire structure is also zero. Based on the measured loss values of 0.2 dB for 2 × 2 multimode interference (MMI) couplers, the insertion loss of each AMZ is expected to be 0.4 dB at the transmissivity peak. The insertion loss of each AMZ triplet is estimated to be 1.02 dB as a sum of 0.8 dB loss by 2 AMZs and 0.22 dB loss by a 5% tap coupler. Each AMZ has a pair of 440-Ω resistive heaters. EIC consists of a supervisory controller and 93 control elements (CEs).
Each CE drives the heater pair to increase or decrease the photodiode (PD) currents. Only one of the heaters is driven at a time. Noise equivalent power of the PD input was designed to be <1 nW.
Pulse width modulated (PWM) signal is used to drive heaters (Fig. 3), which reduced the power overhead of drivers down to only 2.8%. This had a 1-μs repetition period and 100 levels of pulse widths. When triggered by the supervisory controller, a CE performs a cycle of dithering-based control sequence: 1st step is dithering pulse width between 2 slightly different values by a heater controller, and storing the corresponding 2 voltages from the monitor into a sample and hold circuit (S & H); 2nd step is comparing the stored values by a comparator (Comp), output of which is used by the heater controller to determine whether the pulse width should be increased or decreased before moving to the next cycle. Supervisory controller repeats triggering this control cycle over all CEs at an interval of 2 ms. 1.8-and 3.3-V power supplies, 100-MHz clock, and Serial Peripheral Interface (SPI) for sending supervisory commands and reading status, are the only electrical connections to the assembly. Further details of control algorithm are given by ref. [26]. A 50-GHz-spaced 32-ch DWDM signal was launched into the input port, and the entire part of the CAT was controlled simply by increasing or decreasing the value of each PD current as in the algorithm implemented in the controller shown in Fig. 3. Fig. 4(a) is the spectra obtained before error corrections, where we can observe no periodic transmissivity peaks. With a progress of the error corrections, distinct peaks appear and their values increase as shown in Fig. 4(b) and (c). With a further progress, periodicity in the transmissivity spectra becomes clearer as shown in Fig. 4(c) and (d). Fig. 4(e) is an enlargement of the dashed area in Fig. 4(d), showing enhanced isolation at the transmission peak as a result of error corrections. Fig. 5 shows temporal changes in pulse widths for 93 CEs during error correction process. The progress of error correction causes rapid changes in pulse widths, which are stopped after all errors have been corrected. As indicated by Fig. 4(d), this simple control algorithm is effective in realizing autonomous and complete error corrections, and it is highly scalable and applicable to channel numbers of as large as 32.

IV. EXPERIMENTS
With a 50-GHz-spaced 32-ch DWDM signal launched into the input port, EIC operation was started. Fig. 6 shows temporal changes in pulse widths for 93 CEs occurring as a result of the control sequence.
After a rapid change for several seconds due to the progress of error correction, all pulse widths became static indicating initial correction had been finished. This reproduces the result of numerical calculation shown in Fig. 5. The control sequence was continued to dynamically compensate changes occurring after the initial error correction, such as those of PIC temperature as demonstrated in [28], signal wavelengths, heater efficiencies, etc. At the finish of initial correction, the overall power consumption of the controller EIC was measured to be 1270    mW, which was broken down into 1150 mW for digital drivers and monitors, and 120 mW for the logic. This corresponds to average power consumption per CE of 13.7 mW (12.4 mW for a digital driver and monitor, and 1.3 mW for the logic). Power consumption for monitors has still much room for reduction, because presently every CE has a monitor circuit, which can be shared by AMZs. Also improvements of heater efficiency would directly contribute to decreases in power consumption of digital drivers due to negligible power overhead of the drivers. Fig. 7 shows measured spectra of demultiplexed signals obtained from the 32 output ports with unmodulated on-grid 32-ch WDM signal launched from the input port. It should be noted that the power contrast between the signal peaks and crosstalk components was as large as 43.8 dB. Fig. 8 shows 1-ch crosstalk, total crosstalk, and transmissivity of the demultiplexer for all the channels derived from the values of signal and crosstalk peaks in Fig. 7. 1-ch crosstalk and total crosstalk are defined as the crosstalk power of the worst channel, and as the ratio of sum of all crosstalk powers to the signal power, respectively. The total crosstalk power was evaluated to be  −38.5 dB for the worst port. For standard Si PIC platforms, this value is strikingly low and unprecedented. To our knowledge, this is the smallest even in comparison with all kinds of Si PIC demultiplexers ever reported. The average of loss values was evaluated to be 9.8 dB. Fig. 9(a) shows the spectrum of 32-ch 25-Gb/s DWDM signal having non-return-to-zero 2 31 -1 pseudorandom binary sequence (PRBS) format. 32-ch continuous-wave light was collectively modulated by a lithium niobate modulator and amplified with a praseodymium-doped fiber amplifier. To decorrelate the  modulation patterns among the 32 channels, the modulated light was transmitted through a 1-km dispersion shifted fiber as a dispersive medium. Fig. 9(b) shows the spectra of demultiplexed signals obtained from all 32 output ports.
For all demultiplexed signals, we measured eye diagrams as shown in Fig. 10 and bit error ratio vs. optical signal-to-noise ratio (SNR) as shown in Fig. 11, all of which successfully reaching 10 −12 level. The bitrate would be further scaled by using higher symbol rates and/or more advanced modulation formats combined with DSPs. V. BENCHMARKING Fig. 12 shows comparisons with other demultiplexers on standard and non-standard Si PIC platforms. As shown in Fig. 12(a), the loss value is similar to or better than those in the trend of standard Si PIC. With a smaller coupler loss as demonstrated in [29], it would be potentially reduced to ∼2 dB ( = 0.1 dB/coupler × 4 couplers/stage × 5 stages).
As depicted by blue circles, the total crosstalk of standard Si PICs drastically increases both with an increase in channel count ( Fig. 12(b)) and with a decrease in channel spacing (Fig. 12(c)). As the red circles indicates, the total crosstalk is drastically reduced with CAT, especially for large channel counts and small channel spacings. While using thicker silicon on insulator (SOI) substrates reduces crosstalk, it loses compatibility with the extensive component libraries of standard Si PIC platforms. It should also be noted that the remarkably small crosstalk of CAT was obtained with autonomous calibration by a fully integrated controller as opposed to other demultiplexers capable of error corrections as in refs. [23], [24].

VI. POWER CONSUMPTION FOR TEMPERATURE TOLERANCE
In this section, we estimate the effect of temperature change on the power consumption of EIC. Defining Δ∅ I as an initial phase error of an AMZ wrapped into a range of −π to +π, E(|Δ∅ I |) (E indicates expected value) becomes π/2 assuming that the fabrication error is so large that Δ∅ I takes values in the range with an equal probability. Because heater power required to correct error, Δ∅ I is given by P I = |Δ∅ I | P 2π /2π, where P 2π is heater power required for 2π phase shift, E(P I ) becomes P 2π /4. Multiplied by the number of AMZs, 3(N ch − 1), the expected value of the total heater power required for initial phase error becomes For an AMZ having free spectral range of f F SR , heater power, P T required to correct the phase errors caused by temperature change, ΔT can be expressed by where dλ/dT is temperature coefficient of wavelength shift, which is ∼0.07 nm/°C on standard Si PIC platforms. f F SR of depth-i AMZ (AMZ located at depth-i nodes of the binary tree) is 2 i Δf . Therefore, P T for depth-i AMZ can be expressed by ΔT P 2π (i = 1, . . . , log 2 N ch ) .
Total heater power, P T,total required to correct all the temperature-induced errors can be expressed by (2) Fig. 13(a) and (b) show P I,total and P T,total normalized by N ch P 2π for Δf of 50 and 100 GHz, respectively, both calculated by using eqs. (1) and (2) under ΔT values of 50 and 100°C. According to eq. (2), P T,total /N ch P 2π is proportional to ΔT /Δf . Therefore, among 4 combinations of Δf and ΔT in Fig. 13, Δf = 50 GHz and ΔT = 100°C in Fig. 13(a) leads to the largest values of P T,total /N ch P 2π . Even under this condition, P T,total is only 144% of P I,total at N ch of 32, indicating that the temperature changes have only a limited impact on total power consumption.

VII. CONCLUSION
Enabled by fully autonomous controller-integrated cascaded AMZ triplet, we have successfully demonstrated crosstalk-free (< −38.5 dB) 32-ch DWDM demultiplexing on a standard Si PIC platform for the first time. Together with integrability with vast component libraries of standard Si PIC platform and applicability to temperature-changing co-packaged optics, crosstalk-free nature accelerates to realize highly demanded high-capacity integrated DWDM transceivers.