Coupling of Photonic Waveguides to Integrated Detectors Using 3D Inverse Tapering

We report on the design, fabrication, and characterization of a Silicon Nitride (SiN)-based integrated photonic chip in which the dielectric waveguides are coupled to photodetectors integrated homogeneously into the Silicon substrate. The photonic-electronic coupling was realized by a 3D inverse tapering of SiN waveguides. The novelty of our approach consists in tapering the waveguide in the vertical direction by means of an engineered wet chemical etching. This allows for a smooth transition from a full-height to an arbitrarily thin waveguide thickness at the detector location, expanding adiabatically the optical mode towards the latter. The measured chips showed a responsivity $R\approx 109\;\mu$A/mW and a corresponding quantum efficiency of 16% at an excitation wavelength of 850 nm. Our technological solution offers a versatile method for a top-down monolithic integration of lightwave circuitries with substrate-located photon sensing devices.


I. INTRODUCTION
I N RECENT years Photonic Integrated Circuits (PIC) experienced enormous growth [1]- [3]. By sharing a large common basis with the mature semiconductor technology, silicon and silicon nitride materials are used to fabricate photonic devices within CMOS facilities, permitting the development of PICs in well-established fabrication plants.
Integration of PICs with photon detectors requires a coupling scheme to transfer the optical power from the waveguide to the detector region. Recently, several strategies have been developed to couple photonic and electronic components for example with SiGe detectors [4] mainly in SiN, SOI and SIN/SOI platforms, as summarized In Table I. This has become an important topic, especially to foster emerging quantum technologies where the coupling efficiencies with external detectors hampers the development of quantum  integrated photonic circuits, and thus research toward integrated solutions is thriving [12]- [15].
This work demonstrates a novel approach to inverse tapering which enables the coupling of SiN waveguide to a Si photodetector integrated in the substrate.
The conventional approach for the realization of an inverse tapering consists in reducing the waveguide width during the pattern definition stage. While this option does not require additional fabrication steps, it is often challenging to reduce the waveguide to an arbitrarily small width without incurring in lithographic limits on critical dimensions. Here, we exploit a chemical wet-etching process to reduce locally the cross-section of the waveguide in the vertical direction (Fig. 1). This, combined with conventional lateral tapering, enables a complete This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 3D inverse tapering that allows the waveguide losses towards the substrate to be locally enhanced in the region where the photodetector is located. Our approach is largely independent on the lithographic constraints on the waveguide. The fabricated devices show up to 16% quantum efficiency at NIR wavelengths, subject to large improvements upon further optimization of the fabrication process.
The paper is structured as follows: in Section II, we describe the device concept and simulations used to design it. Section III illustrates the fabrication process. In Section IV, the optical and electro-optical characterization of the device are discussed. Finally, Section V summarizes the results and draws conclusions.

II. NUMERICAL SIMULATIONS
Our approach to waveguide-detector coupling exploits the mode expansion by inverse tapering which allows the optical mode to leak efficiently into the substrate at the detector position. This can be achieved by tailoring the waveguide dimensions from a large cross-section to a weakly guiding small-core one by reducing the thickness of the waveguiding layer, as sketched in Fig. 1(d). The technique used for a shallow-angled wedge formation on thin films is used to shape photonic structures in the vertical dimension, allowing the creation of a smooth transition between two regions in the same photonic layer having different thicknesses [16]- [18]. Such transition in the vertical direction can be eventually paired with an in-plane tapering by using standard lithographic techniques to create a complete 3D tapering of the waveguide.
The device under study consists of an electronic-photonic integrated circuit structured as follows. The epitaxial Silicon substrate hosts the photodetectors, formed by ion-implanted p-n junctions. The photonic layer is formed on top of the substrate and consists of single-mode waveguides which allow for guided mode propagation without losses towards the substrate. At the location of the p-n junctions, the light is transferred from the waveguide to the underlaying photodetector via 3D inverse tapering of the waveguide. While our numerical simulations are performed for SiN-based single-mode channel waveguides, the method described here is general and can be extended to other photonic material platforms and waveguide geometries. Numerical simulations, performed using the Finite Elements Method (FEM), allow to obtain the geometrical parameters and the modal characteristics of the waveguides. In particular, the channel waveguides of 300 nm height and 700 nm on top of ∼ 1 μm SiO 2 bottom cladding allow for single mode propagation with low loss towards the Si substrate ( Fig. 2(a)). Fig. 2(b) shows the small core region after the tapering, where most of the mode energy is squeezed out of the core of the waveguide down into the substrate-integrated photodetector with a corresponding loss of 2400 dB/cm. In this case the waveguide width and the height are reduced to 500 nm and to 75 nm, respectively. Fig. 2(c) shows the distribution of the electromagnetic field intensity in the transverse cross-section of the waveguide. In this case, light propagates from the thick waveguide on the left towards the small waveguide on the right, passing through the wedge transition. Underneath the thin portion of the waveguide, the light is collected within the active region of a photodiode. The complete inverse tapering case, where the waveguide thickness is brought down to zero, is shown in Fig. 2(d). Here, above the photodetector, the light is essentially confined within the top SiO 2 cladding and the highly absorbing Si substrate.

III. DEVICE FABRICATION
The devices were fabricated starting from 6-inch epitaxial Si substrates in which, first, the photodetectors were realized by ion implantation of Phosphorous and Boron to form the p-n junctions. The photodetectors have an elongated shape following the waveguide trace in order to permit an efficient collection of the evanescent light field within an extended region. Fig. 3(a) shows the CAD layout of the detector region, where the Phosphorous and Boron doping regions are visible highlighted in red and blue, respectively. On top of the Si substrate, a 1050 nm thick bottom SiO 2 cladding layer of is deposited in order to isolate the PIC from the substrate (see the sketch in Fig. 1(a)). Next, the wafer is covered with a 7 nm thin film of Si 3 N 4 via Low-pressure Chemical Vapour Deposition (LPCVD) to realize an etch-stop layer, the utility of which will be explained in the following. Then, a SiN film of 300 nm is deposited via Low-frequency (380 kHz) Plasma-enhanced Chemical Vapour Deposition (PECVD) to form the the photonic device layer ( Fig. 1(b)). At this stage, the definition of the vertical tapering is realized by opening a window in the photoresist at the location of photodetectors and wet etcing the SiN film in a buffered HF solution (BHF) (Fig. 1(c)). While the wet etching consumes slowly the SiN film isotropically, at the same time, the BHF erodes progressively the interface between the photoresist film and the SiN layer, promoting an additional etching front at the photoresist-SiN interface. For appropriate combinations of the etched material, the adhesion promoter and the curing process of the photoresist, the etching speed along the photoresist-SiN interface can be made faster than the isotropic etching rate of the SiN film itself. This situation generates a triangular-shaped etching front, producing the wedge-shaped transition shown in Fig. 1(c). We have produced different wafers in which the SiN film was either thinned down to 75 nm or eliminated completely to form a complete inverse tapering. The latter situation can be achieved precisely due to the presence of the etch-stop Si 3 N 4 film which prevents ethcing of the bottom SiO 2 cladding. The procedure, physics, and mathematical description of the wet-etching process are described in more detail in [19], [20].
After the realization of the wedge tapering, the waveguides were patterned with i-line stepper lithography and reactive ion etching (RIE), shown as purple lines in Fig. 3(a). Then the waveguides were treated thermally at 975 • C for 1 h in an N 2 atmosphere to release the residual hydrogen from the PECVD film, and to activate the doping in the epitaxial substrate. Next, the wafer was covered with another 7 nm thick LPCVD Si 3 N 4 , followed by a deposition of 1 μm thick Tetraethylorthosilicate (TEOS) SiO 2 which acts as a top cladding (Fig. 1(d)).
The wafer was then patterned with stepper lithography to realize vias through the top cladding, the intermediate Si 3 N 4 film and the bottom SiO 2 to allow the deposition of metal contacts in the doped regions. The vias were formed via Deep RIE. Additional non-contacting vias were etched in various regions of the chips close to the waveguides and the detectors, which were later filled with Aluminium to form barriers for stray light travelling in the oxide layers. The wafer was then Fig. 4. The quantum efficiency of the diodes exposed to a normal illumination from an external spectral source. The spectral features with ≈ 50 nm of period are due to thin-film interference of the cladding covering the photodiode. covered with a 1.2 μm thick layer of Al-1% Si alloy, sputtered at 200 • C, in order to contact the p-n junction. The metallic film was patterned into wires and contact pads via lithography and defined with RIE. Fig. 3(b) shows an optical micrograph of the realized device. It's worth noting the elongated shape of the Aluminium vias that form a mirror-cage in the cladding all around the photodetector region except in the proximity to the waveguides. Finally, the diced chips were wire bonded to PCB boards for optical/electrical characterization. Fig. 3(c) and Fig. 3(d) show two devices with bonded electronics, with thinned waveguide and complete inverse tapering, respectively. The light here is injected into the waveguide from the top part of the figure towards the bottom.

IV. MEASUREMENTS
First, the photodiodes were characterized for normal incidence responsivity, that is, from external illumination from an external source directly impinging on the detector surface. The current at −1 V bias, generated by excitation from a spectral lamp, was measured and power-normalized with a calibrated detector. Fig. 4 shows the spectral responsivity to normal incidence of four photodiodes. The responsivity remains substantially identical for the different devices, with spectral features with a period of ≈ 50 nm due to thin-film interference of the cladding film on top of the photodiode. We have investigated the waveguide-coupled quantum efficiency (Q.E.) at a wavelength of 850 nm, where the PIC is expected to operate. However, the responsivity of the silicon detectors is higher at shorter wavelengths, and thus the method is more efficient for devices operating with visible light.
Next, the devices were tested for excitation from the integrated waveguide by using the setup shown in Fig. 5(a). Light from a laser diode emitting at 850 nm is injected into the waveguide using a tapered lensed fiber. The light travels in the waveguide until it reaches the region above the detector. Here, the waveguide geometry is varied to expand the mode profile into the underneath detector, where a photocurrent is generated and measured with the sourcemeter. After the detector region, the waveguide cross-section is tapered back to its original dimensions. The residual light is then collected at the output facet with another tapered lensed fiber and sent to an external Si detector. In order to estimate the Q.E. of the photodetectors with respect to the PIC we have estimated the light power in the waveguide right before the coupling region with the photodetector. This estimation is realized by subtracting from the calibrated 5 mW source the optical losses that occur in the chip before the detector. Optical losses are mostly due to the insertion loss at the input fiber-to-waveguide coupling interface and the propagation loss in the waveguide from the edge of the sample to the detector region.
Both insertion and propagation losses were estimated via cut-back method on a twin chip, realized on the same wafer next to the one hosting the photodetectors. On the testing chip, spiral waveguide structures with lengths from 0.5 cm to 6 cm were present, allowing for a loss estimation through Beer-Lambert law fitting of the transmission data. Fig. 5(b) represents the propagation loss data samples for both transverse-electric (TE, blue) and transverse-magnetic (TM, red) input polarizations. While TE polarization exhibits slightly lower propagation loss, the devices are expected to show better operation in TM polarization, where the coupling towards the substrate is higher, and hence the generated photocurrent is larger. Once the propagation losses are estimated, the detector responsivity is measured with the setup shown in Fig. 5(a). This time, variable optical power is injected into the optical waveguides coupled to the detectors. The optical power before the detector, P in , is calculated by subtracting insertion and propagation losses inside the chip from the laser power, which is monitored with a calibrated power-meter (S120VC). For each level of input optical power an IV-curve is measured on the detector, as shown in Fig. 6(a). In Fig. 6(b) we plot the generated photocurrent I ph at −1 V bias as a function of the input optical power P in . From fitting the data with a linear regression, the responsivity R = I ph /P in of the detector can be estimated, which in our case is 0.109 A/W. The quantum efficiency of our devices has been estimated as Q.E. = I ph /P in × hν/e where h is the Plank constant, ν is the frequency of the photons and e is the elementary charge. From the measurements, the Q.E. of the device resulted as high as 15.9%, which is very close to the predicted 16.7% from FEM simulations.
We have also characterized chips with complete inverse tapering ( Fig. 2(d)). Here, the light diffuses into the SiO 2 cladding, which can be appreciated from the optical image shown in Fig. 3(d). The photodetector still absorbs the light trapped in the cladding, but at a slower rate. In this case, an efficient coupling in the active region is ensured by caging the light with deep trenches filled with metal which act as mirrors. Thanks to the lateral confinement provided by the metal cage, these devices achieve a Q.E. of 15.4%, similar to that of the thinned waveguides.
We note, that the measured responsivities are comparable with the state-of-the-art R's in waveguide-integrated photodetectors, which are typically of the order of 0.3 A/W [5]- [7]. Here, the lower values of R can be explained by the fact that the absorbance value of the realized devices is mostly limited by the thickness of the epitaxial layer, which is 3 μm in our devices. The epitaxial layer, determines the detector's active volume where the photogenerated electron-hole pairs are collected. Even though the light couples to the substrate from a waveguide parallel to the surface, Snell refraction bends the light to about 60 • with respect to the SiN/Si interface, thus reducing the optical path within the active layer to approximately 3 μm /sin(60 • ) ≈ 3.5 μm. In fact, in Ref. [5], which uses a 10 μm epitaxial Si, an R ≈ 0.3 A/W has been demonstrated. Nevertheless, as in the case for the devices described in [5], this issue can be mitigated with the use of thicker epitaxial layers or with back-side reflector strategies.

V. CONCLUSION
The geometries we tested for substrate-coupling of the light at the end of a PIC show promising results to be used in integrated devices fabricated with optical lithography, especially where monitor photodiodes are required. Our coupling strategy provides a simple reliable coupling method which is broadband, resolution-insensitive and robuts to fabrication toleracies. We believe that our method could provide an excellent alternative to grating couplers that, being essentially resonant structures, are bandwidth-limited and sensitive to fabrication tolerances. In particular, the vanishing-waveguide variation is efficient for short-wavelength applications where a thick oxide impedes the evanescent coupling and the definition of a grating coupler is particularly challenging. With respect to other approaches developed for waveguide-photodetector coupling, the technology described in this paper permits an independent development of arbitrary electronics within the epitaxial Si substrate, followed by an integration of arbitrary PIC architecture on top of the substrate. The future perspective is to use this technology to couple SiN photonic circuitries with single-photon avalanche diodes [21] in order to make a step forward towards the development of VIS-NIR operating quantum photonic platform in silicon. He has authored or coauthored more than 240 research papers on international conferences and journals in the area of ultra-low-power embedded systems, energy harvesting, and power management of VLSI circuits. His research interests include IoT and distributed lightweight unmanned aerial vehicles UAV, the development of new techniques of energy scavenging for low-power embedded systems, and energy-neutral wearable devices. He was leading industrial cooperation activities with TIM Italia, Rome, Italy, ENI, Rome, Italy, and STMicroelectronics, Geneva, Switzerland. He is an ACM Member.

Martino
Giovanni Paternoster received the M.S. degree in applied physics from the University of Pisa, Pisa, Italy and the Ph.D. degree in physics from the University of Trento, Trento, Italy, in 2013. Since 2013, he has been as a Researcher with Micro Nano Facility Unit, Fondazione Bruno Kessler (FBK), Trento, Italy. Since 2022, he coordinates the Detector Technology Group within the "Custom Radiation Sensors" unit. He contributed to the development of the high-density SiPM (HD-SiPM) and LGAD technologies for fast timing with FBK. His research interests include the fabrication process and technology development of silicon radiation sensors, and in particular of silicon photomultipliers and low gain avalanche diodes.
Mher Ghulinyan received the M.S. and Ph.D. degrees from Yerevan State University, Yerevan, Armenia, in 1995 and 1999, respectively. He is currently a Senior Researcher with the Centre for Sensors and Devices with Fondazione Bruno Kessler, Trento, Italy. He has several years of experience in teaching Photonics with the University of Trento, Trento, Italy. He has authored more than 130 research papers and is an Inventor of several patents. His research interests include the field of waveguide and resonator optics, with a particular focus on the technological developments towards integrated silicon-based quantum photonics and heterogeneously integrated active silicon photonics. He is a Senior Member of the Optica (former OSA).