A Bioimpedance Spectroscopy Interface for EIM Based on IF-Sampling and Pseudo 2-Path SC Bandpass ∆Σ ADC

—This paper presents a low-noise bioimpedance (bio-Z) spectroscopy interface for electrical impedance myog-raphy (EIM) over the 1 kHz to 2 MHz frequency range. The proposed interface employs a sinusoidal signal generator based on direct-digital-synthesis (DDS) to improve the accuracy of the bio-Z reading, and a quadrature low-intermediate frequency (IF) readout to achieve a good noise-to-power efficiency and the required data throughput to detect muscle contractions. The readout is able to measure baseline and time-varying bio-Z by employing robust and power-efficient low-gain IAs and sixth-order single-bit bandpass (BP) ∆Σ ADCs. The proposed bio-Z spectroscopy interface is implemented in a 180 nm CMOS process, consumes 344.3 - 479.3 µ W, and occupies 5.4 mm 2 area. Measurement results show 0.7 m Ω / √ Hz sensitivity at 15.625 kHz, 105.8 dB SNR within 4 Hz bandwidth, and a 146.5 dB figure-of-merit. Additionally, recording of EIM in time and frequency domain during contractions of the bicep brachii muscle demonstrates the potential of the proposed bio-Z interface for wearable EIM systems.


I. INTRODUCTION
I N recent years, there has been a remarkable surge in the interest and adoption of wearable devices for healthcare.These devices, encompassing everything from smartwatches and fitness trackers to more specialized medical wearables, have opened new opportunities for personalized healthcare and real-time health data tracking.
Bioimpedance (bio-Z) spectroscopy is an attractive technique for wearable devices, since it can provide valuable electrophysiological insights from biological tissues, at a relatively low cost.These assets make this technique versatile across various clinical and point-of-care applications, including electrical impedance tomography (EIT) [1], impedance cardiography (ICG) [2], detection of cancerous tissue [3], [4], body composition analysis [5], [6], and glucose sensing [7].In addition to these applications, electrical impedance myography (EIM) [8], [9], used to evaluate neuromuscular disorders (NMDs), has also gained attention within the medical community.This technique can provide complementary information to electromyography (EMG) for reliable detection A. D. Fernandez Schrunder, Y. Huang, S. Rodriguez, and A. Rusu are with the School of Electrical Engineering and Computer Science, KTH Royal Institute of Technology, 100 44 Stockholm, Sweden (e-mail: fernande@kth.se;ykhuang@kth.se;saul@kth.se;arusu@kth.se of muscle contractions [10], [11] and has been proposed as a biomarker for NMDs, such as amyotrophic lateral sclerosis and duschenne muscle dystrophy [12], [13]. EIM measures the impedance of muscle using four surface electrodes, as shown in Fig. 1.The outer electrodes deliver a low-amplitude sinusoidal current (in compliance with international standard IEC60601-1 [14]), in the kHz to MHz frequency range, while the inner electrodes capture the voltage response (V in ) from tissues, which contains the modulated bio-Z.Assuming that the readout used for this measurement has a large enough input impedance, no current flows into the inner electrodes, so the captured V in can be simply expressed as: where Z EIM is the total impedance from underlying tissues, I pk and ω SG are the peak amplitude and angular frequency of the injected sinusoidal current, respectively.Typical bio-Z readings of EIM show baseline values ranging from 1 Ω up to 10 kΩ, which depend on the measured muscle, amount of subcutaneous and intramuscular fat, and distance between electrodes [15].Additionally, bio-Z readings fluctuate by 10 mΩ to 1 Ω due to physiological processes and muscle contractions [10], [15]- [17].Consequently, bio-Z spectroscopy systems require readouts with low noise (Z n,rms < 10 mΩ rms ) and large signal-to-noise ratio (SNR > 100 dB) to detect the baseline bio-Z signal and its fluctuations over the entire frequency range.Moreover, to diagnose neuromuscular disorders, bio-Z errors below 1% are typically required [18].Furthermore, it has been demonstrated that muscle contractions, which happen in the 0.1 Hz to 2-10 Hz bandwidth [19], [20], can be detected in two ways: i) single-frequency multi-channel EIM, by measuring relative bio-Z magnitude and phase changes of all channels [10], [21], ii) multi-frequency single-channel EIM, by measuring phase shifts in the bio-Z spectrum [11].Both approaches require relatively high data throughputs.In the first approach, the measurements from all channels should be acquired faster than the necessary Nyquist rate (∼ 4-20 Hz).
Similarly, in the second approach, the measurements at all frequencies in the bio-Z spectrum should be acquired within the same time window.
To extract Z EIM from V in , as in eq. ( 1), the measured voltage response from tissues needs to be demodulated.I/Q demodulation is the most ubiquitous technique, as it can be implemented either in analog or digital domain and it is potentially less sensitive to noise and DC offset than other demodulation techniques [1].To extract the real and imaginary parts from the demodulated bio-Z, narrowband filters are required to remove the high frequency components, and the filter settling time should be carefully considered to achieve sufficient data throughput.The approach in [22], aiming EIT applications, achieves high data throughput with the wideband architecture, shown in Fig. 2.a, which digitizes the signal at the bio-Z frequency and employs I/Q demodulation in digital domain.In [23], similar data throughput is achieved with the zerointermediate frequency (IF) architecture, shown in Fig. 2.b, by controlling the cutoff frequency of a pseudo-resistor-based passive LPF.However, these two approaches are power hungry as they require a high bandwidth instrumentation amplifier (IA) before demodulating the bio-Z signal.Additionally, the zero-IF architecture [23] is sensitive to 1/f noise and DC offset as the bio-Z signal is down-converted to DC after the IA.This brings considerable design challenges in the ADC.Furthermore, the LPF in [23] introduces significant signal distortions which affect the bio-Z accuracy.In [24]- [26], considerably better power efficiency is achieved, by implementing I/Q demodulation in the analog domain with the zero-second-IF architecture shown in Fig. 2.c.This ar-chitecture relaxes the bandwidth requirements of the IA by pre-demodulating the input signal to IF, thus saving power.Additionally, high data throughputs are achieved by employing succesive-approximation register (SAR) ADCs and increasing their sampling frequency beyond the Nyquist rate of the bio-Z signal, which relaxes the bandwidth requirements of the LPFs.However, the zero-second-IF architecture is sensitive to 1/f noise and DC offset after the IA, as zero-IF architectures.The low-IF architecture, shown in Fig. 2.d [27], demodulates the input signal to IF, and digitizes directly at IF with a continuous time (CT) bandpass (BP) ∆Σ ADC to avoid 1/f noise and DC offset.Moreover, since it employs I/Q demodulation in digital domain, it can flexibly trade-off data throughput and impedance sensitivity as required for the application.However, this architecture is sensitive to noise folding at spectral images of the local oscillator, used to demodulate the bio-Z signal.Additionally, the proposed CT BP ∆Σ ADC requires digital calibration.The ADC also consumes significant power as it requires two OTAs to achieve first order noise shaping and requires a high sampling frequency to achieve sufficient resolution.
This paper proposes a bio-Z spectroscopy interface, based on the low-IF readout shown in Fig. 2.e), which achieves lownoise, high-accuracy, low-power and sufficient data throughput to detect muscle contractions by: i) pre-demodulating the bio-Z signal to IF using quadrature (I/Q) XNOR-merged clocks, ii) amplifying, filtering, and buffering the signal with a lowgain and low-noise IA, iii) directly digitizing the amplified signal at IF with a high resolution and power-efficient BP ∆Σ ADC based on pseudo 2-path switched-capacitor (SC) resonators.The paper is organized as follows: Section II presents the proposed architecture, Section III describes the circuit implementation of the key building blocks and Section IV shows measurement results.Finally, Section V concludes the paper.

II. PROPOSED ARCHITECTURE
The architecture of the bio-Z spectroscopy interface, shown in Fig. 3, is proposed to achieve the required performance for wearable EIM applications in a power efficient way.The bio-Z accuracy is addressed by careful design of the current signal generator, and evaluating its impact on the readout.The required bio-Z sensitivity and SNR are achieved by minimizing the noise contributions of the interface, while maintaining the linearity over the maximum input range.Moreover, simultaneous measurement of the baseline and time-varying impedance from muscles are enabled by the wide dynamic range (DR) of the readout.Lastly, necessary data throughput is achieved by direct digitization at IF.
As it can be seen in Fig. 3, the interface consists of two subsystems: i) a sinusoidal signal generator (SSG), comprised by a clock divider, a DAC control and a 6-bit thermometer-encoded current-steering DAC (IDAC), and an I/Q XNOR-based clock generator, ii) a quadrature IF-sampling readout, comprised by the I and Q channels, which contain a double-balanced passive mixer, a current-balancing IA, and a pseudo 2-path BP ∆Σ modulator.The output bitstream of the BP ∆Σ modulator is

Sinusoidal Signal Generator
Sinusoidal Signal Generator

SPI Master
Fig. 3: Block diagram of the proposed bio-Z interface.
decimated and filtered with an off-chip digital signal processor (DSP) to obtain the demodulated bio-Z data.The configuration of the programmable blocks in the architecture is set via a serial-peripheral interface (SPI).The system-level details of each one of these blocks will be discussed in the following subsections.

A. Sinusoidal Signal Generator
The error requirements for EIM (< 1 %) impose challenging linearity specifications on the SSG.Ideally, the injected sinusoidal current signal would be a single tone, as this would guarantee an error which would only be limited by the noise of the readout.In practice, however, the injected sinusoidal current might have considerable harmonic content, which will fold into the bio-Z bandwidth during the demodulation process, degrading the accuracy.State-of-the-art SSGs generate sinusoidal waveforms via direct digital synthesis (DDS), as it provides a good compromise between power consumption, linearity, and flexibility [18].In DDS, a sinusoidal signal at f SG , is generated by oversampling in digital domain at f s , and converting the signal via a digital-to-analog converter (DAC), with N DAC bits [28].The choice of oversampling ratio (OSR SG =f s /f SG ) and N DAC determines the achievable signal-tonoise ratio (SNR SG = 1.76 + 6.02N DAC + 10 log (OSR SG )) and spurious-free dynamic range (SFDR SG ) of the SSG, which is given by [29]: Although increasing the OSR SG results in improved SNR SG and SFDR SG , the maximum f s is limited by the technology node.Moreover, the power consumption of the digital blocks scale linearly with f s .Since for EIM the maximum f SG is 2 MHz, OSR SG of 64 was chosen, resulting in a maximum f s = 128 MHz, which can be implemented in a 180 nm CMOS technology.By choosing N DAC = 6 and OSR SG = 64, the SSG is able to achieve an SFDR SG of 36 dBc and SNR SG of 55.94 dB, which can significantly reduce the impedance errors due to harmonics folding during demodulation, as it will be shown in detail in Section II.B.1.The effects of the SSG thermal and 1/f noise contribution to the noise budget will be discussed in Section II.B.2.
The SSG generates a 64-tap sinusoidal current signal with programmable frequency and amplitude.Its frequency (f SG ) can be selected among 12 logarithmically spaced frequencies, between 1 kHz and 2 MHz, while the current amplitude can be set between 1 µA and 150 µA.The SSG output is connected to the external resistors, R b (1 MΩ), to bias the output stage to a common-mode voltage of 0.9 V, and capacitors C HPF to avoid injecting any DC current to the patient, as it is required for safety [14].Additionally, the SSG generates the I/Q clocks for demodulation of the bio-Z signal, by merging a clock at f SG and a clock at IF, f IF , using XNOR gates.
The clock divider selects the appropriate DAC control clock, which runs at 64f SG .The phase accumulator block divides a period of the sinusoid into 64 phases, by accumulating cycles of the DAC control clock.The accumulator output is then used to map the sinusoidal waveform by means of a look-up table (LUT), which contains the corresponding DAC's binary input.In this process, the phase accumulator is effectively oversampling a sinusoidal signal at f SG with OSR DAC = 64.The binary amplitude mapping signal goes through a thermometer encoder and a butterfly shuffler for dynamic element matching (DEM), which improves the IDAC's linearity and up-converts 1/f current noise [26], [30].The 6-bit IDAC consists of 64 Fig. 4: Illustration of spectrum when mixing bio-Z input signal with XNOR-merged clocks.
complementary unit current sources that generate positive and negative rectified sinusoidal current waveforms, which are chopped at f SG to generate a differential waveform.The clock divider and DAC control were implemented by synthesizing their respective register transfer level (RTL) code, using a standard digital flow.

B. Quadrature IF-Sampling Readout
At its input, the readout is connected to an off-chip passive high-pass filter (HPF) with a cutoff frequency of 500 Hz to AC couple the incoming bio-Z signal.An IF, f IF = 15.625 kHz, was chosen as a trade-off between 1/f noise and power consumption.The AC-coupled bio-Z signal, at f SG , is up- The frequency conversion to IF is performed by double-balanced passive mixers driven by the aforementioned I/Q clocks.The signal is amplified by the low-noise currentbalancing IAs, which provide high common mode rejection ratio (CMRR), high input impedance, and good power-to-noise efficiency.Moreover, the gains of IAs can be programmed between 6 dB and 20 dB in 7 steps, to extend the input bio-Z range, without saturating the readout.These IAs also perform 1 st order anti-aliasing filtering, with cutoff frequency f c = 2f IF = 31.25 kHz, and buffering before digitization at IF with a BP ∆Σ ADC.The IAs will introduce a phase delay of approximately 28°.However, since all the input signals are converted to IF, they will experience the same phase delay regardless of f SG , which can be easily calibrated off-chip.
Since the proposed readout is implemented with a low-IF architecture, harmonic content and spectral images fold to IF when demodulated [31].The SSG will introduce harmonics which are caused by sampling and non-linearities in the IDAC.Furthermore, the SSG, the measured bio-Z, and the electrodes, also produce thermal noise at the input.The harmonic content and thermal noise at the spectral images will fold to IF and might degrade the bio-Z measurement accuracy and precision.To achieve bio-Z errors below 1%, it is necessary to guarantee that the folded harmonics are negligible as compared to the bio-Z signal.Thus, it is necessary to evaluate the impact of the I/Q XNOR-merged clock mixing in the proposed bio-Z interface.Likewise, to achieve sub-Ω bio-Z sensitivity, it is also important to evaluate the system noise budget, which is critical for designing the IA and ADC.
1) I/Q XNOR-Merged Clock Mixing: An illustration of this process is shown in Fig. 4. The clocks with frequencies f SG and f IF are merged with XNOR gates, and their fundamental frequencies and harmonics are mixed.The resulting merged clock will contain harmonics at k 1 f SG ± k 2 f IF , where k 1,2 = 1, 3, 5... are the harmonic numbers of each clock.These harmonics have decaying amplitude by a factor 1/(k 1 k 2 ) 2 .Each one of these harmonics will mix with the bio-Z input signal in the demodulation process.Consider that the SSG is able to achieve an SFDR of 36 dBc with a dominant harmonic at 63f SG .This means that the harmonic at 63f SG will be down-converted, and attenuated by a factor of 1/63 2 (-71.96dB).It can be readily noticed that the down-converted harmonic to IF will have an amplitude of 107.96 dBc, thus it will introduce an error of 0.0004 %, which will have an insignificant impact on the system accuracy.Additionally, the limited SNR SG and non-linearities in the SSG's IDAC will cause odd harmonics at frequencies below 63f SG , which will also be down-converted.Nonetheless, the amplitude of these harmonics can be estimated to be 20 dB lower (∼ 55.94 dBc) than the one at 63f SG due to the chosen SNR SG and applied DEM [28], [29].Therefore, they will introduce errors below 0.017 %, which should not significantly degrade the system accuracy either.
In addition to the folding of harmonics from the signal generator, thermal noise at spectral image frequencies, i.e., at k 1 f SG ± 2f IF , will also fold to f IF .However, given that the input signal has been already demodulated in quadrature at the input of the readout, the noise folded from the spectral images can be rejected in digital domain [31] and it will not significantly impact the bio-Z measurement accuracy, allowing sub-Ω bio-Z sensitivity.2) Noise Budget: One of the biggest design challenges in bio-Z readouts is achieving a good noise-to-power efficiency, while avoiding saturation of the readout due to a large baseline impedance [26].Previous works, focusing on 2-electrode bio-Z measurements, propose cancelling the large baseline impedance from the electrodes [24]- [26], [30].However, in EIM, the baseline bio-Z contains information regarding tissue composition, so it should be measured together with the timevarying bio-Z (requiring an SNR > 100 dB).Therefore, the noise of the readout should be minimized while considering the maximum measured impedance.The bio-Z noise of the interface in EIM measurements is given by: where v 2 n,TCA is the input-referred noise voltage of the transconductance amplifier (TCA) in the IA, i 2 n,SG is the output noise current of the signal generator, Z EIM is the bio-Z of tissues, and I pk is the peak amplitude of the injected sinusoidal current.The noise at f IF = 15.625 kHz should be reduced since the signal is sampled at IF.By increasing the size of the TCA's input pair devices, the flicker noise corner frequency is pushed significantly below f IF , thus only v 2 n,TCA,thermal contributes to v 2 n,TCA .To reduce the IDAC flicker noise at 1/(f-f SG ), we apply DEM to the unit current sources, which up-converts the noise from f SG to f SG +f DEM .However, the current reference in the IDAC still contributes to i 2 n,SG,1/(f-fSG) .Nonetheless, the current reference noise can be significantly reduced by increasing the size of a single transistor, such that mostly i 2 n,SG,thermal contributes to i 2 n,SG .Since the devices in the IDAC are biased in weak inversion, i 2 n,SG,thermal cannot be reduced further and and limits the minimum Z 2 n,BioZ .Consequently, v 2 n,TCA,thermal should be chosen to trade-off noise with linearity and power consumption of the IA.Since EIM requires SNR > 100 dB, the SNDR of the ADC was set to 110 dB.Additionally, since the minimum required time-varying bio-Z signal is Z bio-Z,min × I pk = 10mΩ × 150µA = 1.5 µV (-116.47dBV), the integrated noise was set to 316 nV rms over a 61 Hz bandwidth (-130 dBV), to ensure a ∼ 14 dBV margin from the minimum bio-Z signal.Therefore, the maximum programmable gain of the IAs was set to 20 dB to guarantee noise below the ADC lowest level, and the minimum was set to 6 dB, to ensure that the readout does not saturate due to a very large baseline impedance.
3) SC Bandpass ∆Σ ADC: For the SC BP ∆Σ ADCs, the sampling frequency, f s , is set to 4f IF , to simplify the realization of the loop filter via the pseudo 2-path transformation.Applying this transformation to the noise transfer function (NTF) of a LP ∆Σ ADC guarantees that the resulting BP ∆Σ ADC preserves the properties of its LP counterpart, including noise-shaping order, oversampling ratio (OSR ADC ), and stability [32].Therefore, f s = 4f IF = 62.5 kHz, and the OSR ADC = f s /2f BW is obtained by choosing the bandwidth of the noise stopband, 2f BW .In this design, the proposed BP ∆Σ ADC employs single-OTA pseudo 2-path SC resonators [33], to achieve the required SNDR with better power efficiency than an implementation based on generalized N-path transformation.It is noteworthy that for the considered application, BP ∆Σ ADCs based on pseudo 2-path SC resonators have several advantages over the equivalent CT implementations: i) Pseudo 2-path SC resonators are more robust than CT single-opamp resonators [34], as the Q-factor and resonant frequency are independent of component mismatch; ii) The gain-bandwidth product (GBW) requirement for the OTAs in the loop filter can be easily achieved by biasing them in weak inversion, and thus CT implementation offer no advantage in terms of power savings.

III. CIRCUIT IMPLEMENTATION A. Current-Steering DAC and Programmable Current Driver
The programmable current driver, at the output of the 6-bit IDAC, is shown in Fig. 5.The reference current, I ref , can be programmed to supply 14-140 nA to the IDAC.The reference current is mirrored to the unit cascode current sources in the IDAC, to generate sinusoids with amplitudes of 1-10 µA.These unit cascode current sources improve linearity, and their speed is enhanced by steering to supply or ground when idle.To overcome the limited voltage swing and limited output impedance of these sources, a programmable current driver, based on complementary wide-swing binary-weighted cascode current mirrors, applies the sum of unit current sources from the IDAC to tissue.The output current amplitude can be programmed from 1 µA to 150 µA by selecting the driver current gain in 16 steps, from 0 dB to 23.52 dB.

B. Current-Balancing Instrumentation Amplifier
The current-balancing IA is shown in Fig. 6.Compared to standard current-balancing IAs, in which the transimpedance amplifier (TIA) is implemented by placing a resistor at the output of the transconductance amplifier (TCA) current mirror, here the TIA is implemented with a closed-loop topology.This approach comes with two benefits: i) since both the TCA and TIA are closed-loop topologies, the IA is more robust to process-voltage-temperature (PVT) variations, ii) No V mn :20 :20 additional active circuitry is required after the IA, since the TIA stage acts as an anti-aliasing filter and buffer before the ADC.
The programmable TCA consists of a G m core and 3-bit binary-weighted programmable current mirrors.The G m core is based on a flipped-voltage-follower (FVF) topology with a common-gate (CG) stage which provides a higher loop gain than traditional FVF [35] and super source follower [36] topologies, without compromising stability.The high loop gain ensures that the input voltage, V in , is buffered to the source of the input pair, causing a current flow through R DEG .This current is copied and attenuated to the TCA output by the binaryweighted programmable current mirrors, to accurately adjust the entire G m without compromising linearity and noise of the G m core.The programmable current mirrors are implemented with cascodes to guarantee a larger output impedance than the input impedance of the TIA, and improved linearity.Assuming sufficiently large loop gain and FVF's output impedance much smaller than R DEG , the programmable transconductance of the TCA can be approximated by: where i represents the branch number in the programmable current mirror.i = 0 represents the default branch, which is not controlled by switches, and i = 1, 2, 3 represents the branches controlled by b i (b<2:0>).
The half-circuit noise model of the G m core can be seen in Fig. 7. Neglecting channel-length modulation of all transistors in the core, the total input-referred noise voltage is given by: As explained in Section II.B.2, the TCA thermal noise contribution is the only design parameter that needs to be considered in the noise budget.Therefore, the biasing current of M 1,2 , and value of R DEG should be carefully chosen to achieve the integrated noise requirement of 316 nV rms over a 61 Hz bandwidth (-130 dBV).The contribution from M 1 (v 2 n,M1 ) and M 2,3,5 (i 2 n,M2,3,5 ) can be reduced with sufficient biasing current on the input pair.The contributions from R DEG (i 2 n,RDEG ) can be minimized by reducing the resistor value.However, the lower bound of R DEG is set by the saturation condition of the G m core, given by V in,max = 2I bias,M1,2 R DEG .This means that the power consumption needs to be traded off for sufficiently low noise and voltage headroom.In this design, the maximum input voltage is given by the maximum required bio-Z and the maximum injected current, i.e., V in,max = Z bio-Z,max ×I pk,max = 1 kΩ×150 µA = 150 mV.Therefore R DEG = 15 kΩ and I bias,M1 = 8 µA were chosen to achieve a noise density of 43.62 nV/ √ Hz, thus an integrated noise of 340.68 nV rms over a 61 Hz bandwidth (-129.35dBV), and leave enough voltage headroom for V in,max .
The TIA is implemented with a two-stage OTA with feedback resistor, R TIA of 210 kΩ.A feedback capacitor, C TIA of 24 pF in parallel with R TIA , is employed in combination with Miller compensation (C MC and R MC ) to achieve stability.Additionally, C TIA adds a low frequency pole, which acts as a first-order anti-aliasing filter, with a low-pass corner f c = 1/(2πR TIA C TIA ) ≈ 31.25 kHz.The TIA output stage, driving the sampling capacitor at the input of the ADC (10 pF, as detailed in section III.C) and C TIA , should supply enough current to settle the signal within a sampling period, T s of 16 µs.An output biasing current, I bias,out of 10 µA, was chosen to achieve a slew rate of 0.3 V/µs, sufficient to drive a fullscale sinusoid within T s .Additionally, to reduce the amplitude of sampling artifacts, charge bucket filters are used at the output of the TIA.

C. Pseudo 2-Path SC Bandpass ∆Σ ADCs
The block diagram of the proposed BP ∆Σ modulator based on pseudo 2-path SC resonators is shown in Fig. 8.a, and its timing diagram is shown in Fig. 8.c.The 6 th order BP NTF and signal transfer function (STF), shown in Fig. 8.b, are obtained by applying the (z −1 → −z −2 ) transformation to a 3 rd order LP feedforward ∆Σ modulator.To achieve faster bio-Z readings, the noise stopband for the bio-Z signal was chosen as 2f BW = 122 Hz (OSR ADC = 256).This allows increasing the cutoff frequency of the off-chip decimation filters above the bio-Z bandwidth (4 Hz) while achieving the required SNDR.This choice of f BW enables a throughput of 10 samples/sec for the 12 bio-Z frequencies.Moreover, the SNDR can be traded-off for higher data throughput, by adjusting the filters cutoff frequency and decimation ratio.To reduce the in-band noise gain, the modulator coefficients were obtained via optimized zero placement of the NTF [37].The 6 th order BP feedforward ∆Σ modulator with single bit quantizer and OSR ADC = 256, is chosen since it can achieve the required SNDR of 110 dB with lower power consumption than other alternatives.To save more power without degrading the modulator performance, the feedforward summing node is implemented with passive switches.In this application, the single-bit quantizer approach does not bring stability concerns, since the ADC's input signal is a single tone at IF, and its amplitude can be easily controlled via the IA's programmable gain and the SSG's current amplitude.
To relax the gain requirements of the OTAs, gaincompensated pseudo 2-path SC resonators are employed [33], as shown in Fig. 8.a.These resonators estimate the non-zero voltage across the resonator's input caused by the finite OTA gain, and cancel this offset to create a near ideal virtual ground.More specifically, the capacitors C h acquire the voltage offset of the OTA at their right-hand terminals during the sampling phase, i.e., ϕ 1 , A 1 , B 1 , and C 1 .This voltage is subtracted during the integration phase, i.e., ϕ 2 , A 2 , B 2 , and C 2 , thus creating a virtual ground at the left-hand terminals of C h .The resonators (z −2 /(1−z −2 )) are implemented with a doubledelayed charge transfer feedback scheme.For instance, the sampled charge during ϕ 1 , is transferred to the integrating capacitor of path A during A 2 .This charge is held onto this capacitor for two sampling periods and then transferred to the integrating capacitor of path C during C 2 .This cycle is interleaved with the cycle of path B transferring charge to path A. Consequently, at the output of each resonator, there are effectively 2 double-delayed charge transfer paths.
The OTA used in the first resonator, shown in Fig. 9.a, is implemented with a folded cascode topology to achieve the required gain and voltage swing.The OTAs in the second and third resonators, shown in Fig. 9.b, are implemented with A resistoraveraged SC common-mode feedback (CMFB) was adopted due to its intrinsic linearity and to avoid power overhead.
The sampling capacitor in the first resonator, 22Cs 1 ≈ 10 pF, was chosen as a trade-off between kT/C noise, area and power consumption.Since the impact of kT/C noise of the following stages is suppressed by the loop, the sampling capacitors in the second and third resonators were reduced by a factor of 2 and 3, respectively, to save area and power.Although these capacitors could theoretically be reduced further, the gaincompensation capacitor (C h = 1 pF) sets the lower boundary, as it needs to be around x10 smaller than the sampling capacitor, and x10 larger than the parasitic capacitance of the OTAs input pair.This condition is necessary to achieve the aforementioned relaxation of the OTAs gain requirement.
The quantizer is implemented with a strong-arm latch dynamic comparator, which provides robustness and power efficiency [38].To achieve adequate timing of the feedback, the quantized output is double-delayed with a pair of D flipflops.To reduce charge injection into the resonators, delayed versions of the non-overlapping clocks (ϕ 1,d and ϕ 2,d ) are used.Switches are implemented with CMOS transmission gates to improve linearity.Additionally, dummy switches are added to reduce charge injection.The non-overlapping clocks and delayed versions are generated by cross-coupled NOR gates with delay elements, and the pseudo 2-path clocks (A 1,2 , B 1,2 , C 1,2 ) are generated with a differential Johnson counter and digital logic, as shown in Fig. 10.

IV. MEASUREMENT RESULTS
The proposed bio-Z interface was implemented in a 180 nm CMOS process.Fig. 11 shows the die micrograph with an overlayed transparent image of the layout, with block annotations.The active area, which includes the SSG, IAs, and BP ∆Σ modulators, is 5.4 mm 2 .The digital and analog domains are powered by two separate 1.8 V supplies, while the digital I/Os and ESD protections are powered by 3.3 V supplies.The digital circuits are placed in deep n-wells to isolate the substrate from noise.Similarly, the analog blocks are separated from the digital blocks with n-well trenches, to improve noise isolation.The readout consumes 339.8 µW (2×45.5 µW from TCAs, 2×36.9 µW from TIAs, and 2×87.5 µW from BP ∆Σ modulators), and the SSG consumes 4.5-139.5 µW, depending on the injected current I pk (1-150 µA).

A. Measurement Setup
The measurement setup for electrical characterization and experimental verification of EIM measurements is shown in Fig. 12.To evaluate the impedance sensitivity, SNR, and linearity of the whole bio-Z interface IC, measurements on selected commercial resistors from 10 Ω to 100 kΩ with 1% tolerance ratings, were performed.Additionally, to evaluate the performance of the BP ∆Σ ADC, measurements were performed using an ultra-low distortion signal generator (Rohde and Schwarz SMA100B).Finally, to experimentally verify the system feasability for EIM, measurements over the right arm's biceps brachii muscle were performed using gel electrodes, which were placed at an inter-electrode distance of ∼ 2.5 cm.To reduce the mains (power-line) interference, an additional electrode on the left arm (not shown in the measurement setup) was used to bias the subject's body to the common mode voltage (0.9 V).

B. Electrical Characterization
Fig. 13 shows the input-referred noise density of the readout, when I pk was adjusted for each resistor from 2.45 µA to 111 µA, to keep the input voltage amplitude within the linear range (∼ 245 mV).The spectral density for each measurement is obtained by: i) recording 1310720 samples of the output bitstream from the ∆Σ modulator in the I path, ii) slicing the recorded data in 20 subsets of 65536 samples, iii) performing a flat-top-windowed fast Fourier transform (FFT) over each data subset, iv) taking the root-mean-square (RMS) voltage density from the FFT of all data subsets.The measurement results show that for low resistors, the noise density of the interface is close to the TCA's predicted noise.Additionally, no flicker noise is observed within the bio-Z band, demonstrating the effectiveness of the noise reduction approach described in section II.B.2.As the measured resistor increases, the noise density increases due to conversion of SSG current noise into voltage noise through the resistor.Nonetheless, the noise density can be kept constant by reducing I pk , which reduces the current noise from the SSG.The SNR measured over a 4 Hz bandwidth, as presented in Fig. 14, shows that the interface fulfils the requirements and achieves a SNR max of 105.8 dB.Moreover, the SNR increases linearly, from 68.1 dB to 105.8 dB, with the measured resistor and it saturates at around 100 -105 dB for measured resistors between 2.2 kΩ and 100 kΩ.This is due to the increase of the root mean square resistance noise and limited linearity of the IA, at the maximum input voltage swing.Nonetheless, the SNR is practically constant above 2.2 kΩ, making the proposed readout suitable for measuring large resistors with sub-Ω sensitivity.Compared to the state of the art [24], [25], [30], the proposed interface achieves a higher SNR max despite employing a larger R DEG in the TCA, as it withstands a wider input voltage range, and avoids additional noise from baselineimpedance-cancelling feedback.
Fig. 15 shows the spectral density of the SC BP ∆Σ ADC for input signal amplitudes between -75.3 dBFS and -1.6 dBFS, at f IF = 15.625 kHz.It can be noticed that the noise floor of the ADC fulfills the noise budget requirements and no significant distortions are observed within the signal band.Moreover, the third order BP noise shaping is accurately centered at f IF without calibration, and out-of-band distortions are within 10 dB of the noise level.However, it should be noted that there is an increased in-band noise that limits the ADC performance, which is caused by: i) folding noise from f s /3 to f IF due to mismatches in the SC resonators [33], ii) parasitic capacitances due to routing (from the sampling capacitor to the integrating capacitors), which leak charge between paths, affecting the precision of the double-delayed charge transfer.It is worth noting that it was observed in postlayout simulations that the second cause has a substantially stronger effect on the noise contribution.
The SNDR of the BP ∆Σ ADC, presented in Fig. 16, shows a peak SNDR of 107.07 dB at -2.08 dBFS input amplitude and a DR of 107.48 dB.These measurement results demonstrate that the performance of the proposed ADC enables digitizing the amplified baseline and time-varying bio-Z signals simultaneously, without any loss of information.Moreover, the proposed ADC shows excellent linearity due to its narrowband characteristics and low in-band spurious content.
The linearity performance of the bio-Z interface is shown in  Fig. 17.The results were obtained by measuring the resistors with our bio-Z interface IC, at f SG = 500 kHz, and comparing them with reference readings from a high-precision LCR meter (Rohde and Schwarz -HM8018).The frequency, f SG , was chosen to prove that good linearity can be achieved despite the impact of parasitics at higher frequencies.The injected I pk was adjusted for each resistor to keep the input voltage within the linear range of the readout.It can be seen that the proposed bio-Z interface achieves errors below 3% as compared to the reference readings, from 10 Ω to 4.7 kΩ.The higher errors (> 1 %), under 400 Ω, might be due to larger contact resistance relative to the measured resistor.Table I summarizes the measured electrical performance of the implemented bio-Z interface IC and compares it with the state of the art.For fair benchmarking with prior art, SNR max and Figure of Merit (FoM SNR ) is reported over a 4 Hz bandwidth.The proposed bio-Z interface achieves the best SNR max and a FoM SNR comparable with the state of the art, at the cost of higher power consumption due to the wider input range.Although previous art report better FoM SNR [24], [25], [30], it is worth noting that this work achieves competitive performance while digitizing the signal with high resolution at IF, which comes with several benefits in terms of data throughput, design simplicity, and flexibility as discussed throughout this paper.Furthermore, it can also be seen that our proposed bio-Z interface achieves considerably higher SNR and FoM as compared to previous art employing a low-IF readout architecture and BP ∆Σ ADC [27].

C. Experimental Verification of EIM
EIM measurements were performed to validate the bio-Z interface IC during dynamic activity of the biceps brachii muscle, i.e., by sequentially relaxing and contracting the muscle, as shown Fig. 18.a.The bio-Z of muscle was obtained by applying a single frequency FFT, with a resolution-bandwidth of 4 Hz, to 20 data subsets of the I/Q channels output bitstream, and taking the RMS voltage density at each frequency (as described in Section IV.B).The frequency domain measurements in Fig. 18.b, show that during muscle contractions there is an overall decrease in impedance magnitude throughout the whole spectrum, with more significant decrease for frequencies below 125 kHz.Furthermore, a noticeable phase shift and increase of the phase peak also occurs in the phase spectrum  while contracting the muscle.These results are consistent with previous demonstrations of EIM during muscle contractions employing high-accuracy bio-Z spectroscopy equipment [11].
With these results, we demonstrate that our bio-Z interface IC can accurately detect changes in the bio-Z spectrum due to muscle contractions in a power-efficient way.Furthermore, the time domain measurements at f bio-Z = 31.25 kHz in Fig. 18.c, show a magnitude and phase variation of ∼ 5 Ω and ∼ 4.5 • , respectively.Moreover, it can be noticed that the noise is practically negligible as compared to these variations, which shows the potential of the bio-Z interface IC to detect smaller variations with high precision.Lastly, these results demonstrate the ability of the bio-Z interface IC to accurately detect changes in bio-Z due to muscle contractions, in real time, which enables future applications of wearable EIM.

V. CONCLUSION
A bio-Z spectroscopy interface IC for electrical impedance myography (EIM) was presented.The proposed interface achieves low-noise, high-accuracy, low-power, and sufficient data throughput for EIM, through a DDS-based SSG and a low-IF readout architecture.The SSG improves the interface accuracy and SNR by reducing the impact of harmonic content, and 1/f noise through oversampling and DEM.The low-IF readout achieves a good power-to-noise efficiency by: i) relaxing the IA bandwidth requirements while avoiding 1/f noise and DC offset, ii) employing a robust IA, which acts as a buffer and LPF for the ADC, thus avoiding additional circuitry, iii) employing a BP ∆Σ ADC based on pseudo 2-path SC resonators.The proposed architecture allows simultaneous measurement of the baseline impedance from tissues, and small variations due to physiological changes and muscle contractions with high precision.These set of features, and the performed experimental verification, demonstrate that the proposed bio-Z interface is a potential candidate for wearable EIM systems.
This article has been accepted for publication in IEEE Transactions on Biomedical Circuits and Systems.This is the author's version which has not been fully edited and content may change prior to final publication.Citation information: DOI 10.1109/TBCAS.2024.3370399Thiswork is licensed under a Creative Commons Attribution 4.0 License.For more information, see https://creativecommons.org/licenses/by/4.0/

Fig. 5 :
Fig. 5: Programmable current driver This article has been accepted for publication in IEEE Transactions on Biomedical Circuits and Systems.This is the author's version which has not been fully edited and content may change prior to final publication.Citation information: DOI 10.1109/TBCAS.2024.3370399This work is licensed under a Creative Commons Attribution 4.0 License.For more information, see https://creativecommons.org/licenses/by/4.0/CG stage

Fig. 7 :
Fig. 7: Half-circuit noise model of the G m core.

Fig. 10 :
Fig.10: Clock generation telescopic cascodes to reduce power consumption.A resistoraveraged SC common-mode feedback (CMFB) was adopted due to its intrinsic linearity and to avoid power overhead.The sampling capacitor in the first resonator, 22Cs 1 ≈ 10 pF, was chosen as a trade-off between kT/C noise, area and power consumption.Since the impact of kT/C noise of the following stages is suppressed by the loop, the sampling capacitors in the second and third resonators were reduced by a factor of 2 and 3, respectively, to save area and power.Although these capacitors could theoretically be reduced further, the gaincompensation capacitor (C h = 1 pF) sets the lower boundary, as it needs to be around x10 smaller than the sampling capacitor, and x10 larger than the parasitic capacitance of the OTAs input pair.This condition is necessary to achieve the aforementioned relaxation of the OTAs gain requirement.The quantizer is implemented with a strong-arm latch dynamic comparator, which provides robustness and power efficiency[38].To achieve adequate timing of the feedback, the quantized output is double-delayed with a pair of D flipflops.To reduce charge injection into the resonators, delayed versions of the non-overlapping clocks (ϕ 1,d and ϕ 2,d ) are used.Switches are implemented with CMOS transmission gates to improve linearity.Additionally, dummy switches are added to reduce charge injection.The non-overlapping clocks and delayed versions are generated by cross-coupled NOR gates with delay elements, and the pseudo 2-path clocks (A 1,2 , B 1,2 , C 1,2 ) are generated with a differential Johnson counter and digital logic, as shown in Fig.10.

Fig. 11 :Fig. 12 :
Fig. 11: Die photograph with transparent layout overlay of the proposed bio-Z interface IC.
This article has been accepted for publication in IEEE Transactions on Biomedical Circuits and Systems.This is the author's version which has not been fully edited and content may change prior to final publication.Citation information: DOI 10.1109/TBCAS.2024.3370399Thiswork is licensed under a Creative Commons Attribution 4.0 License.For more information, see https://creativecommons.org/licenses/by/4.0/

Fig. 18 :
Fig. 18: Measurements of contracted and relaxed biceps brachii muscle: (a) Demonstration of relaxed and contracted muscle and electrode placement, (b) Magnitude and phase spectrum (frequency domain), (c) Time domain magnitude and phase at f bio-Z = 31.25 kHz.

Off Chip Off-chip DSP clk_ADC Decimation Filter USB Comm.
This article has been accepted for publication in IEEE Transactions on Biomedical Circuits and Systems.This is the author's version which has not been fully edited and content may change prior to final publication.Citation information: DOI 10.1109/TBCAS.2024.3370399FoM SNR =SNRmax+10×log(BW/Power) where power is the sum of max. in readout and min.inCG.
This work is licensed under a Creative Commons Attribution 4.0 License.For more information, see https://creativecommons.org/licenses/by/4.0/