An Isolated Soft-Switched High-Power-Factor Rectifier Based on the Asymmetrical Half-Bridge Flyback Converter

This article presents the analysis and design of a high-power-factor rectifier that integrates a discontinuous conduction mode operated Boost input cell with an asymmetrical half-bridge flyback converter (AHBFC). The particular connection of the dc–dc stage with the boost cell makes the dc link voltage decrease at light load, thus naturally limiting the switches’ voltage stress. A suitable design procedure is described that accounts for the resonant nature of the AHBFC, and allows to calculate all converter parameters to meet the design specifications and to achieve zero-voltage turn-<sc>on</sc> for the switches in any operating condition, considering both input voltage and load variations. The theoretical analysis is validated by experimental results taken on a <inline-formula><tex-math notation="LaTeX">$\mathbf {160\,}$</tex-math></inline-formula>W rated prototype, working at the nominal switching frequency <inline-formula><tex-math notation="LaTeX">$\mathbf {f_{s}= 400\,}$</tex-math></inline-formula>kHz, with a line voltage rms value ranging from <inline-formula><tex-math notation="LaTeX">$\mathbf {85\,}$</tex-math></inline-formula> to <inline-formula><tex-math notation="LaTeX">$\mathbf {135\;{\mathrm V}}$</tex-math></inline-formula>.


I. INTRODUCTION
I SOLATED high-power-factor rectifiers are usually obtained by cascading a Boost input stage with an isolated dc-dc converter. Such combination yields a very good input power factor, while providing a fast output voltage regulation. The two converters are controlled independently, using the respective degrees of freedom. In the attempt to reduce the number of components and the cost, especially for low-medium power applications, many integrated solutions are proposed in literature that combine a Buck, Boost or a Buck-Boost input cell with an isolated dc-dc stage, sharing the switches. For example, in [1] and [2], a Boost rectifier, operating in discontinuous conduction mode (DCM), is combined with a two-switch forward converter. In [1], the input current discharging subinterval is affected by the forward transformer magnetizing current, thus worsening the power factor, while in [2] a ripple-steering concept is applied to the output inductive filter, to smooth the output current. Examples of boost+flyback combinations can be found in [3]- [6], where passive loss-less snubbers and/or auxiliary windings are used to deal with the transformer leakage inductance. However, all these solutions are hard-switching, with the exception of [4], where an auxiliary winding is employed to achieve soft commutations at the cost of a higher input current distortion. Better performing solutions are those that combine a Boost input stage with a resonant converter, that is exploited to achieve a zero-voltage-switching (ZVS) condition for all switches. This is, in our opinion, the most significant advantage with respect to the cascade configuration, where the boost switch usually operates in hard-switching, unless DCM/CCM borderline operation at variable switching frequency is chosen, and, in any case, with an output voltage higher than twice the peak of the line voltage. Among the different resonant topologies, the most widely adopted is the LLC one, combined with an input stage with a standard diode bridge rectifier, as in [7]- [10], or in a bridgeless configuration, like in [11] and [12]. Interleaved boost stages, aimed at reducing the input current high-frequency content, are proposed in [13] and [14], while continuous conduction mode (CCM) of the boost stage is also exploited in [15]. Excluding the latter, all the other solutions operate at constant duty-cycle, fixed at 50%, with a variable switching frequency. The main drawback of the LLC converter is that, when designed to work in its inductive region to achieve ZVS, its voltage gain decreases when the switching frequency increases. Thus, at light-load, when the switching frequency must be increased to reduce the power drawn from the line, the dc link voltage increases, because of the reduced LLC gain, making it very hard to keep the switch voltage stress within acceptable limits. An attempt to solve the problem is found in [16], where a combined pulse frequency/interleaved asymmetric pulsewidth modulation is used to keep the dc link voltage below 500 V with an universal input voltage range. However, it requires the use of a full-bridge LLC structure with an interleaved boost cell (three magnetic elements are needed).
Other dc-dc topologies have been proposed, like in [17] and [18], where the DCM boost rectifier (with interleaved configuration as in [17], or bridgeless, like in [18]) is combined with an asymmetrical half-bridge buck topology, where the transformer magnetizing inductance is exploited to achieve ZVS. However, the dc-dc stage has a parabolic gain curve that limits the dutycycle variation range. A similar topology is proposed in [19], where, compared to [18], the dc-dc stage employs a half-wave rectifier, instead of a full-wave one. A constant line rms voltage was considered and results are reported only at nominal power.
Both papers neglect the transformer leakage inductance. A resonant converter with a modified input impedance was presented in [20], that operates at discrete switching frequencies, with a variable duty-cycle. The aim was to reduce the dc link voltage variation, with the drawback of an asymmetrical operation of the resonant converter. Other input stage topologies were proposed as well, as in [21] and [22], where a buck-type rectifier was combined with an isolated flyback dc-dc stage. The buck-type input stage facilitates the design for universal input voltage, and the typical dead zone in the line current can be removed with a series-connected energy buffer, as in [22]. However, the transformer leakage inductance and the hard-switching condition severely limit the applicability of these configurations. A buck-boost input stage was exploited in [23]- [25], combined with a flyback, LLC and CLCL dc-dc topologies, respectively. Only the last two papers, that employ resonant dc-dc converters, are able to achieve soft-switching, but at the expense of a more complicated structure ( [25] needs four magnetic elements).
The asymmetrical half-bridge flyback converter (AHBFC) has been proposed in [26], combined with coupled input inductors and two filter capacitors connected to the switching node. An improved version of the abovementioned topology appeared in [27], including an additional input inductance, besides the coupled input inductors, and synchronous rectification at the output of the dc-dc stage. Both solutions achieve a continuous input current, but with a parabolic input power function that limits the maximum duty-cycle to 50%, impeding the full exploitation of the dc-dc stage. Moreover, the resonant nature of the dc-dc stage is neglected. Another application of the AHBFC, integrated with a DCM-operated Buck-type rectifier, was proposed in [28] and [29] for high power factor ac-dc applications. While the solution in [28] presents the typical dead zone in the line current of buck-type rectifiers, the circuit proposed in [29] achieves a better power factor by introducing a series-connected energy buffer, as was done in [22]. However, both schemes present high conduction losses of the input stage, being the input current forced to flow through the series combination of a diode and a switch, besides the two input bridge diodes. Obviously, this adversely affects the overall conversion efficiency that, despite the achieved soft switching, remains below 85% in the whole input voltage and load range.
This article proposes a high-power-factor rectifier built combining a DCM-operated Boost input stage with an AHBFC. Its main outcomes include: 1) a detailed converter design procedure that, taking advantage of the resonant nature of the AHBFC, guarantees the ZVS for both switches in the whole input voltage and load range; 2) a simple feed-forward control of the switching frequency, based on the line rms voltage, to reduce the needed duty-cycle variation; 3) the experimental proof of a high power factor obtained keeping a constant switching frequency and duty-cycle in the line half period, with a limited and well controlled maximum dc link voltage, over the whole load range.
The article is organized as follows. Section II describes the converter operation, while the design procedure is outlined in Section III. Experimental results, from a 160 W prototype, are discussed in Section V and shown to confirm the theoretical analysis, reaching the expected performance. Section VI concludes this article.

II. DESCRIPTION OF CONVERTER OPERATION
The proposed isolated PFC is shown in Fig. 1. The input voltage is v g (θ) = V g pk sin(θ) = √ 2V g sin(θ), with θ = ω g t. The particular connection of the AHBFC cell makes its duty-cycle d c , which refers to the turn-ON interval of the upper switch S H , equal to the complement of the boost cell duty- The reason of such connection will become clear during the explanation of the converter behavior. As well known, in order to obtain a reasonable power factor at a constant duty-cycle and switching frequency, the boost cell must be designed to operate in DCM. The main converter waveforms in a switching period, taken around the peak of the line voltage, are reported in Fig. 2 for two different AHBFC operating regions. As a result of the chosen design criteria, that aim to fully exploit the resonant nature of the dc-dc stage, DCM operation happens at the minimum line rms voltage, while CCM characterizes the operation at the maximum line rms voltage, both at nominal power (here, CCM means that the rectifier diode D r conducts at least for the entire (1 − d c )T s subinterval). As we will see in the converter analysis, CCM operation is likely to occur at light-load too. This converter, in a switching period, cycles through the subtopologies illustrated in Fig. 3. The sequence depends on the operating mode of the AHBFC stage: for the DCM example of Fig. 2(a) the cycled subtopologies are b-c-d-e-d; for the CCM example of Fig. 2(b) the cycled subtopologies are a-b-c-e.

A. DCM Boost Analysis
Considering a generic switching period inside the line halfcycle and assuming a constant dc link voltage v b (t) ≈ V b , the inductor current has a triangular waveshape (see Fig. 2 With respect to the boost cell only, three subintervals can be identified. It is important to observe that the subinterval (1 − d b − d b )T s is caused by the turn-OFF of the input bridge diodes, since the boost cell operates with a synchronous rectification (thanks to the upper switch S H ). This fact has important practical consequences, besides forcing the use of fast input diodes (please, refer to Section V for further discussion of this point). Indicating with m B = V b /V g pk the boost voltage gain, it is easy to recognize that, for a correct DCM operation of the boost cell, the following condition must be satisfied at any time: Now, considering the inductor flux balance for which |v , the average inductor current in a switching period is given by: Only if m B → ∞ the average inductor current becomes proportional to the input voltage, thus achieving, in principle, a unity power factor. In all the other cases, low-frequency distortion appears, and the power factor is lower than one. The average input power is given by Analyzing (3), we see that, when the output power reduces, the duty-cycle must be reduced and/or the switching frequency must be increased in order to maintain the input/output power balance. An alternative would be to increase the boost inductance L b , by using a variable inductor arrangement, but at the cost of a much more complex inductor construction. When the boost cell is integrated with a dc-dc stage, no matter which topology is used, it shares the same control variables, i.e., duty-cycle and switching frequency. However, these control variables are now used to regulate the output voltage of the dc-dc stage, leaving the dc link voltage V b uncontrolled, i.e., a function of the converter operating point. If is the voltage gain of the dc-dc stage, that can be, in general, a function of dutycycle, load, and switching frequency, the combined Boost+dcdc stage must obey the following system of equations: where η is the estimated overall conversion efficiency, and the relation d c = 1 − d b was used. For a given set of parameters P o , V g , and f s , (5) allows to find the corresponding boost duty-cycle d b , as well as the dc link voltage V b . Differently from the LLC converter, the voltage gain of the AHBFC increases with its control variable, i.e., with duty-cycle d c . 1 At light-load, the boost duty-cycle d b must decrease, to account for the reduced transferred power: the consequent increase of the AHBFC duty-cycle . This is the reason why the AHBFC cell was connected in parallel to the bottom switch in Fig. 1 and not to the upper switch. The opposite choice would indeed lead to an unacceptable increase of the dc link voltage at light-load. At the same time, the decrease of d b at light-load makes it easier to satisfy constraint (1).

B. AHBFC Analysis
As stated in the previous section, the solution of (5) requires the knowledge of the voltage gain expression of the dc-dc stage. The analysis of the AHBFC, taking into account its resonant behavior, was recently proposed in [30]. Here, only the main outcomes of such analysis are reported. Considering a steady-state condition, the inductors' volt-second balance and the capacitors'charge balance yield the following relations: The third equation is a unique property of the proposed topology, consequence of the half-wave rectification, which makes the switched current values load-dependent, thus affecting the switches' ZVS condition. Two different resonant tanks are involved, depending on the rectifier diode D r state, whose parameters are as follows: The inductance ratio λ = L r /L m will also be used in the following. If the voltage across capacitor C r has a negligible ripple, piece-wise linear current waveforms are obtained, and the converter is likely to operate in CCM. In this case, the AHBFC behaves essentially like an isolated Buck converter, showing a voltage gain proportional to the duty-cycle. In fact, neglecting the small subinterval d f T s in Fig. 2(b), the volt-second balance of the magnetizing inductance yields (8) However, as demonstrated in [30], when the resonant voltage v C (t) has a non-negligible ripple, as for the case of Fig. 2, the above relation fails to correctly predict the converter behavior. A more precise equation, valid for CCM operation [i.e., for the waveforms of Fig. 2 with coefficients k 1 and k 2 given by In these expressions, Only two approximations have been used in the derivation of (9): subinterval d f T s in Fig. 2(b) is neglected, and the magnetizing current waveform is assumed to be perfectly triangular.
The comparison of (9) with simulation and experimental measurements shows a good match. With respect to the ideal voltage gain m ideal DC , the resonant operation increases the gain and shows a nonmonotonic behavior that limits the maximum duty-cycle the converter can work with. 2 This limit increases when the load resistance is reduced.
Far from this maximum duty-cycle value, the voltage gain turns out to be practically independent of the load. However, it shows some dependency on the switching frequency and, in particular, it decreases when the switching frequency increases. We will exploit this property to reduce the duty-cycle variation needed to cope with the input voltage variation in the specified range (see Table I).

III. PROPOSED DESIGN PROCEDURE
In this section, we describe the converter design procedure, that is carried on referring to the specifications listed in Table I and derived from a line-fed, solid-state lamp driver test-case.The design objectives are as follows: 1) Guaranteeing DCM operation of the boost cell in any condition (⇒ the minimum dc link voltage is bounded).  Table I, the other two affect all the design outcomes, as it will become clear shortly. Selecting the nominal Boost duty-cycle at d b = 0.5, the minimum dc link voltage for DCM operation of the boost cell, from (1)), is 311 V. We select V b = 370 V, to keep enough margin also in different operating points.
2) Calculation of the Boost Inductance: The boost inductor is calculated based on the desired output power, i.e., from the power balance ηP g = P o , where η is the estimated conversion efficiency. Using the nominal operating point in (3), assuming η = 0.94, the required inductance is L b = 35 μH.

3) Calculation of the DC Link Capacitance:
The value of the dc link capacitor C b can be estimated based on the desired residual low-frequency ripple. To this purpose, the integrated Boost+AHBFC can be considered equivalent to the cascade connection of a Boost stage and a dc-dc stage, for which the dc link capacitance is in charge of filtering the twice-the-line frequency power fluctuation caused by an almost sinusoidal input current absorption. The average current absorbed by the dc-dc stage can be approximated as I DC in ≈ P o /V b = 0.43 A, at the nominal operating point, with V b = 370 V. Consequently, imposing a desired peak-to-peak voltage ripple of ΔV b = 60 V, the needed capacitance value turns out to be C b = I DC in ω g ΔV b = 23 μF. The selected value was C b = 2 × 10 μF, so as to have the possibility   Fig. 2(b). The solution is found numerically, building a system of seven equations made-up by four relations exploiting the continuity property of state variables i r (t) and v C (t), plus the three constraints (6). However, there are eight unknowns, i.e., the four state variable values V C1 , V C2 , I r1 , I r2 , and the four converter parameters L r , L m , C r , n 21 . Thus, we can use one of the two current values, that affect the ZVS turn-ON of the switches, to set an additional constraint. Please note that, while the ZVS turn-ON of the upper switch S H is facilitated by the Boost inductor peak current I L pk , which sums with I r0 = I r1 , the ZVS turn-ON of the bottom switch S L depends entirely on I r2 [see Fig. 2(b)], since, at the end of the upper switch conduction interval, the boost current i L (t) is always zero, if the boost cell is correctly operating in DCM. For this reason, the current value I r2 can be imposed as a constraint. However, the nominal operating point is not the worst case scenario for S L ZVS condition, which happens at light load. In fact, assuming an almost triangular current waveform, the peak magnetizing current is estimated as At light load, both I o and d b are at minimum [d b decreases to reduce the power drawn from the line, see (3)]. This is to explain why the selected I r2 value at the nominal operating point must be much higher than the minimum value that guarantees the ZVS condition for the bottom switch. The initial guessed values for the seven unknowns were calculated according to the procedure described in [30]. The solver returned the following values: L r = 6.17 μH, L m = 55 μH, C r = 16.1 μF, n 21 = 0.806. The values used in the experimental prototype, are listed in Table II, and are pretty close to the calculated ones.The simulation of the AHBFC, at the nominal operating point, shows a condition quite close to the DCM/CCM boundary, with d f = d 3 = 0, but with a small d 1 T s ≈ 160ns, which is less than 7% of the switching period.

5) Check for the Boost DCM Condition at the Maximum
Line rms Voltage: The calculation of the Boost duty-cycle and the dc link voltage at V g max requires to find a solution for the system (5). Since d b becomes lower than 50%, i.e., the value corresponding to the nominal input voltage, d c = 1 − d b will increase, thus making the AHBFC enter the CCM region. In order to limit the maximum d c value in this condition, and avoid working too close to the maximum of the AHBFC voltage gain curve, we decided to increase the switching frequency to f smax = 500 kHz. Using (9) into (5), and solving numerically the system, we found d b = 0.413, and V b = 350 V, higher than the minimum value required for DCM operation of the Boost cell (V blim = 325 V).

6) Check for the Boost DCM Condition at the Minimum
Line rms Voltage: At the minimum line rms voltage, the Boost duty-cycle increases above 50%, causing the AHBFC to operate in DCM, where (9) is no longer valid. To solve this problem, the voltage gain in the DCM region was investigated following the same approach used in [30]. Essentially, a brute-force approach was used, consisting in numerically solving, in a MATLAB TM script, a nonlinear system of 11 equations with unknowns , for a given dc link voltage V b and load resistance. The value of V C2 is not listed in the unknowns as it is a function of the output voltage only, being equal to the voltage at which D r becomes forward polarized. The equations come from the continuity property of state variables v C (t) and i r (t) [four equations each, for the four subintervals in Fig. 2(a)], plus the three steady-state equations in (6). The convergence was assured by starting with guessed values obtained in the design phase considering the boundary DCM/CCM operating point, and then reducing the duty-cycle in small steps assigning, as guessed values for a new iteration, the values obtained from the previous one. Once again, to limit the duty-cycle variation, the switching frequency was reduced to f smin = 300 kHz. Then, a quadratic equation was used to fit the curve obtained with the procedure outlined above, with the following coefficients m (

7) Check for the ZVS Condition at the Minimum Power
and Maximum Line rms Voltage: At a reduced output power, the boost duty-cycle must decrease to maintain the input/output power balance, and the reduction is deeper at the maximum line rms voltage. Once again, we decided to increase the switching frequency to f smax = 500 kHz in order to mitigate the dutycycle variation. Solving (5) for the minimum power, we obtained  It is important to observe that, with the proposed topology, it is not possible to handle a universal input voltage range, because that would require a too wide variation of both the control parameters, namely duty-cycle and switching frequency, with consequent difficulties in guaranteeing the ZVS condition for all the operating points.
Finally, we would like to clarify that the choice of varying the switching frequency to accommodate more easily input voltage and load variations was done to exploit all possible degrees of freedom of this topology, but is not strictly necessary. One could first try to design the converter keeping the switching frequency constant, if the required duty-cycle variation is acceptable.

IV. CONTROL IMPLEMENTATION
The rectifier circuit is digitally controlled by a low-cost microcontroller (STM32F334R8), following the scheme illustrated by Fig. 4. As can be seen, two control parameters are simultaneously used to steer the converter operating point: the duty-cycle d and the switching period T s . The former is regulated by a standard proportional-integral (PI) controller, designed to achieve the target control bandwidth, 100Hz, so as to minimize the input current distortion, with an adequate phase margin > 60 • . The sampling period of the output voltage is set to T s Vo = T s /20. The switching period, instead, is slowly adjusted to the measured value of the rectified input voltage (iteration frequency is in the 15 − 250Hz range, i.e. T s V i = T s Vo /1000), in a feed-forward manner. This requires a piece-wise linear map to be implemented in the microcontroller firmware, whose parameters are then iteratively tuned to compensate the undesired effect of input voltage variations on voltage V b . As will be shown in Section V, this organization allows to effectively minimize the variation of voltage V b in the considered input voltage range.

V. EXPERIMENTAL RESULTS
The schematic of the implemented prototype is illustrated in Fig. 1, where Z g models the line impedance. It employs four bridge diodes STTH803 and two MOSFETs STB26N60M2, all from STMicroelectronics TM , while the rectifier SiC diode is the model IDD03SG60 C from Infineon TM . A silicon device could be used as well but, in any case, the voltage rating needs to be higher than the theoretical diode voltage stress because of the ringing that occurs at its turn OFF when the converter operates in CCM. In fact, the high di/dt the rectifier diode experiences, during subinterval d f T s in Fig. 2(b), is likely to excite high frequency oscillations between the device's parasitic capacitance and the transformer secondary leakage inductance, with a consequent increase of the diode voltage stress (see Fig. 9 in [30]). The transformer has been realized with a PQ 26/25 magnetic core (material N49), with primary and secondary windings made by 23 and 18 turns, respectively, both using a Litz wire (bundle of 200 strands, having each a diameter of 50 μm). The values obtained for the magnetizing inductance and the total primary side leakage inductance are reported in Table II, measured at 400 kHz with the Agilent 4294 A precision impedance analyzer. Please note that no additional external inductor has been used, the only resonant element being the transformer leakage inductance. The input inductor was built on an RM10 core (material N49), using 20 turns of the same Litz wire. The obtained value was L b = 38.8 μH, slightly higher than the calculated one. A simple EMI filter was used, that includes a common mode choke (2 × 3.3mH), having a leakage inductance of roughly 33 μH, and two capacitors (C 1 = 100 nF, C 2 = 0.92 μF). The dc link capacitor was selected as C b = 2 × 10 μF, film type. The output filter capacitor is C o = 680 μF. This value was selected to attenuate the unavoidable line frequency ripple in the output voltage for testing the converter with an equivalent resistive load. However, if the final application is for solid-state street lamps, electrolytic capacitors should be avoided. This can be obtained by allowing a higher line-frequency ripple that will be attenuated by the LED current controller stage, like in [12], where a Twin-Bus Buck output stage was employed. The photo of the implemented prototype is visible in Fig. 5: the main passive/active components are highlighted. The converter was initially tested to verify the proposed deign procedure: Fig. 6(a) shows the implemented feedforward variation of the switching frequency and the corresponding range of the boost duty-cycle, as a function of the input rms voltage and for minimum and nominal output power values. The corresponding variation of the dc link voltage is visible in Fig. 6(b): the maximum voltage results bounded below 400V, and reduces at light load, as expected. Moreover, the measured value is well above the minimum value given by (1) (see dashed lines), so that DCM operation of the boost cell is always guaranteed.  Fig. 7(a), deserves a deeper discussion, and it is related to the clamping diode D cl , visible in Fig. 1 with dashed connections. As mentioned in Section II, the discontinuous boost current is caused by the turn-OFF of the two bridge diodes that are conducting in the considered line half cycle. When they turn OFF, after interval d b T s in Fig. 2, the bridge diodes' parasitic capacitance resonates with the boost inductor, causing voltage v i (t) to oscillate around the dc link voltage. Since this resonant tank has virtually no damping, the peak voltage reaches almost twice the dc link value, increasing the diode voltage stress and causing EMI problems (the measured resonance frequency was 3.3 MHz). Diode D cl solves the problem by clamping the voltage v i (t) to the dc link voltage V b , with two consequences: ; the second effect causes the mentioned crossover distortion in the input current. In fact, when the bottom switch S L turns ON, the inductor current starts to rise, initially, with a higher slope because the clamping diode is still on. When i L (t) becomes positive, after the small interval Δt 1 in Fig. 7(b), D cl turns OFF, and the resonance between L b and the bridge diodes' parasitic capacitance discharges the latter. Only when voltage v i (t) drops below |v g (t)|, after another small interval Δt 2 , two bridge diodes turn ON and the current slope becomes |v g (t)|/L b , as it should be. This initial transient is independent of the line voltage instantaneous value, meaning that the inductor current is nonzero even during the line voltage zero crossing, which causes the distortion visible in Fig. 7(a).
It is interesting to analyze the effect of this crossover distortion on the input current harmonic content. In Fig. 8, we can see the comparison between the measured and the theoretical line current, in terms of waveform and harmonic content. The waveforms reveal a slight shift of the measured current peak due to the nonnegligible ripple of the dc link voltage v b (t) [see Fig. 7(a)], while the harmonic content shows that the crossover distortion is almost entirely canceling the third harmonic component,  while increasing the higher order harmonics, compared with the theoretical expectations. In any case, the harmonic content is well below the IEC 61 000-3-2 limits, relative to Class C (lighting equipment).
The light-load condition at the maximum line rms voltage was tested as well, and Fig. 9 shows the main converter waveforms taken in two switching periods (f s = 500 kHz): the dc link voltage is around 300 V, with d b = 0.24, once again values well predicted in the design phase. Quasi ZVS is achieved for the bottom switch, because the switched current, which is around 1 A, is able to discharge almost completely the switching node capacitance (down to ≈ 20 V). This behavior reflects the strong nonlinearity of the MOSFETs' output capacitance of the chosen devices, that increases more than two orders of magnitude when their V DS voltage approaches zero. As expected, at light-load, the AHBFC operates deeply in CCM.
The comparison of the proposed rectifier with state-of-the-art Boost+LLC solutions (refs. [11] and [12]) and with the recent rectifier application [29] of the AHBFC is shown in Table III.  TABLE III  COMPARISON WITH STATE-OF-THE-ART INTEGRATED AC-DC TOPOLOGIES WITH  Based on these data, we can make the following considerations: 1) for fixed load applications, the Boost+LLC converter operating at constant 50% duty-cycle and variable switching frequency is probably the best solution, mainly because of the possibility to employ a bridgeless configuration, with a significant reduction of the input stage losses; 2) universal input voltage range can best be handled by a buck-type input rectifier, as in [29], with a penalty in the overall efficiency mainly caused by the need for the input energy buffer to get rid of the input current dead zone. However, as far as the Boost+LLC rectifiers are concerned, even at nominal load, in order to cope with the considered input voltage variation, the switching frequency needs to change by a factor higher than 2, with a significant variation of the dc link voltage. In both refs. [11] and [12] no information is given in terms of switching frequency and dc link voltage variation when the output power is reduced (ref. [12] reports only the efficiency curve as a function of the output power for V g = 120 V rms ). It is important to consider that the ZVS condition must be ensured at the maximum switching frequency (where, unluckily, the maximum dc link voltage occurs).
The measured power stage efficiency of the proposed topology is reported in Fig. 10: as we can see, it reflects the higher conduction losses of the input bridge rectifier, compared with bridgeless solutions, and the chosen switching frequency, much higher than in similar prototypes presented in literature. Please note that, despite the measured efficiency is lower than the guessed value used in the converter design (see point 2 in Section III), the prototype proved to be able to achieve the desired nominal output power, with no need for further design iterations.
On the other hand, we believe that the major advantage of these integrated rectifiers, compared with a cascade configuration, relies exactly on the possibility to reduce the overall magnetic volume (EMI filter included) by increasing the switching frequency, while maintaining the ZVS condition, i.e., a reasonable efficiency. From this standpoint, let us compare the number and the total volume of the magnetic components (EMI filter not considered) reported in the last column of Table III: [11] does not give information about the magnetic core used, but it employs three magnetic elements, just like in [12], where the inductors of the twin-bus buck LED current controllers were not considered, for a fair comparison. Huang et al. [29] employed only two magnetic elements, like our proposal, but the magnetic volume is almost twice, due to the much lower switching frequency.
As a last comment, Table III shows that load variations are better managed by the proposed topology, for which the dc link voltage decreases at light load.

VI. CONCLUSION
In this article, a high-power-factor rectifier combining a DCM operated Boost input cell with an AHBFC was proposed and analyzed in detail. The main contributions are: 1) a detailed design procedure that, by exploiting the resonant nature of the AHBFC stage, allows to calculate all converter parameters, while ensuring zero-voltage-switching turn-ON for the switches, in the specified input voltage and load ranges; 2) a combined feedforward-feedback digital control strategy that exploit both duty-cycle and switching frequency control parameters; and 3) the investigation of a particular type of input current crossover distortion caused by the DCM operation of the boost input cell. The theoretical analysis is validated by experimental results taken on a 160 W rated prototype, working at the nominal switching frequency of f s = 400 kHz.