Multithreaded State Controller for Grid-Connected Converter With Imposed Limits

This article proposes an innovative approach to control a grid-connected converter. The method combines the versatility and high-quality control offered by the state-feedback controllers for linear plants with the ease of imposing limits on the controlled variables offered by the cascaded control systems. The method is groundbreaking in its ability to bridge the gap between the elegance of the full-state-feedback control structure and its lack of popularity among power electronics engineers and possibly also other groups of practitioners. A multithreaded state controller is proposed in the form of three state controllers: one to control grid currents and dc-link voltage if limits of the currents are not reached, and two state controllers that are put into the closed loop if one of the current limits is reached. A complete design procedure is proposed, including the selection of all gains present in the three state-feedback controllers using the pole placement method. An algorithm of soft switching between the three control signals is also developed. Sharing the desired dynamics between the threads is fulfilled thanks to the eigenstructure assignment introduced to overcome the problem of multiple solutions by choosing the most orthogonal eigenvectors. The proposed control system is then verified in a simulation, and its high practicality is demonstrated experimentally.


Multithreaded State Controller for Grid-Connected Converter
With Imposed Limits Marek Michalczuk , Member, IEEE, Bartłomiej Ufnalski , Senior Member, IEEE, and Andrzej Gałecki , Member, IEEE Abstract-This article proposes an innovative approach to control a grid-connected converter.The method combines the versatility and high-quality control offered by the state-feedback controllers for linear plants with the ease of imposing limits on the controlled variables offered by the cascaded control systems.The method is groundbreaking in its ability to bridge the gap between the elegance of the full-state-feedback control structure and its lack of popularity among power electronics engineers and possibly also other groups of practitioners.A multithreaded state controller is proposed in the form of three state controllers: one to control grid currents and dc-link voltage if limits of the currents are not reached, and two state controllers that are put into the closed loop if one of the current limits is reached.A complete design procedure is proposed, including the selection of all gains present in the three statefeedback controllers using the pole placement method.An algorithm of soft switching between the three control signals is also developed.Sharing the desired dynamics between the threads is fulfilled thanks to the eigenstructure assignment introduced to overcome the problem of multiple solutions by choosing the most orthogonal eigenvectors.The proposed control system is then verified in a simulation, and its high practicality is demonstrated experimentally.
Index Terms-Current constraints, full state feedback (FSF), grid converter, multithreaded state controller (MTSC), state feedback control.
The main advantage of such a solution is a possibility of limiting the set value of the grid current components.Since the value of i ref q is known at all times, imposing the current limitation comes down to imposing restrictions on the i ref d signal.Fig. 1(c) illustrates the concept with a state-feedback current controller (SFCC) and a voltage controller in the outer control loop [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14].This concept assumes a simplified description of the object excluding v dc as the state variable, at the stage of designing the SFCC.Similarly to the circuit presented in Fig. 1(b), this solution allows imposing of constraints through a limitation on the output signal of the voltage controller.On the other hand, Fig. 1(d) presents the control system with the state feedback, where the reference signals correspond to dc voltage v dc and current component i q [25], [26], [27], [28].This control structure has good control properties, but it does not allow the direct imposition of the current limitations through d-axis current set point due to the lack of such a signal in the control structure.The proposed name, a state-feedback voltage controller (SFVC), is conventional and refers to the primary purpose of control, which is to maintain the desired dc voltage at the converter output.In fact, the system with an SFVC has a second reference signal, which determines the desired current component in the q-axis.
The innovative multithreaded state controller (MTSC), whose concept was first presented in [29], allows taking advantage of an FSF with a current limiting method that is simple to implement.The idea is to use different structures of the state controller, depending on the control mode.The concept of two parallel operating SFCs was previously used only for a doubly fed induction generator to synchronize the system in the transition between stand-alone and grid operation [30].That solution was used to change the control structure depending on the plant configuration.The MTSC extends this idea by the cooperation of parallel control threads to ensure the right timing of transition between particular control modes.
The research presented in [29] elaborates on methods for imposing limits on state variables.Plant augmentation according to the internal model principle to get zero steady-state error for constant references and disturbances is discussed there.A complete design procedure, including analytical gain tuning and deriving the back-calculation formula to enable soft switching between the threads of the controller, is presented as well.The research also includes a numerical comparison between the cascade control system and the state-feedback control system as well as results for a hardware-in-the-loop simulation of the converter-fed dc machine.
This article presents an innovative implementation of the MTSC for a grid converter and presents the full experiment results for any MTSC application.Section II introduces a multithreaded SFC for a grid-connected converter.A distinguishing feature of the presented structure, compared to the most popular approaches using SFC [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], is the control of dc-link voltage and grid currents with the use of a parallel structure.The controller design procedure is described in Section III.The design includes controller tuning with the use of the eigenstructure assignment theorem-this is to address the nonuniqueness of the eigenvalue assignment using state-feedback control for linear time-invariant multi-input multi-output systems.The simulation and experimental results in a physical 10-kVA grid-connected converter are presented in Sections IV and V, respectively.Finally, Section VI concludes this article.

II. MULTITHREADED STATE CONTROLLER
The idea of the MTSC for the grid converter is presented in Fig. 2. It uses three control threads with state feedback.The main control thread is the state-feedback control loop for dc voltage v dc control (SFVC).The other two control threads are the grid current control loops (SFCC).Reference signals i max At each step of the algorithm, all the control threads are calculated.When the control signals have been determined in each of the three threads, the signal selector chooses a signal passed as an input to the plant.The SFVC is considered as the main thread because it fulfills the primary purpose of the control, which is the control of v dc , and if the system does not enter the operation region where the current or control signal should be limited, the control signal applied to the object is equal to u v , the output of SFVC.The operation scheme of signal selection consists in comparing the lengths of vectors u v , u min c , and u max c and choosing the middle value.Considering the negative plant gain-which will be described in the next section-between the inputs and outputs of i d and i q , in the case Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.] as a control signal allows the implementation of current limitations in the grid converter system.Owing to the limited range of grid converter output voltages at a given dc voltage, the value of the control signal is limited to the linear operating range of the modulator [31].The SFCs whose outputs are not selected at a given time as the plant control signal operate in an open loop.It means that the loop is broken in the selection or the saturation block.No more than one SFC selected by means of the median filter operates in a closed loop.
The structure of SFCs [32] is presented in Fig. 3. To ensure zero steady-state error at constant disturbance condition, integral terms of control errors are incorporated to the control structure.This, in turn, requires an antiwindup mechanism for integral terms to provide expected control performance.The antiwindup aims to adjust the state of integrators in an open-loop operation of a given SFC.The problem of adjusting augmented states in statefeedback control structures at the transition between two control modes is also addressed in [30].However, the concept, presented there, of using an additional controller to match control signals of different controller types cannot be applied to the MTSC.This is because such a mechanism does not allow the selection of control modes based on control signal as the control signal selection block (CSSB) does.In [29], it has been demonstrated that the back-calculation loop with a gain K b = N −1 keeps the integrator state at the desired level and provides the desired response of the system when a transition between open-and closed-loop operations of the given controller takes place.

III. CONTROLLER DESIGN
The design of an MTSC comes down to designing the statefeedback gains K c and K v and feedforward gains N c and N v for current and voltage SFCs.This section provides all the steps of the design and selection of control structure parameters.The presented numerical results are provided for the grid converter system characterized by parameters listed in Table I.For the purpose of designing SFCs, the linearized plant model at the nominal operation point is considered.In the continuous time domain, the grid converter system is described by the following state-space equations: where A is the state matrix, B is the control matrix, E is the disturbance matrix, x is the state vector, u is the control vector, and z is the disturbance vector.

A. Current SFC
To design the SFCC, a discretized and simplified model of the plant, including only two state variables i d and i q , is taken into consideration.It is described in the discrete time domain as follows: x where The discretization is done based on the zero-order hold (ZOH) method (i.e., match to the step response) according to the following relations: In order to provide zero steady-state tracking errors e d = i d − i ref d and e q = i q − i ref q for constant reference and disturbance signals, the control structure includes integrators (see Fig. 3), which results in plant augmentation by two states p d Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.and p q [3], [4], [27].Additional two state variables representing the output voltage of the converters u cnv d and u cnv q are included in the state vector when the unit delay resulting from the digital controller operation is considered in the plan description [6], [10].Thus, the subsequent plant model used for the design is as follows: where . The feedback gain K c is calculated using the pole placement method.There are six desired closed-loop pole locations on the z plane to be defined.Two of the open-loop poles that are introduced by state variables u cnv d and u cnv q are already in the preferred position.They are in the origin and represent the unit delay.The next two pairs of closed-loop poles are dominant and determine the response of the control system.Initially, the location of the poles is set in the s plane.The closed-loop bandwidth is chosen at ω cur = 2πf cur (f cur = 700 Hz) and the damping ratio 2 , which is a typical tradeoff between the speed of the response and the accompanying overshoot for current control systems Afterward, z plane poles are calculated by using the definition of z as follows: Assuming the same dynamic for i d and i q , the desired closedloop poles (see Fig. 4) are as follows: p CL cur = 0 0 p z1 p z2 p z1 p z2 .
The reference input matrix N c is defined as follows: which results in placing the zeros introduced by the reference feedforward in the z plane origin.This compensates the poles placed there.The response of the current controller is presented in Fig. 5.In accordance with the selected damping ratio for a step reference signal, the system responds with an overshoot of approximately 4%.The results also demonstrate good disturbance rejection properties of the controller, which is noticeable at time 10 and 25 ms when a grid voltage step change of 25 V occurs.

B. Voltage SFC
To design the discrete voltage SFC, a discrete form of the plant [see (2)] is used where F 2 , G 2 , and E 2 come from ZOH equivalent discretization Similarly to the steps performed for the current controller in Section III-A, the plant is augmented by states u cnv d and u cnv q and integral of control error p v and p q , respectively, for the control of v dc i q .The plant in this design stage is formulated as follows: where and . This SFC requires seven closed-loop pole locations to be defined.It should be pointed out here that the final goal is to use the voltage state controller as a part of the MTSC; thus, the freedom of selection of pole location is limited.In other words, the dynamics of SFVC must be associated with the dynamics of the SFCC.Two poles are placed in the z plane origin for the previously mentioned reason.The same dynamics of i q control for both the voltage and current SFCs is expected to be achieved, and this is why two poles, p z1 and p z2 , of the closed-loop system are placed in the same location as the current controller poles (see Fig. 6).The last three pole locations are selected to achieve a desired control performance of i d and v dc states.One less dominant pole is placed on the real axis at the  point corresponding to the ω cur frequency.This set of conditions should be met to ensure that the control signal selection block adequately switches between the operation modes.Moving this pole to the right side reduces dynamics and causes belated transition to the current control mode when a current saturation is needed.On the other hand, moving toward the origin might cause unnecessary transients to the current control mode and reduce the robustness of the system.The last two dominant poles p z4 and p z5 are selected as z plane equivalent to s plane poles p s3 and p s4 p z4 = e p s4 T s p z5 = e p s5 T s (11) where p s3 and p s4 correspond to the natural frequency ω vol = 0.25ω cur and damping ratio ζ vol = 0.5.That gives us the set of closed-loop poles (see Fig. 6) as follows: p CL vol = 0 0 p z1 p z2 p z3 p z4 p z5 .
Having selected the poles of a closed system, it should be pointed out that for the multi-input plant, as analyzed here, there are many solutions for feedback gains, which allow obtaining the desired position of the poles.These possible solutions are not equivalent [33], [34].For an object with a large difference in dynamics between d-axis and q-axis, the place command in MATLAB does not ensure getting the expected dynamics for specific outputs.To be more specific, there is a possibility that in the closed-loop system with poles p CL vol , the control dynamic for i q will be affected not only by 0, p z1 , and p z2 poles but also by some or all of the remaining poles p z3 , p z4 , and p z5 , which would be undesired.Therefore, the eigenstructure assignment theorem is applied to design the feedback matrix [35], [36], [37].

C. Eigenstructure Assignment
Let us denote the eigenvalue of closed-loop state matrix and eigenvector associated with λ i by v i , where i = 1. ..7.Then, there exists the following equation: Set a matrix S i associate with each λ i and a compatibly partitioned matrix whose columns form a basis for the kernel of S i .Equation ( 12) can be formulated using partition matrix as Since columns of P i constitute a basis for the kernel of S i , it means that v i ∈ span{L i }; thus, v i can be expressed as 12) is satisfied.In [35], it is proved that the feedback matrix can be constructed based on the following equation: where If all the eigenvalues are real numbers, K v is calculated directly from For complex eigenvalues, some minor adjustments must be calculated to ensure that the feedback matrix contains only real numbers [35].In the case of a pair of conjugate eigenvalues λ i =λ * i+1 , we have Then, in (17), v i and v i+1 are replaced by v i and v i , respectively.The same rule is applied to the pairs of vectors w i , w i+1 and w i , w i .
For the two analyzed input systems, there are two independent solution vectors v i , which belong to the kernel of S i , and two corresponding vectors w i .Therefore, for a given set of closedloop poles p CL vol , there is no uniquely defined K v .The designer has the freedom of selecting one of the possible closed-loop eigenvector sets.In the analyzed system with two inputs and seven state variables, there is 2 7 = 128 possible combinations of eigenvector set.Because there is a need to minimize the interaction between state variables, in other words, to make the dynamics of i q independent of the most dominant closed-loop poles, the designer should select the set with the most orthogonal eigenvectors.This set can be easily numerically found by searching the minimum value of eigenvector dot product for all the possible sets.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Next, after calculating K v from ( 17), using zero-pole compensation at the z plane origin, N v is defined as follows:

D. Voltage Controller Dynamic
The performance of the designed voltage controller is presented in Fig. 7.In the period from 5 to 15 ms, there is a pulse of load current.At the v dc plot, we can observe the desired disturbance rejection properties.The system has the same dynamic as current controller in terms of i q control, which is shown at step changes of i ref q in 20 and 25 ms.The compliance with the assumed controller bandwidth is also visible at the reference step response in time instance 30 ms.The consequences of the demand for such high dynamics are large instantaneous values of current in transient states (7 and 42 ms).Because the peak current exceeds the I max value, this provides a strong justification for applying the multithreaded control concept.

IV. SIMULATION RESULTS OF MTSC FOR DISCRETE LINEAR PLANT
The MTSC for the grid-connected converter (see Fig. 2) has been verified in a simulation study.The results are provided in Fig. 8.The ability of the system to correctly impose the limits on the current component i d and the control signal has been presented for the test scenario, which includes the following: 1) step changes of load current i load (at time 5, 40, 75, and 90 ms); 2) a grid voltage sag in the period from 20 to 35 ms; 3) step changes of i ref q at time 50 and 65 ms.

TABLE II STABILITY MARGIN VARIATION
In Fig. 8, the operation mode of the converter is presented.In time marked with blue color, the controller is in the voltage control mode.It means that the control signal applied to the plant is the signal produced by the SFVC u v .This happens for the majority of the system operation time.However, in the transient states, the mode might be changed to impose the predefined constraints.The intervals marked with red color correspond to the current control mode.This means the realization of the current saturation for the grid converter.The control signal applied to the plant comes from one of SFCCs and is either u min c or u max c , depending on whether the lower or upper current threshold is reached.In time intervals marked with yellow color, the system goes into the control signal saturation mode.This result shows that the final dynamics of the system is the combination of the dynamics designed for the current and voltage controllers.For example, in a period just after the load step at 5 ms (see Fig. 8), the response corresponds to the one presented in Fig. 5 at 5 ms.In turn, just after the load step at 90 ms, the response corresponds to the one presented in Fig. 7 at 20 ms.
Since the stability criterion was not taken into account at the tuning stage, the system should also be analyzed in this respect.Table II shows the results of a stability analysis at the plant inputs, showing the sensitivity to plant parameters' variation.Two values are provided for each case.The first one corresponds to the SFCC and the second one to the SFVC.The control system robustness directly results from the robustness of the FSF controllers implemented as parallel subsystems.The robustness is not weakened by the limitation mechanism of the state variable range itself.In addition, there is no negative inverse impact, i.e., the change in the plant parameters does not affect the ability to impose limits.The proposed method is not based on the plant model, which distinguishes it from other methods of imposing limits in FSF controllers [38].

V. EXPERIMENTAL RESULTS
The experimental validation of the proposed control structure was carried out at the laboratory setup consistent with the parameters provided in Table I.The view of the setup is shown in Fig. 9. Two three-phase voltage source converters with a common dc circuit have been used in the experimental setup.The first one was operated as a grid-side converter, and  the second one was used an active load.Both the converters were controlled by a control board with the TMS320F28335 microcontroller.
The MTSC performance at the step load condition is illustrated in Fig. 10.At time 5 ms, a load current pulse lasting 60 ms starts.In the period between 6 and 11 ms, the system goes into the current control mode, using SFCC, to impose the current limitation.The amplitude of the phase current matches the predefined threshold in the transient state.During that time, v dc increases at a constant rate.The described design of the MTSC ensures that the system goes back to the voltage control thread in the right time and with the appropriate state of integral term; therefore, the character of response remains as desired.
A longer phase of operation in the current saturation mode is presented for the grid voltage dip case in Fig. 11.At time 30 ms, grid voltage starts to decrease, and this, in turn, causes an increase in grid current.At time 70 ms, the grid current reaches the maximum value.The consequence of imposing current saturation is the drop in output voltage v dc .The effect of the independent design of i q current dynamics not coupled with the v dc dynamics is presented in Fig. 12.In this case, the system remains on the main thread using SFVC.Thanks to the selection of eigenvectors with high orthogonality, the dynamics of i q for SFVC and SFCC is the same.
The presented experimental results demonstrate the accomplishment of all the targets for the described controller.

VI. CONCLUSION
The SFC is a very effective solution from the control theory point of view.Unfortunately, its standard implementation with a single instance of such a controller suffers from a lack of straightforward methods of imposing constrains on the state variables.In most practical applications, this is prohibitive and, hence, is less popular among practitioners, who often discard this kind of controller in favor of a cascaded control structure.
Often, the tuning cascaded control structure has its limitations coming from the fact that the bandwidth of the outer loop has to be significantly lowered with respect to the bandwidth of the inner control loop, if tuned in the loop-at-a-time fashion, which is standard practice.This restriction does not apply to the state controller, which is of a parallel structure, and all the feedback loops are at the same hierarchy level.Control quality, in terms of achieving the desired step-response character and disturbance rejection properties, can then outcompete the one offered by the cascaded controllers.
The proposed MTSC retained all the benefits an FSF and, at the same time, imposed limits on the state variables as well on control signals.This made it practical in real-life engineering control tasks.We believed that this is a bridging technology toward transitioning from cascaded to parallel control structures in many industrial applications, including power electronics and drives.Moreover, the control structures of FSF architecture were also fully capable of being extended to accommodate oscillatory terms, if this was required by a specific application.
The developed algorithm was verified experimentally, and the obtained results confirmed its efficacy.This was the very first fully fledged demonstration of the viability of the algorithm in a physical control system.However, the topology of the proposed multithreaded state control was not application specific, i.e., the number of state controllers may vary with the application as it is directly linked to the number of limits one needs to impose, but the overall concept stays the same.Further research will be directed toward the implementation of the algorithm in a physical drive system and a grid converter with an LCL filter.There are potential significant benefits for the system with the LCL filter, resulting from the usage of the MTSC instead of classical methods, i.e., there is a possibility of effective imposing restrictions in dynamic states on the capacitor voltage and currents at both the inductors.He is currently an Assistant Professor with the Institute of Control and Industrial Electronics, Faculty of Electrical Engineering, WUT.His main research interests include modeling and development of power converters, advanced control of power electronics, especially in the area of grid-connected converters.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

Fig. 1 .
Fig. 1.Simplified block diagrams of the control structure for the grid converter.(a) Schematic diagram of the plant.(b) Cascade output feedback control.(c) Cascade control with the SFCC.(d) SFVC.

Fig. 2 .
Fig. 2. Block diagram of the MTSC for a grid converter.

d
and i min d for the SFCCs indicate the maximum and minimum values of the d-axis current component, respectively.

Fig. 5 .
Fig. 5. Numerical results showing the theoretical performance of the designed SFCC.

Fig. 7 .
Fig. 7. Numerical results showing the theoretical performance of the designed SFVC.

Fig. 12 .
Fig. 12. Experimental results for pulse of i ref q .(a) Grid line-to-line voltages.(b) Phase currents.

Bartłomiej
Ufnalski (Senior Member, IEEE) was born in Warsaw, Poland.He received the M.Sc.and Ph.D. degrees in electrical engineering in 1999 and 2005, respectively, and the D.Sc.degree in automatic control and robotics in 2016, all from the Warsaw University of Technology, Warsaw.Since 2017, he has been Associate Professor with the Institute of Control and Industrial Electronics, Faculty of Electrical Engineering, Warsaw University of Technology, where he is currently the Head of the Electrical Drive Division and the Head of the Energy Conversion and Storage Research Center.His research interests include automatic control in power electronics and drives, with emphasis on repetitive, nonlinear, and adaptive control algorithms for these systems.Dr. Ufnalski is a Member of the International Scientific Committee of the European Power Electronics and Drives Association.Andrzej Gałecki (Member, IEEE) was born in Wegrow, Poland.He received the M.Sc.and Ph.D. degrees in electrical engineering from the Warsaw University of Technology (WUT), Warsaw, Poland, in 2010 and 2019, respectively.