Actual Reasons Involving Turn-Off Losses Improvement With Increasing Load and Gate Resistance in MOSFETs Enhanced With Kelvin Source

This article explains the actual reasons behind the improvement in terms of turn-off energy losses (Eoff) reduction, obtained using Kelvin pin (4-lead, 4L) mosfets instead of 3L ones. Eoff increases by increasing gate resistance and load, but the experimental results reveal that the increment is less in 4L than in 3L mosfets. Analyzing the turn-off waveforms and adopting circuit analysis, the article first proves that the common argument about the undesired effect of the parasitic source inductance in 3L mosfets is misleading. Then, the reasons behind the aforesaid improvement in 4L mosfets with increasing gate resistance and load are described by means of the derived analytical expressions. Finally, the analysis of the equations has provided helpful information at the design stage, also accounting for the different device technologies. In particular, the improvement obtained using 4L mosfets reduces as the driving loop parasitic inductance increases and evanesces if its value becomes comparable with the power loop parasitic inductance.


I. INTRODUCTION
T HE design of efficient power converters is highly desirable to obtain environmental-friendly electric systems and reduce operating costs [1], [2], [3]. Power density increment is more and more required in many applications and from consumers [4]. The wide-bandgap (WBG) devices present good features that facilitate the achievement of these targets [5], [6]. Using an additional source, the Kelvin pin, is helpful to obtain a highly efficient and compact converter also adopting Silicon devices, thus benefiting from the technology maturity. On the other hand, the WBG devices can benefit from the use of the Kelvin pin too [7], [8]. Moreover, these advantages deriving from the Kelvin pin have also been proved in other device technologies [9]. The main problem, solved by 4L MOSFET, is the coupling between the driving and power loop due to the source parasitic inductance of the 3L. Some works have proposed to optimize the gate driver to mitigate the effect of this parasitic inductance [10], [11], [12]. In other cases, layout and packaging guidelines have been proposed [13], [14], [15], [16]. However, using the 4L MOSFET is the best state-of-art solution.
The advantages deriving from the use of a MOSFET equipped with a Kelvin pin (4L MOSFET) in comparison with a 3-lead device (3L MOSFET) increase as the current increases, making the former interesting in high currents applications [17]. More specifically, for both kinds of packages, the switching losses increase with increasing current, but the increment is lower in 4L MOSFETs compared to 3L ones as the current increases. The lower switching losses involve lower heating of the device and other components, thus improving the converter lifetime and/or reducing the need for bulky cooling systems. Moreover, 3L MOSFET could suffer undesired self-turn-ON at the turn-OFF [18]. Finally, the parasitic inductance can affect the protection performance under overcurrent/short circuit conditions [19].
Regardless of the technology, these advantages obtained during the commutation are commonly attributed to the decoupling of the driving and power loops [20], [21]. More specifically, in 3L MOSFETs, during the turn-OFF, the decreasing current opposites to the reduction of the gate-source voltage, thus slowing down the switching [22]. This is due to the voltage drop across the source parasitic inductance, which affects the gate-source voltage since this inductance belongs both to the driving and power loops [see Fig. 1(a)] [23]. In 4L MOSFET, this voltage drop does not affect the gate-source voltage since the source parasitic inductance belongs to the power loop only [see Fig. 1 Similar reasoning is usually adopted to explain the advantages during the turn-ON [24]. Indeed, such an interpretation is valid only for the turn-ON, not for the turn-OFF, as we will prove in the following.
The contributions of this article are listed as follows.
1) It proves, in Section III, that the common explanation (consolidated in academia and industry) about the effect of the source inductance on the turn-OFF of 3L and 4L MOSFETs is misleading. The proof is obtained by comparing the common turn-OFF equations with the experimental turn-OFF waveforms reported in this article and literature. 2) It highlights, in Section IV, the actual reasons why turn-OFF energy losses increase less in 4L than in 3L MOSFETs. with increasing gate resistance and load current (this is the main contribution).
3) It provides, in Section IV, practical information for the layout designer. The rest of this article is organized as follows. Section II reports: 1) the comparison between 3L and 4L MOSFETs presented so far by Academia and Industry; 2) a test vehicle to compare the switching losses for increasing gate resistance and load current, for confirmation purposes. Section III reports: 1) the well-consolidated phenomenon interpretation in Academia and Industry by recalling the turn-OFF equations usually adopted to support this common interpretation; 2) some test vehicle turn-OFF switching waveforms used for proving that the aforementioned common interpretation is misleading, and results from the literature used with the same purpose. Section IV reports: 1) the correct circuit analysis of 3L MOSFETs, which is also based on the analysis reported in Section III; 2) the circuit analysis of 4L MOSFETs; 3) a comparison of the results of the two circuit analyses to highlight the actual reasons for which the difference between the power losses of 3L and 4L MOSFETs increases with increasing gate resistance and load current. Finally, Section V concludes this article.

A. Academia and Industry Experience
A demonstration board has been prepared in [25] to verify the impact of parasitic inductance on both the commutation times and power losses of 3L and 4L MOSFET. The results revealed that the improvement obtained by 4L MOSFET increases as the load current increases. An experimental comparison of the turn-ON and turn-OFF switching losses in 3L and 4L MOSFETs has been presented in [20]. The results have shown that both switching losses increases as the gate resistance increases but the slope of the losses increment is larger in 3L MOSFET. The improvements obtained using a 4L MOSFET are discussed and analyzed in [26]. Then, a new technique based on an inductive rather than resistive gate driver impedance was proposed to mitigate or even completely compensate for the effects of source inductance in 3L MOSFET. In [17], the experimental results highlighted that the 4L MOSFET performs better than the 3L one in high currents applications, while the higher cost of the former limits their use in low-current applications. A comparison of the double pulse test switching losses of a 3L and 4L SiC MOSFET has been reported in [27]. The comparison has highlighted that the difference between the case temperature of the two devices increases as the load increases as well as the gate resistance increases. The gate-source spikes occurring during the MOSFET commutation have been analyzed in [18] to highlight the advantages enabled by 4L devices in terms of spike reduction.
The turn-ON energy losses measured experimentally for different load conditions in [24] have shown that the energy advantage of the 4L is reduced at low load. This is due to the drainsource voltage waveform of the 3L device, which is more similar to those of the 4L one at a low current. More specifically, the drain-source voltage waveform of the 3L device usually presents a plateau due to the voltage drop across the parasitic inductances during the current rising and due to the clamp imposed by the diode until it conducts. The higher current speed of the 4L MOS-FET involves that the plateau should occur at a lower value of the drain-source voltage, and then this voltage takes longer to reach the clamp value. On the other hand, the higher current speed of a 4L MOSFET involves a reduced time necessary for it to reach the load current, thus unclamping the diode earlier. Consequently, the drain-source plateau does not occur, thus reducing turn-ON losses.
The switching loss in the 4L SiC MOSFETs is lower affected by package degradation, and the difference with the 3L ones increases at high currents [28]. When the gate resistance is decreased to increase the turn-ON speed of a 3L MOSFET, in order to reduce the gap with the 4L performance, high turn-ON oscillations occur. In [29], a gate driver able to suppress these oscillations has been proposed. In [30], the results highlighted that the switching energy reduction in 4L MOSFETs increases as the load increases. This advantage also intensifies as the gate resistance increases. Similarly, this [31] has also highlighted that 4L MOSFETs present reduced switching losses, oscillations, and voltage spikes than 3L ones, and the improvement is more significant at high currents.
An Infineon application note [32] has also confirmed that the difference between the switching losses between 3L and 4L MOSFETs increases with increasing load current. Also, an STMicroelectronics application note [33] has underlined that this difference also increases with increasing gate resistance.

B. Experimental Analysis of 3L and 4L MOSFETs E off : Impact of the Load Current and Gate Resistance
The analysis of the literature has revealed that the improvement obtained using 4L MOSFETs increases with increasing load Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. current and gate resistance. In this section, an independent investigation is carried out by evaluating the turn-OFF energy losses for different combinations of load current and gate resistance.
The test vehicle is the boost converter reported in Fig. 2. The test equipment consists of: Agilent ac-dc power supply 6813B; 1 GHz Oscilloscope Tektronix MS05140; Tektronix current probe TCP0030; Tektronix voltage passive probe (1:10); Passive voltage probe LeCroy P6139B (1:100); Flir Thermocamera; Power Meter Yokogawa WT310; Chroma 6314 electronic load. The gate driver is TC4422. Fig. 2(c) reports the point-to-point main parasitic components of the PCB. The parasitic inductors in series with L B are neglected since they present a negligible inductance compared to the boost inductor. For similar reasons, the parasitic resistors in series with the gate resistor are neglected. The device parasitics (due to bonding wire, terminals, and so on) are inside the MOSFET block. Table I reports quantities related to the converter and the devices [34]. Fig. 3 reports the variation of the energy loss, Eoff, during the turn-OFF versus increasing load for different gate resistances. The results highlight that the losses increase more in 3-L MOSFET than in 4-L with increasing load. Therefore, the improvement, in terms of power loss reduction, obtained using 4-lead MOSFETs actually increases as the load increases. An interesting aspect arising from the results is that the gate resistance modulates this phenomenon. More specifically, the loss difference between the 3L and 4L MOSFETs increases with increasing gate resistance. For example, at full load, the loss difference between 3L and 4L quadruples when passing from R G = 3.9 to R G = 15. The same effect occurs on the turn-ON energy losses, although the reasons are different, as proved by Gaito et al. [24].

III. COMMON MISLEADING INTERPRETATION OF THE IMPACT OF THE SOURCE PARASITIC INDUCTOR ON THE TURN-OFF LOSSES IN 3L MOSFETS
This section first recalls the common explanation about the effect of the source inductance on the turn-OFF of 3L and 4L MOSFETs. It is worth noticing that this explanation is well consolidated in academia and industry as it emerged from the literature analysis, and it has led to a misleading interpretation of the impact of the source parasitic inductor on the turn-OFF losses of 3L and 4L MOSFETs. Some experimental waveforms of the turn-OFF for different gate resistance values and load conditions, which are analyzed in Section II to obtain Fig. 3 are reported in the following to highlight the incorrectness of the common explanation.

A. Common Reasoning About the Undesired Interaction Between Current and Gate-Source Voltage During 3L MOSFET Turn-Off
In a power converter, there are many parasitic elements due to the PCB and, more in general, due to the interconnection among devices, components, power supply, and so on. Even an ideal design of the converter that eliminates any parasitic element cannot totally avoid the presence of parasitic components that are due to the MOSFET itself. Anyway, the MOSFET parasitic components are sufficient to pinpoint the effect of the source inductance since the difference with an actual case is mainly quantitative instead of qualitative. Fig. 1 shows a significant case where only the parasitic capacitance and inductance of the MOSFET and some PCB parasitic components are added to the circuit of the boost converter. More specifically (also considering Fig. 8) they are as follows: L d parasitic inductance from the internal drain terminal (node D) to the lead connection with the PCB, plus the parasitic inductance from that point to node E; L s parasitic inductance from the internal source terminal (node S) to the lead connection with the PCB, plus the parasitic inductance from that point to node N; L g parasitic inductance from the internal gate terminal (node G) to the lead connection with the PCB, plus the parasitic inductance of the driver edge.
The boost converter has been chosen as the test vehicle because it enables easily setting the MOSFET current when the turn-OFF starts, by a simple tuning of the electric load. In the following analysis, the input and output voltages have been considered constant without losing generality.
When the 3L MOSFET is considered, the gate-source voltage v GS , across the parasitic capacitor c gs can be obtained by applying the Kirchhoff's voltage law (KVL) to the driving loop [see Fig. 1 During the turn-OFF, V G is zero (or negative in SiC MOSFETs) and the decreasing v GS asymptotically tends to this value. The MOSFET current is decreasing, then the derivative of i S is negative, thus involving a positive quantity in (1), which opposes to the reduction of v GS . Consequently, after a given time τ , from the beginning of turn-OFF, the v GS value is greater than if the current i S does not affect it (i.e., when L S is zero) By assuming that the turn-OFF switching losses occur while the MOSFET is in the active region, recalling that the MOSFET current is proportional to the gate-source voltage in this region and according to the previous considerations about v GS (relation 2), it follows that, at a given time τ , after the start of the turn-OFF, the value of i S is greater than if i S itself has no effect on v GS (i.e., when L S is zero) In other terms, the decreasing i S delays the v GS commutation that, in turn, delays the i S lowering. Such behavior is undesired because it involves higher turn-OFF switching time and losses. Similar considerations can be obtained when focusing on the i D .
Instead, when the 4L MOSFET is considered, v GS is obtained by applying the KVL to a different driving loop arising from the different topology [see Fig. 1 Equation (5) highlights that, in the case of 4L MOSFET, i S does not affect v GS regardless of the L S value.

B. Analysis of the Experimental Results Under Variable Load
In the following, first, the waveforms of a turn-OFF (see Fig. 4) are analyzed to prove that the reasoning described in Section A is misleading. After that, more results are reported and discussed to generalize this conclusion. It is worth noticing that the following analysis does not aim at proving that the parasitic source inductance does not delay the turn-OFF in 3L MOSFET. This inductance actually slows the turn-OFF but the actual reasons are those described in Section IV. Hence, the following analysis aims only at proving that the typical argumentation described in Section III-A is misleading. Of course, understanding the correct mechanism leads to helpful information at the design stage of the converter as it will be shown in Section IV-C. Fig. 4 reports the waveforms of the 3L MOSFET current (red), gate-source voltage (green), and drain-source voltage (blue) at the maximum load with R G = 3.9 Ω. The sample rate is 1ns, while the time-step in the figure is 5 ns/division. The red dashed line represents the zero current axis. Similarly, the green and blue dashed lines represent the zero voltage axes for, respectively, the gate-source and drain-source voltage. The gray dotted line represents the voltage threshold of the device at 53.7°C (device temperature measured by the thermocamera).
The first vertical line indicates the instant t1, when the MOSFET current starts decreasing. Before, the current is constant (indeed it is slightly increasing) while the gate-source voltage is decreasing. Therefore, according to (1), the constant current does not delay the gate-source voltage reduction (indeed the slightly positive derivative implies that the current facilitates the reduction). At t1, the drain-source voltage is slightly higher than during the ON-time (see Fig. 4). Consequently, the MOSFET would be in the active region of the output characteristic if the gate-source voltage was greater than the threshold. On the other hand, as Fig. 4 highlights that the gate-source voltage (2.9 V) is below the threshold (3.8 V at 53.7°C, which is the temperature measured by the thermocamera), then relation 3 does not hold. Therefore, when the current derivative is negative and, consequently, the current could actually delay the gate-source voltage reduction [according to (1)], the v GS commutation does not delay the current reduction. The second vertical line indicates the instant t2, when the sudden reduction of the MOSFET current starts, i.e., the magnitude of the derivative current is very high, then according to (1) the reduction of v GS should be strongly delayed. It occurs when v DS is about equal to the converter input voltage, which implies that the boost inductor current i B [see Fig. 1(a)], does not increase more. At t2, the gate-source voltage is widely below the threshold voltage, and then the previous considerations (made for t1) are still valid. In conclusion, the common reasoning about the effect of the parasitic source inductance based on assuming that the falling current delays the gate-source voltage commutation that, in turn, delays the former is misleading. This deduction can be generalized by the following analysis.
The difference between the gate-source voltage and the threshold voltage for different values of gate resistance and load conditions is shown in Fig. 5. Such an approach accounts for the reduction of the threshold voltage with increasing temperature [35]. The temperature increases when R G and the load increase, involving higher power losses. The difference computed at the instant t2 (dotted lines) is always negative, thus, relation 3 does not hold regardless of the value of R G and the load condition. Therefore, the v GS commutation does not delay the current reduction. The difference computed at t1 (solid lines) is negative for a typical R G value (3.9 Ω) regardless of the load condition, hence, the previous considerations are still valid. The difference is positive when R G is high (15 Ω), especially at a high load. However, it can be demonstrated that the MOSFET current reduction, in t1-t2, is caused by the capacitive behavior of the diode instead of the MOSFET behavior in the active region. In other words, even in this case, the MOSFET current reduction is not due to relation 3. Hence, the common reasoning is misleading even in these cases.
To demonstrate the previous statement, it is sufficient to analyze just the case with the largest positive difference between the gate-source voltage and the threshold voltage (R G = 15 Ω, load = 100%). In the interval t1-t2, the diode (see Fig. 1) is in the reverse region and it behaves similarly to a capacitor whose differential capacitance c JD , is reported in Fig. 6 as a function of the reverse voltage v R .
Recalling that the voltage across the diode v Diode is It follows that, in the interval t1-t2, the diode current i o (see Fig. 1) can be expressed as Then, in this interval, the diode current is positive since the drain-source voltage increases. Moreover, the voltage increment rate dv DS dt is also increasing, as shown in Fig. 7, which refers to the analyzed case (such a typical behavior is shown in Fig. 4  too). Then, the diode current is increasing in the interval t1-t2. According to (6), the reverse voltage is decreasing in this interval and, consequently, according to Fig. 6, c JD is increasing, thus, further supporting the increment of the capacitive current i o flowing through the diode. This current can be estimated by using (7) and the blue curve in Fig. 7(b). Then, looking at node E in Fig. 8, an estimation of the waveform of the inductor current i B [see violet curve in Fig. 7(b)] can be obtained by adding, point-to-point, the estimated current i 0 to the measured MOSFET current i D (see red line in Fig. 7), Therefore, looking again at node E in Fig. 8, this proves that the increasing capacitive current is the cause of the reduction of the current flowing through the MOSFET and, consequently, the MOSFET current reduction is not due to the v GS reduction. So it confirms once more that the reasoning of Section III-A is misleading. In fact, at t 2 , the gate voltage is sufficiently below the threshold to affirm that relation 3 and, consequently, relations 4 and 5 are not valid after t2, when there is a sudden decrease of the MOSFET current. Therefore, the knowledge of the current through the diode and the inductor after t2 is not important for the aim of the proof and, consequently, they have not been estimated.
Furthermore, it is worth noticing that: the MOSFET derivative current is small in the interval t1-t2 [see Fig. 7(b)]; the difference between the MOSFET gate-source voltage and the threshold is only about 1 V in this interval, which is not sufficient to obtain 18 A according to the output characteristic.
The previous discussion can be applied to the switching waveforms reported in the literature. For example, the analysis of the turn-OFF waveforms reported in [21] highlights that at t1 the gate-source voltage is equal to the threshold voltage while at t2 it is lower than the threshold voltage. Hence, the same considerations made referring to Fig. 4 are confirmed. That is, relation 3 does not hold at t1 and later when the current derivative is negative, and, consequently, the current could actually delay the gate-source voltage reduction [see according to (1)] and the v GS commutation does not delay the current reduction. The analysis of the turn-OFF waveforms reported in [23] reveals, once again, that relation 3 does not hold when the current derivative is negative, then the common interpretation is misleading since the discussions about Fig. 4 are valid also in this case. The analysis of the turn-OFF waveforms reported in [28] reveals that at t2 the previous considerations as well as those related to Fig. 4 hold true, while a different behavior arises at t1. In detail, at t1, the gate-source voltage is greater than the threshold. However, comparing the gate-voltage of 3L and 4L MOSFETs in [28], it is evident that they are similar in the interval t1-t2, consequently, the negative current derivative does not have an additional undesired impact on the gate-source voltage decrement in 3L MOSFETs in this interval. Hence, this proves, again, that the common reasoning about the source parasitic inductance impact is misleading.

IV. FORMULATION OF THE ACTUAL REASONS ENABLING THE TURN-OFF LOSSES REDUCTION IN 4L MOSFET
The actual reasons involving the reduction of the turn-OFF losses in 4L MOSFET are analytically investigated in this section. Moreover, the increment of the difference between the turn-OFF losses of 3L and 4L MOSFETs with increasing gate resistance and load conditions is also analytically obtained.
Finally, useful considerations regarding the different technologies are reported based on the obtained equations. Fig. 8 shows a schematic of a boost converter during the switch turn-OFF, when a 3L MOSFET is used. The figure is valid once the v GS is below (or, according to the discussion about Fig. 7, close to) the MOSFET threshold. Some parasitic components of the switch, e.g., parasitic inductances of the bonding wires and leads, and the PCB, e.g., parasitic inductances of the copper/aluminium traces connecting the converter components, are reported.

A. Analysis of 3L MOSFETs Turn-Off
The total parasitic inductance in the input path (from node N to A-plus from A to E) can be neglected since it is in series with the boost inductor L B . The total parasitic inductance in the output path (from node E to U-plus from U to N, comprising, for example, the ones due to diode leads) cannot be neglected and should be reported in the circuit. On the other hand, as will be apparent in the following, this parasitic inductance does not affect the specific analysis, thus, it has been omitted.
In the figure, upper letters indicate quantities that do not vary during the analyzed interval, while lower ones indicate variable quantities. The subscripts of the symbols indicating actual components are upper letters, while lower letters are used for the subscript of parasitic components. The input and output capacitors of the converter have been modeled with constant voltage sources since their voltages can be assumed to be almost constant.
The identification of the impact of the drain current, i D , on its derivative function is the target of the following analysis. To this aim, a reduced sparse tableau approach for circuit analysis has been adopted. In Fig. 8, are reported the nodes (A, E, U, D, G, S and N) and branches of a graph related to the circuit. Each component of the circuit represents a branch of the graph, except for the driver branch, which comprises some circuit components, which are inside the blue-dashed polygon. The twigs of a spanning tree (ST) are colored with double-red-straight lines, while the co-tree branches are colored with double-green-dashed lines.
The following equations are independent of each other since they are obtained by applying the Kirchhoff's current law to the fundamental cut sets (FC).
FC1: driver branch, c gs , c gd FC5: L d , V IN , V OUT , and FC3 and FC4 FC6: c ds , c gd ,V IN , V OUT , and FC3 and FC4 Other independent equations are obtained by applying the KVL to the fundamental loops (FL). FL1: c gs , driver branch, FL2: c gd , driver branch, L s , c ds A well-known equation is obtained by combining them The following equation is obtained by substituting (14) in (11): which, in turn, can be rewritten as The following equation is obtained by substituting (14) and (16) in (8): The following equation is obtained by subtracting (8) from (9) and then substituting (17): Eventually, the unnumbered equation shown at the bottom of the next page is obtained by firstly substituting (10), (17) and (18) in (12), then by explicitly expressing the derivative of the drain current This equation highlights the effect of the drain current on its derivative during the subperiod of the turn-OFF in which the current actually varies.

B. Analysis of 4L MOSFETs Turn-Off
A similar relation can be obtained for a 4L MOSFET. In this perspective, as Fig. 9 reveals, (8), (10), and (11) are still valid because the related FCs (1, 3, 4, 5, 6) are equal to the ones in Fig. 8. Hence, (16) and, consequently, (17) are still valid. Obviously, (14) still holds. On the other hand, FC2 and the related equation are changed as follows.
FC2-4L: L s , V IN , V OUT , and FC3 and FC4 The two FLs considered for the circuit with 3L MOSFET are not valid for the one with 4L MOSFET, as shown in Fig. 9.
Moreover, the driver branch also includes the parasitic Kelvin inductance, L k . Then, the two FLs and the related equations change as follows in the case of 4L MOSFET, although they are still similar to the ones of 3L MOSFETs [(12) and (13)].
FL1-4L: c gs , driver branch (now includes L k ) FL2: c gd , driver branch (now includes L k ), c ds Equation (23) is obtained by first substituting (10) and (17) in (21), then by explicitly expressing the derivative of the drain current

C. Practical Design Consideration Emerging From the Comparison Between 3L and 4L MOSFETs Turn-Off
During the turn-OFF, the derivative of the drain current i D is negative. In (19) (3L) and (23) (4L), the contribution of the drain current term is negative since i D is positive. So, in both cases, an increasing drain current has an empowering effect on its derivative. Moreover, considering that the drain current is equal to the inductor current when the turn-OFF starts, and, in turn, the inductor current is proportional to the load current, i LOAD , then the magnitude of the current derivative, di D dt , increases with increasing load.
By summarizing, considering that as follows: 1) the greater the derivative, the faster the commutation, the lower the turn-ON switching losses; 2) the coefficient of the drain current in (23) (4L) is greater than the one in (19) (3L); 3) the initial value of the drain current is equal to the boost inductor current I B , when the turn-OFF begins; 4) the boost inductor current is proportional to i LOAD ; then the 4L MOSFET more and more outdoes the 3L one as the load increases.
More practical information for converters design can be obtained by evaluating the magnitude of the increment Δ of the derivative current in 4L MOSFET due to the current itself. By setting and considering (19) and (23) shown at the bottom of the next page, it follows: which can be rewritten as follows (26) shown at the bottom of the next page: Recalling that c gs c gd , the following relation is obtained: Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.
Interesting considerations arise from analyzing (27) in two extreme cases. More specifically, when When the device is turned-OFF, the initial value of the drain current is equal to the boost inductor current, which, in turn, is proportional to the load current. Therefore, (25), and its approximated relations (28) and (29), show that the improvement obtained using a 4L MOSFET (that is the difference between the power losses of 3L and 4L MOSFET) increases as the gate resistance increases as well as with increasing the load. This result is compliant with the experimental results in Fig. 3 and the literature, as discussed in Section II.
The analysis performed so far has only considered the MOSFET parasitic inductances. However, the main effect of the other parasitic inductances, e.g., those due to the PCB, can be translated in an increment of inductances L k and L s , thus extending the validity of this article and the usability of the obtained equations for providing practical information to the layout designer. In this perspective, the approximated (28) and (29) reveal that the improvement, i.e., Δ, obtained using 4L MOSFETs reduces as the Kelvin parasitic inductance increases. Moreover, in 28 and 29, when L g ≈ L k , the effect of the gate parasitic inductance on Δ cannot be neglected since this inductance is in series with the Kelvin one. In other words, in this case, it empowers the effect of the Kelvin inductance. Therefore, it presents the same effect related to the other parasitic components, e.g., the PCB parasitic inductances. According to this, the previous statement can be generalized: the improvement obtained using 4L MOSFETs reduces as the parasitic inductance of the driving loop increases.
Therefore, defining L dri as the parasitic inductance of the driving loop, which is obtained by summing the aforementioned contributions, (27) can be approximately rewritten as (30) This result is useful for the designer since it is suitable to define the following figure of merit: As said, in (31) the overall (device plus PCB and so on) source and Kelvin parasitic inductances are considered. Therefore, the following remarks based on the discussion of (31) are useful at the design stage.
Eq. (31) highlights that, for a given R G i D , the improvement depends on the MOSFET technology (that is, the ratio between the Miller and the gate-source capacitances) when α → 0. This condition, according to (24), occurs when the source inductance is equal to the Kelvin one. Generalizing, accounting for the overall parasitic inductances, the condition α → 0 occurs when the power loop inductance is equal to the one of the driver loop. The Kelvin parasitic inductance is usually small, thus obtaining this condition in a practical application means that the PCB layout should be strongly optimized to reduce the parasitic source inductance. However, it is challenging to obtain a power loop parasitic inductance equal to the driver loop one. Nevertheless, if the designer focuses on the reduction of the power loop inductance only and pays no attention to the driver loop, the α → 0 condition could occur, thus jeopardizing the advantages of the 4L MOSFET.
On the other hand, the impact of the MOSFET technology is negligible when the PCB layout involves power loop parasitic inductance significantly larger than the driver loop one (α 1), which is the most common case. Therefore, (31) provides information about the effectiveness of different layout solutions in terms of improvement achievable using a 4L MOSFET. The greater δ(α) the better the improvement a 4L MOSFET provides. Finally, (31) also highlights that the improvement decreases with increasing driver loop parasitic inductance. Therefore, the designer of the PCB layout must pay more attention to this inductance than those of the power loop and, similarly, the 4L v GS = V G − R G (c gs c ds + c gd (c gs + c ds )) dv DS dt + (c gs + c gd ) i D + − (L g + L k ) (c gs c ds + c gd (c gs + c ds )) d 2 Δ = L k [α (c gs + 2c gd ) + c gd ] (L g + L k ) [(L g + L k ) (c gs + c gd ) + αL k (c gs + 2c gd ) + L k c gd ] MOSFETs manufacturers must take more care of the kelvin and gate parasitic inductances than the source one. However, this concern must be even more considered at the PCB design stage since the additional parasitic contribution in the driving loop could be more significant than the one due to the package.

V. CONCLUSION
As well known, the adoption of an additional source terminal, the Kelvin pin, improves the switching performance of both Silicon-and WBG-based devices, especially at large loads. This article has first proved that the common reasoning about the causes of this improvement during the turn-OFF is misleading. After that, the correct reasons have been evinced by means of analytical circuit analysis. Information useful at the design stage of the converter has been highlighted by using the results of this analysis. The ratio between the Miller and the gate-source capacitances influences the improvement when the PCB design strongly reduces the parasitic source inductance or, more precisely, when similar parasitic inductance in both the driver and power loops are obtained (α → 0). In fact, in this case, the decoupling of the driver and power loop is not sufficient to fully benefit from the additional source terminal. Moreover, another important aspect that emerged from the study is that the improvement using 4L MOSFET could become ineffective in the presence of large parasitic inductance in the driving loop. Therefore, the layout designer has to reduce this contribution. However, it is worth noticing that these considerations account for the turn-OFF only. A proper design must also consider the behavior during the turn-ON [24].
Finally, this article lays the foundation for an in-depth understanding of the advantages of the Kelvin pin as well as the aspects that can hinder them in various applications. Starting from this point, the research could focus on extending this article to wide-bandgap devices as well as to applications where the devices are placed in parallel or in power modules adopting multi-die switches. Moreover, interesting future work is the identification of the equations describing the device voltage waveforms during the switching, and to esteem the turn-OFF switching losses by combining them with the equations obtained for the current.