A Family of Single-Phase Single-Stage Boost Inverters

H-bridge inverter is a common topology used for single-phase applications. Due to its limited voltage gain, a two-stage power conversion with a front-end dc–dc converter is usually adopted to accommodate the low dc source voltage. Recently, single-stage boost inverters are gaining significant interest due to their higher power efficiency and compactness. In this article, we present a family of boost inverters with continuous dc source current. By the incorporation of merely a power switch and a boost inductor to the first leg of H-bridge, voltage boosting and three-level generation can be simultaneously achieved within a single-stage operation. All potential topologies using the same number of components are derived. An extension to generate five voltage levels with voltage gain enhancement is also proposed. The operation of the proposed boost inverters is thoroughly analyzed. The simulation andexperimental results are presented for verification.

the modulation index of the sinusoidal pulsewidth modulation (PWM). For applications that require voltage boosting, such as grid-connected renewable energy or energy storage systems, a front-end dc-dc boost converter is usually mandatory to provide a sufficient dc-link voltage for the H-bridge inverter [1], [2]. A main downside of this two-stage power conversion structure is its low efficiency due to the high loss dissipation across the boost converter. The efficiency can be improved by making use of two paralleled front-end boost converters so that the interleaving operation between the two converters [3], [4] provides equal power sharing to reduce the losses in the dc-dc stage.
Instead of improving the two-stage topologies, significant research has been devoted to establishing single-stage inverters that inherit high-voltage-boosting capability. In [5] and [6], the positive terminal of an H-bridge is disconnected to constitute two boost converters with separate dc links. In order to prevent from dc offsets in the ac output, both converters are controlled with a sinusoidal varying duty cycle that not only generates a differential ac voltage but also enables their dc voltages to counteract each other at the same time. It is important to note that the generation of accurate differential ac voltage between the two dc links is highly complicated, rendering the design of control scheme for this topology challenging [7]. Moreover, the circulating current is another major concern that needs to be addressed.
Impedance-source inverters are another type of single-stage topologies that also gain popularity in recent years [8]. The earliest impedance-source inverter introduced in 2003 is referred to as a Z-source inverter [9]. As its name implies, a Z-shaped impedance network is integrated into the dc link of the conventional voltage-source inverter. Note that a shoot-through state is introduced when both switches in the same phase leg are ON, thereby allowing the impedance network to operate with a boosted dc-link voltage. Despite the drawbacks, such as a discontinuous input current and the need of several passive components for the impedance network, this pioneering contribution has inspired substantial related research works. A comprehensive review concerning the developments of impedance-source inverters can be found in [10], [11], and [12].
Recently, a distinctive family named split-source inverter (SSI) that features simplicity, high compactness, continuous input dc current, and continuous dc-link voltage has been explored [13], [14], [15], [16], [17]. It requires the incorporation of only one inductor, one capacitor, and two diodes into the This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/ H-bridge inverter. The single-stage configuration, which encompasses a boost converter, and an H-bridge inverter permit concurrent accomplishment of dc-link voltage boosting and ac voltage generation. The first topology introduced in [13] is later denoted as SSI in [14] to better reflect the circuit structure. A more compact design can be attained by relocating the dc source with the utilization of a commercial device that comprises two common-cathode diodes [18]. All the earlier SSIs, however, exhibit common shortcomings, such as high-frequency commutations of diodes, aggravated harmonics that are induced by the variable charging duty cycle of the boost inductor, and incapability of bidirectional power conversion.
A latter study improves the SSI by replacing the two diodes with two power MOSFETs [19]. When both the power MOSFETs operate in synchronous rectification mode at the line frequency, the modified SSI mitigates the high-frequency commutation of diodes and achieves bidirectional power flow. Besides, the presented hybrid quasi-sinusoidal and constant PWM scheme is able to provide a constant charging duty cycle for the boost inductor. It is also worth noting that the operations of the two H-bridge legs are effectively decoupled. One leg is responsible for inductor charging and dc-link voltage control, while the other leg is responsible for ac voltage generation according to the sinusoidal PWM.
A single-phase SSI topology that allows bidirectional power flow with reduced component count is presented in [20]. While preserving all the inherent merits of earlier SSIs, this so-called simplified SSI exhibits the highest compactness in the SSI family. Voltage boost function and three voltage levels generation are attained within a single-stage operation by merely the incorporation of an additional power switch into the first leg of an H-bridge. However, this topology suffers from high-frequency common-mode voltage (CMV) that is not feasible for applications, such as photovoltaic (PV) system. By using the same number of components, all potential topologies for single-stage boost inverters (BIs) are derived in this article. Some of the topologies in this BI family have been presented in the literature, while the remaining are novel. An extension from three-to five-level generation with voltage gain enhancement is also proposed. The rest of this article is organized as follows. In Section II, the BI family is introduced. Section III presents an extension to generate five voltage level and enhance voltage gain. Section IV compares the proposed topology with the state-of-the-art five-level inverters. The simulation and experimental results are discussed in Section V. Finally, Section VI concludes this article. Fig. 1 depicts the derivation of the BI family. Four basic topologies of the dc-dc boost converter are considered, and they are termed as BC1-BC4. By combining BCs with a similar circuit structure for their dc source and boost inductor, a total of six switched-boost cells (SBC1-SBC6) are obtained. In each SBC, a power switch is inserted into the half-bridge that introduces a new switching state for controlling the voltage of ac neutral. Six topologies of BI (BI1-BI6) are established by adding a half-bridge to each respective SBC. The first (BI1) and third (BI3) topology, as depicted in Fig. 1, has been introduced in [20] and [21], respectively, while the remaining BIs are novel that have not been presented in the literature.

II. THREE-LEVEL BIS
All BIs, as depicted in Fig. 1, can generate three voltage levels and boosting voltage gain simultaneously within a single-stage operation. They have four useful switching states, as shown in Fig. 2. The boost inductor can be charged by clamping it across the dc source during all voltage levels. To boost the voltage across capacitor, the boost inductor is discharged in series with the dc source during zero level.
To enable a single-stage dc-ac power conversion, PWM scheme, as depicted in Fig. 3, consists of two reference signals and a triangular carrier. A constant duty cycle D for charging the boost inductor is obtained by comparing the constant reference V const with the triangular carrier. By considering the volt-second balance of the boost inductor, the voltage across capacitor V C is Simultaneously, a sinewave reference is used to control the ac output with the amplitude of fundamental voltage as follows: where M =V sine /V tri is the modulation index. In this PWM scheme, the modulation index and constant duty cycle are coupled for achieving voltage boosting and ac voltage generation simultaneously in a single-stage operation. The minimum value for constant reference is given by the peak of sinewave reference. Therefore, the minimum constant duty cycle is equal to the inverter modulation index, D min = M. The ripple of capacitor voltage and ripple of inductor current consist of double-line-frequency and high-frequency components. A comprehensive ripple analysis can be referred to the article presented in [20]. Considering sinusoidal ac current, the capacitor voltage ripple ΔV C and inductor current ripple ΔI L can be, respectively, written as whereÎ o,1 is the amplitude of fundamental ac current, I L is the average dc source or inductor current, f o is the fundamental ac frequency, f s is the frequency of the triangular carrier, L is the inductance, and C is the capacitance.

III. EXTENDED FIVE-LEVEL TOPOLOGY WITH VOLTAGE GAIN ENHANCEMENT
All BIs, as depicted in Fig. 1, have the same component count and operating principle, as summarized in Fig. 2. The location of ac neutral point that determines the inverter CMV is their main distinctive feature. The ac neutral point of BI1, BI2, BI4,  and BI5 is separated from the dc source by a switch. Due to the switching of this switch, high-frequency CMV is introduced. Among the novel three-level BIs in Fig. 1, BI6 has an attractive structure when its ac neutral is directly connected to the positive terminal of the dc source. This implies that the neutral point voltage with respect to any dc source terminals is constant without high-frequency CMV. As shown in Fig. 4(a), the CMV across the parasitic capacitor is -V dc , which is constant. It prevents the risk of leakage current that is very feasible for applications, such as PV system. Therefore, this topology is considered for further extension.
To increase the number of voltage levels from three to five, a capacitor C 2 and four power switches S6-S9 are added, as shown in Fig. 4(b). Fig. 5 shows the switching states of the extended five-level topology [BI6(5L)]. Both capacitors C 1 and C 2 are charged in parallel. Therefore, their voltage is equal. Maximum voltage levels (+2 and -2) can be generated by discharging the capacitors in series. The magnitude of these maximum voltage levels is two times of the capacitor voltage. This implies that the voltage gain of BI6(5L) is double compared with BI6 for the same D and M.
As shown in Fig. 5, the boost inductor can be charged during any voltage levels. To discharge the boost inductor during 0, +1, or -1 level that ensures a constant duty cycle D for voltage boosting while simultaneously generating five-level ac voltage, a phase-shifted PWM scheme, as depicted in Fig. 6, is proposed. This PWM scheme not only enables a five-level generation that reduces the overall total harmonic distortion (THD) of ac output voltage but it also improves the harmonic spectrum. Compared with BI6, the dominant harmonics of ac voltage generated by BI6(5L) is extended to twice the triangular carrier frequency. This is beneficial for reducing the power filter requirement, i.e., smaller power filter for higher cutoff frequency.   To design BI6(5L), D min = M is considered. Modulation index M for the required voltage gain G is Two capacitors with the same value are considered as follows: Finally, the value of inductor can be calculated as follows: Table I summarizes the comparison of the proposed BI6(5L) with the state-of-the-art five-level inverters without highfrequency CMV. The topologies presented in [22], [23], [24], and [25] uses lesser number of power switches. However, their major drawbacks are limited voltage gain and discontinuous dc source current. A five-level inverter presented in [26] improved the voltage gain significantly, however, with a tradeoff of high switch count. In addition, the issue of discontinuous dc source current is not fully resolved. The capacitors of this topology are connected in series. They are individually charged by the boost inductor and requires voltage balancing control that unfortunately causes significant distortion to the inductor current due to limited redundant states. Inductor or dc source current with discontinuous and highly distorted waveform increases the overall rms value. Referring to the superposition theorem: I 2 rms = I 2 dc + I 2 1,rms + I 2 2,rms + . . ., where I rms is the overall rms current, I dc is the average current, I 1,rms is the rms current of the fundamental harmonic, etc., and the overall rms current would be significantly higher than the average current that increases power loss. This results in lower efficiency because the average power delivered by the inverter is contributed by the average current only. In addition, discontinuous dc source current is not feasible for applications, such as PV system. The proposed BI6(5L) provides the best performance that achieved high voltage gain and continuous dc source current while saving one switch count compared with the article presented in [26]. In addition, the number of conducting switches for inductor current in the proposed topology is also lesser than the article presented in [26].

V. SIMULATION AND EXPERIMENTAL RESULTS
Simulations were conducted using MATLAB/Simulink to verify the operation of the proposed BI6 and BI(5L). To compare the performance of both topologies, the same parameters are considered: V dc = 100 V, D = M = 0.8, C 1 = C 2 = 1000 μF, L = 1 mH, f s = 10 kHz, f o = 50 Hz, load resistance = 100 Ω, and load inductance = 100 mH.
By charging the boost inductor with a constant duty cycle of 0.8, the voltage of each capacitor in both topologies is boosted to 500 V. Three symmetrical voltage levels are generated by BI6 between 500 and -500 V and the amplitude of fundamental component is 400 V. The BI6(5L) has clear improvement that generates two additional voltage levels, i.e., +1000 V and -1000 V. With the same modulation index of 0.8, the amplitude of fundamental ac voltage generated by BI6(5L) is 800 V, double compared with BI6. Consequently, the output power of BI6(5L) in Fig. 7 is 2914 W, which is four times higher than 730 W of BI6. In addition, the fast Fourier transform (FFT) of ac voltage shows that the dominant harmonics of BI6(5L) are concentrated at 20 kHz that is twice compared with 10 kHz of BI6. In addition, the harmonics magnitude and overall THD of BI6(5L) are significantly lower that can improve the load current quality. These significant improvements are achieved while retaining the advantages of BI6, such as constant CMV, without high-frequency component and continuous dc source current.
For further verification, a low power (200 W) proof-ofconcept experimental prototype for BI6(5L) was implemented using silicon carbide MOSFETs (C3M0120090D) that have the ON-state resistance of 120 mΩ. The experimental prototype, as depicted in Fig. 8, was implemented to verify the operation of the proposed topology. The same parameters in simulation study were used, except V dc was reduced to 22 V to ensure that the dc source current is within 10-A current limit of the power supply. Table II summarizes the simulation and experimental parameters of BI6(5L). Phase-shifted PWM scheme, as presented in Fig. 6, was implemented in PLECS and switching signals were generated in real time using the RT Box controller. Fig. 9(a) shows the measured steady-state response at D = M = 0.8 under both R and RL load. It is clearly seen that the dc source or boost inductor L current is continuous. Zoomed-in to this current shows the charging and discharging duration of the inductor is 80 μs and 20 μs, respectively, that confirms the operating duty cycle (0.8) and frequency (10 kHz). The average voltage across both C 1 and C 2 is boosted to 110 V. By connecting these capacitors in series during [+2|C] state, the maximum voltage level generated by the BI6(5L) at D = 0.8  is 220 V, which is ten times higher than the dc source voltage. Five symmetrical voltage levels are observed in the ac output voltage between 220 and -220 V. The fundamental component of the ac voltage is 120 V rms, as reflected by the spectrum captured from the FFT analysis. This observation matches well with the theoretical finding, and it is only slightly less than the calculated value of 124 V rms. The measured voltage gain is 170/22 = 7.7, which is very close to the theoretical value of 8. The dominant harmonics of ac voltage are concentrated at 20 kHz that shows good agreement with the theoretical analysis and simulation results.
Experiments were repeated for D = M = 0.6 when the steady-state responses are summarized in Fig. 9(b). The inductor L is charged by the dc source for 60 μs and discharging to the capacitors for the remaining period in each switching cycle. Continuous inductor current is ensured while boosting   The voltage ripple of capacitors C 1 and C 2 was also measured, as shown in Fig. 11. The ripple waveforms are in phase and similar because the capacitors are charged in parallel that balances their voltage naturally. The measured voltage ripple is approximately 3 V that is slightly higher than 2.4 V calculated using (3). Fig. 12 continues to investigate the efficiency of the proposed topology by modeling the experimental prototype in simulation. Considering a peak ac output voltage of 330 V and dc source voltages of 100 V and 50 V, peak efficiency exceeding 98% can be achieved. The efficiency decreases with power level and more apparent reduction is observed for 50 V due to higher dc source current.

VI . CONCLUSION
A family of six three-level BIs was derived in this article. They are the most compact topologies for single-phase singlestage boost dc-ac power conversion that consists of only five power switches, one capacitor, and one inductor. One of the three-level BIs without high-frequency CMV was further extended to generate five voltage levels. The proposed BI6(5L) also enhanced voltage gain in addition to retaining the benefit of continuous dc source current. In addition, a phase-shifted PWM scheme was proposed that enabled the simultaneous generation of five voltage levels and voltage boosting within a single-stage operation and extended the frequency of dominant harmonics in ac voltage. Good agreement among analysis, simulation, and experimental results had verified the operation and feasibility of the proposed BI6 and BI(5L). Ricxon Jie Sheng Lim is currently working toward the undergraduate joint degree in electrical power engineering with the Singapore Institute of Technology, Singapore, and Newcastle University in Singapore, Singapore.
His research interests include power system engineering, power electronics, and simulation modeling.
Reza Barzegarkhoo (Graduate Student Member, IEEE) received the B.S. degree from the University of Guilan, Rasht, Iran, in 2010, and the M.S. degree from the Sahand University of Technology, Tabriz, Iran, in 2012, both in electrical power engineering. He is currently working toward the Ph.D. degree with the Faculty of Engineering and Information Technology, University of Technology Sydney, Sydney, NSW, Australia.
From 2016 to 2019, he was with the Guilan Electrical Energy Distribution Company, Rasht, as a Senior Grid-Exploiting Electrical Power Engineer. From June to September 2022, he was a Guest Scientist with the Chair of Power Electronics, Christian-Albrechts-Universitt zu Kiel (CAU) University, Kiel, Germany. He has authored and coauthored more than 40 journal/conference peer-review papers in the area of power electronics. His main research interests include the design and control of power electronic converters, multilevel voltage source inverters, switched-capacitor and switched-boost converters, photovoltaic transformerless grid-tied ac modules, and distributed generation systems.