Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode

Body-coupled powering (BCP) and body-coupled communication (BCC) utilize the human body channel as the wireless transmission medium, which shows less path loss around the body area. However, integrating both BCP and BCC requires multiple electrodes or alternating the uplink and downlink in the time domain, due to signal interferences and backflow between different paths. To address this issue, we propose a base station (BS) IC and a sensor node (SN) IC with BCP and BCC concurrency. At the BS, the adaptive self-interference cancellation (SI-C) structure suppresses the output signals that are coupled at the data receiver, enabling the concurrent uplink data recovery and downlink power delivery. At the SN, the ground domain of the uplink data path is separated from that of the downlink power/data path to suppress leakage between the paths. For regulated power supply in different ground domains, the cross-ground-domain power converter is designed with 89.1% efficiency. The ICs are implemented in a 40-nm 1P8M standard CMOS process, and BCC + BCP concurrent operations are successfully validated.

power delivery to prolong the battery lifetime.Therefore, to achieve the sustainable operation of the miniaturized BAN nodes distributed around the body, enabling the simultaneous wireless powering and communication is crucial (Fig. 1).
While the RF-based transmission is a popular wireless solution over the air, it suffers from antenna pattern distortion and the body shadowing effect under non-line-of-sight conditions near the body area [2].In contrast, by using the body as a forward transmission path and the parasitic capacitance as the return path, the capacitive body-coupled approach is shown to have an advantageous on-body path loss while being insusceptible to the body shadowing effect [3], [4], [5], [6], [7].In spite of channel variations when coupling condition changes, by leveraging on the advantageous body path loss, the body-coupled communication (BCC) could enable lower energy per bit [8], [9], [10], [11], [12], [13], whereas the body-coupled powering (BCP) could enable higher power efficiency and wider body area power coverage [14], [15], [16], [17], [18], [19].
To achieve a wireless BAN node with power sustainability, the integration of BCP and BCC has been studied, as illustrated in Fig. 2. In [16], [20], and [21], the BCP downlink, BCC downlink, and BCC uplink are incorporated at the base station (BS) and sensor node (SN), but these three paths are enabled in a time-domain multiplexing (TDM) fashion as they share the body channel.Switches dedicated to the path selection are required, where the synchronization  and switch control remain a challenge.In [22], TDM-based power downlink and data uplink are implemented, where path selection switches are avoided by introducing an electrode at the body interface of each path.To alleviate the need for synchronization between paths, the asynchronous data feedback mechanism that relies on the repetitive transmission of a data packet is proposed, causing redundancy and low data rate.The above TDM-based alternation of BCP and BCC paths poses a trade off between power delivery and data connectivity, which, in a multi-node setting, stops power delivery for all nodes when one is communicating and disrupts all communication when one requires power delivery.Moreover, it limits the communication spontaneity, for example, upon a hypoglycemia shock or a sudden abnormality in the biosignals.Lee et al. [23], on the other hand, alternates the power and data path based on the on-chip energy level at the SN.At the BS, the power transmitter and data receiver are separated into two devices to reduce coupling.Kim et al. [24] achieve the simultaneous power delivery and bi-directional communication for an implantable system, by separating the corresponding electrodes away from each other and separating the external power transmitter and data receiver into two devices, which limits the placement and challenges the miniaturization.
Therefore, to address the limitations in the conventional TDM-based BCP and BCC integration, this work proposes a BS IC and an SN IC that achieve the concurrent BCP downlink, BCC downlink, and BCC uplink, while using a single electrode at each device interface which avoids placement constraints and eases miniaturization, as shown in Fig. 3.
The rest of this article is organized as follows.Section II identifies the challenges for achieving the BCP and BCC concurrency, at both BS and SN.Section III then presents the system architecture, providing an overview of the corresponding solutions in this work.Sections IV and V introduce the detailed design of the proposed BS and SN, respectively.Section VI presents the circuit and on-body system-level measurement results, followed by Section VII which concludes this article.

II. CHALLENGES FOR BCP AND BCC CONCURRENCY
The challenges for achieving the BCP and BCC concurrency are summarized and illustrated in Fig. 4. Here, two electrodes are shown at each BS/SN to clarify the interrupting signal paths.Note that the challenges discussed below worsen as the two electrodes are placed closer or the TX amplitude gets higher.
At the BS, first, the strong output power signal (8.4VPP , for higher power delivery) saturates the data RX.With the body being a good coupling medium, the output power TX signal is coupled at the data RX front end, which is generally larger than the uplink data signal due to closer distance and thus stronger coupling.This saturates the RX front-end amplifier, disrupting the simultaneous uplink data recovery.Furthermore, it is worth noting that the characteristics of such interference signal coupled are subject to changes in the environmental or body-coupling condition.Second, the uplink data signal leaks to the circuit ground through the power TX output path.At power TX output, the parasitic capacitance between the output and circuit ground, or the output switching activity when enabled, forms a relatively low-impedance path to circuit ground (compared with the RX input impedance), degrading the received signal strength of the uplink data.
At the SN, first, the downlink power leaks to the circuit ground through the data TX output path.Similar to the case with power TX, the parasitic capacitance or switching activity at data TX forms a low-impedance path to ground, degrading the power level received at the SN power RX.Second, the uplink data TX output backflows into the power RX.The power RX input impedance is dynamically tracked for maximum power extraction and is comparable or lower than the environmental interface impedance.This causes the data TX signal to flow into the power RX, which not only degrades the output signal strength but also more importantly disrupts the rectifier operation and degrades the power recovery significantly.III.SYSTEM ARCHITECTURE Fig. 5 shows the proposed BS and SN system architecture [25], to address the challenges identified above.The BS consists of a power and command data TX, a data RX, and the adaptive self-interference cancellation (SI-C) circuit to cancel the interference of the coupled TX signal at the RX front end.The power and command data TX consists of an frequency-shift keying (FSK) baseband controller, a digital-controlled oscillator (DCO) that adopts the constant energy-per-cycle ring oscillator (CERO) structure [26] with open-loop for ample testing flexibility, a pulse generation block for driver switch control, and a charge-replenishing highvoltage (CR-HV) driver for reduced power consumption.The OOK data RX consists of an active low-pass filter, a low-noise amplifier (LNA), an envelope detector, a comparator, and a decoder.
The SN consists of a power RX, a data RX, and a data TX, where the circuit ground of the data TX output drivers (GND TX ) is separated from that of the other blocks (GND RX ), to avoid current backflow and leakage in between the uplink and downlink paths.The power RX consists of two detuned impedance boosting (DIB) and rectifier circuits [2], [27] for power recovery from the downlink FSK signal, as well as a dual-ground-domain boost power converter, to provide the regulated power supply for both ground domains while maintaining the ground separation.The data RX is passive receiver based, which performs the clock and data recovery for the downlink signal.The data TX consists of an OOK data preparation block in the GND RX domain, the tri-state output drivers in the GND TX domain, and a cross-ground-domain translation block for signal translation while maintaining the ground separation.

IV. BASE STATION DESIGN
This section elaborates on the BS structure that enables the concurrent power/data TX and data RX, including the adaptive SI-C circuits to cancel the HV TX interference at the data RX front end, as well as the band-stop LC filters to suppress uplink signal leakage.It also elaborates the CR-HV TX driver design, to reduce the BS power consumption and prolong its battery lifetime.

A. Adaptive Self-Interference Cancellation
To avoid saturating the data RX by the TX output signal (8.4VPP ), analog cancellation is performed at the data RX front end, where the TX output signal V HV is canceled with its 180 • out-of-phase replica signal V replica , as shown in Fig. 6.However, inherent to the capacitive body-coupling mechanism, the equivalent loading capacitance at the TX output interface C ENV is subject to variations when the electrode or environmental coupling condition changes, causing the actual output signal V HV slew rate to vary.To ensure accurate V HV cancellation in spite of such loading variations, an adaptive SI-C logic is proposed, which adaptively tunes the replica signal loading capacitance C SI−C , such that V replica matches with the actual output V HV .
The adaptive SI-C logic is illustrated in Fig. 7(a).In cases where C SI−C is larger than C ENV , V replica transitions slower than V HV .At V HV falling edge, this leads to negative peaks observed in the cancellation result V AVG .On the other hand, if C SI−C is smaller, positive peaks would occur.By using the cancellation result V AVG as the feedback to tune C SI−C toward the actual C ENV , the adaptive cancellation of V HV could be achieved.Fig. 7(b) shows the circuit implementation of the adaptive SI-C logic.To ensure a consistent interpretation of V AVG , the positive and negative peak detection, or V AVG evaluation, are activated upon V HV falling edge, where switches S1 and S2 are open, and S3 and S4 are closed; otherwise, S1 and S2 are closed and both V POS and V NEG are tied to "low."The upper path performs negative peak detection, where V NEG is pulled to "high" when V AVG amplitude falls below "0" within a hysteresis window and is tied to "low" otherwise.The lower path performs the positive peak detection, which pulls V POS Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.to "high" when a positive peak occurs in V AVG .By extracting the amplitude and polarity of V AVG , the loading capacitor bank C SI−C of replica signal V replica could be tuned by the C SI−C tuning logic, such that the cancellation results stay within the acceptable range.With V POS = "1" and V NEG = "0" which indicates a positive peak in V AVG and thus C SI−C < C ENV , the C SI−C control bit will be incremented.When V POS = "0" and V NEG = "1," C SI−C will be decremented.
The C SI−C capacitor bank switch design is worth noting, considering that the 8.4V PP (V HV and V replica output swing) across its source and drain.For a standard CMOS-compatible design, the on/off path of the high-voltage (HV) switch consists of four stacked transistors, such that each has a V DS within the nominal level.As Illustrated in Fig. 8, to avoid the additional level shifters or biasing circuits for control signal generation in different voltage domains, M P1 -M P6 are designed to enable the direct control of the HV switch by a nominal gate control signal V CTR .When V CTR = "0," M N1 -M N4 are configured to be a high-impedance inverted diode ladder to suppress the current flow from V SW to the ground (i.e., HV switch off), where V DS of each transistor approaches 1/4V SW .Under the worst case where V SW [i] = 4V DD (10 V theoretically but 8.4 V measured due to the charge pump conduction loss), the drain voltage of M N 1 -M N 4 is thus settled at V DD , 2V DD , 3V DD , and 4V DD , respectively, and V DS approaches 1V DD , within the nominal range.When V CTR = 1V DD for the HV switch on, M P2,4,6 is closed, such that V G of the four stacked transistors is settled around V CTR = 1V DD (2.5 V), and their V DS is settled around 0 V, enabling the current flow from V SW to ground.
The adaptive SI-C achieves the HV TX interference suppression by ∼40 dB (as shown in Section VI), avoiding the saturation of the active low-pass filter in the data RX signal chain, which further suppresses such out-of-band interference.Considering the small ON-resistance of the TX driver output and the small equivalent series resistance (ESR) of the inductors/capacitors, the main noise-contributing block introduced in the RX signal chain is the active low-pass filter required for further interference suppression.

B. Band-Stop Filter
To avoid the uplink data signal leakage through the CR-HV driver or the replica driver output, a band-stop LC filter is introduced at the TX output, as shown in Fig. 6.It resonates near the data uplink frequency (1 MHz) and thus exhibits high impedance to suppress the uplink signal leakage while having a low impedance near the downlink frequency for the normal TX operation.In this work, the bandstop LC filter has the values of 47 µH and 560 pF and is implemented off-chip.The Q factor of the bandstop LC filter should be designed as high as possible while tolerating the inaccuracies of the carrier frequency generated due to the PVT variations.

C. Charge-Replenishing High-Voltage Driver
For higher power delivery over the optimal BCP frequency span (up to 80 MHz [7]), an HV driving stage is designed at the BS TX.Compared with the implementations in the HV or SOI process [28], standard CMOS-compliant designs use the stacked MOS configurations with corresponding biasing techniques to tackle the overstress and gate-oxide reliability issue [22], [29], [30].Serneels et al. [29] and Luo and Ker [30] introduced the self-generated and adaptive gate biasing techniques, respectively.However, both biasing techniques consume high static current which increases with the switching speed.Dong et al. [22] introduced a four-stage charge-pump-based gate biasing technique, which removes the need for additional biasing circuits, level shifters, and tapered buffers, reducing the power consumption.However, the limited transition speed in [22] not only limits the driver switching frequency but also leads to increased power loss due to the crowbar current at a higher switching frequency.
To further minimize the power consumption, while achieving the 8.4V PP swing and up to 80-MHz frequency in standard CMOS, the CR-HV driver is introduced, as illustrated in  nodes 4-6 to transition to higher voltages (corresponding with voltages at C CP1 -C CP3 ).This enables the faster transition of node voltages, and, thus, higher achievable frequency and lower crowbar current.Moreover, by recycling and replenishing charges at the intermediate nodes, power drawn from the supply is reduced.

V. SENSOR NODE DESIGN
This section elaborates the SN design for uplink and downlink concurrency, including the ground-domain separation structure and techniques for leakage and backflow suppression, the dual-ground-domain dc-dc converter for regulated supply in both ground domains, as well as the downlink power and data co-recovery structure.

A. Sensor Node Leakage and Backflow Suppression
At the SN, both the power receiving path and the data output path exhibit low impedance, causing input signal leakage (through the output) and output signal backflow (to the input).To minimize such inter-path current flow, high impedance should be maintained in between the power RX and data TX paths.However, considering the good coupling characteristics of the human body and the need for miniaturization (i.e., downlink and uplink electrodes should be close), this work separates the circuit grounds of the two paths into GND RX and GND TX , to suppress the inter-path current flow.
The detailed ground-domain separation structure is illustrated in Fig. 10.In the CMOS process, GND RX is the p-substrate, whereas GND TX is implemented in deep n-well.VDD RX and VDD TX are the supply voltage with respect to GND RX and GND TX , respectively.The n-well and deep n-well potentials are connected to the supply voltage of the particular ground domain (i.e., VDD TX for GND TX -domain transistors and VDD RX for GND RX -domain transistors).With the GND TX domain introduced, additional couplings exist between GND TX and the electrode interface, BS ground, as well as GND RX .The coupling between the two ground mains (i.e., GND TX and GND RX ) could cause the inter-path signal flow, degrading the downlink/uplink performance when enabled concurrently.Thus, to minimize this coupling, the GND TX domain area in the layout is minimized.Thus, Along the data TX output path, only the driver stage is implemented in the GND TX domain, with the baseband data preparation performed in the GND RX domain.The post-layout simulation shows <0.4 pF coupling.It is worth noting that the potential difference between the GND TX and GND RX is below the nominal range (2.5 V for the thick-oxide devices used), which is attributed to: 1) the relationship between GND RX and GND TX potential through the common signal at uplink/downlink interface and their parasitic coupling and 2) the parasitic diode between p-substrate and deep n-well.
For output signal translation across the ground domains, a comparator operating in the GND TX domain with full input swing is implemented, which takes in the GND RX -domain signal and the GND RX as its inputs, and outputs GND TX or VDD TX .To avoid oscillation and to improve the setting time, the comparator is designed with asymmetrical input transistor pairs for an intentional constant offset, given that the input signal difference is either VDD or 0 (approximately) in this case.Such comparators are, thus, referred to as "unbalanced comparators" and are also used in the cross-ground-domain dc-dc converter control (to be elaborated later).The NMOS transistors are implemented in deep n-well which is connected to the supply in the respective ground domain.
Considering the parasitic coupling between the two ground domains (<0.4 pF), to further prevent the data output from backflowing into the power RX path, a band-stop LC filter is designed at the power RX input, which resonates near the data uplink frequency (1 MHz) to exhibit high impedance for the data output signal and low impedance for the input power recovery, as illustrated in Fig. 10.Moreover, to further suppress downlink signal leakage when the data TX is off, a tri-state buffer is introduced at the data TX output stage to exhibit high impedance when off.

B. Dual-Ground-Domain DC-DC Converter
To provide the regulated supply for circuits designed in both GND RX and GND TX domains while minimizing the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.coupling, the dual-ground-domain dc-dc converter is introduced, as illustrated in Fig. 11.The converter consists of two stages, outputting the regulated VDD RX and VDD TX , respectively.
The first-stage power conversion performs the dual-input boost conversion with the maximum power point tracking (MPPT) [2].The switched-mode power converter operates in the discontinuous conduction mode (DCM), where the inductor charging time T 1 is determined by the hill-climbing algorithm-based MPPT [31].The inductor discharging time T 2 is determined by zero-current switching (ZCS), where a direct comparison between V L_R and VDD RX is performed to determine the PHI2 duration.To reduce the static power consumption for higher conversion efficiency, the ZCS comparator is power gated depending on the T 1 completion and zero-current crossing detection.The maximum conversion frequency is dependent on the DCM time, which adapts to the input voltage level [2].
The second-stage conversion performs the cross-grounddomain voltage regulation, converting the regulated VDD RX to the regulated VDD TX (with respect to GND TX ) while maintaining the separation.Considering the indeterminate potentials between VDD RX and VDD TX in the switched-capacitor-based converter power stage, to ensure the complete GND RX -domain and GND TX -domain switch on/off, an intermediate stage (GND ITM ) is introduced.The GND ITM (VDD ITM ) connects to GND RX (VDD RX ) for charge transfer from VDD RX to the intermediate-stage capacitor.It connects to GND TX (VDD TX ) for charge transfer to VDD TX .Switches in different ground domains are controlled by signals that are translated to their corresponding domains, by the unbalanced comparators.
The normal-mode operation is illustrated in Fig. 12(a).When VDD TX falls below the reference voltage, PHI3 EN is Fig. 12.
Transient illustrations of (a) normal-mode operation and (b) cold-start operation.pulled down, which is then translated to PHI3 ITM and PHI3 RX , opening S P1 -S P2 and S N1 -S N2 , while closing S P3 and S N3 .The negative edge delay is introduced to ensure that PHI3 TX is pulled down last, to avoid flow-through current due to switch transition overlapping which would otherwise degrade the ground-domain isolation.When VDD TX increases above the reference voltage, PHI3 EN is pulled up, causing PHI3 TX to pull up and thus opening S P4 and S N4 .Upon signal translation to the GND ITM and GND RX domain, PHI3 ITM and PHI3 RX are then pulled up, opening S P3 and S N3 while closing S P1 -S P2 and S N1 -S N2 .
When VDD TX is below 0.8 V (the pre-defined cold-start threshold), the second-stage conversion enters the cold-start mode, where all second-stage power switches are closed.Therefore, during cold-start, the data TX should be disabled.In each ground domain (GND TX , GND ITM , and GND RX ), the startup detector [32] is introduced to monitor VDD, which outputs "0" if VDD is below 0.8 V and tracks VDD otherwise.As illustrated in Fig. 12(b), due to the conduction loss, VDD RX usually rises above the cold-start threshold first, followed   VDD ITM and then VDD TX .Despite that, CS_EN RX and CS_EN ITM are only pulled to VDD RX and VDD ITM , respectively, after CS_EN TX is pulled high when VDD TX rises above 0.8 V, in order to align the mode of operation across all three domains.

C. Passive Receiver-Based Command Data RX
The downlink power and data recovery structure is shown in Fig. 13, where the FSK command data receiver is passive receiver based to reduce the active power consumption.The parallel LC structure filters and boosts the input signal at each FSK frequency (1.2 µH and 12 pF for 40 MHz and 8.2 µH and 22 pF for 10 MHz in this design, implemented off-chip).The FSK frequencies and their separation are determined by the body-coupled path loss and the receiver's capability to distinguish, within its power budget.The three-stage rectifier down converts the two frequencies, which are then compared for baseband data extraction, as well as the clock and data recovery.Considering that the human body channel loss differs at different transmission frequencies, to overcome errors in decoding, external biases V B1 and V B2 are introduced to adjust the comparator offset to balance the sensitivity for the two frequencies.

VI. MEASUREMENT RESULTS
This section first shows the BS and SN circuit measurements and then presents the on-body system measurement results for uplink and downlink concurrency.

A. Circuit Performance Measurements
Fig. 14 shows the BS and SN chip micrographs, both of which are implemented in the 40-nm 1P8M CMOS process.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.At the BS, the adaptive SI-C performance is characterized by measuring the signal strength V AVG at the data RX front end, when the downlink high-voltage signal output is coupled to the data RX via the shared electrode.As shown in Fig. 15, the analog cancellation structure achieves the interference  suppression by around 20 dB.By adapting the replica signal loading capacitance for improved cancellation, the adaptive SI-C further improves the interference suppression to over 40 dB, enabling the concurrent data recovery.Considering the interferer signal at 40 MHz and the uplink RX signal at 1 MHz which could be separated in the frequency domain, the interference suppression achieved is sufficient to avoid saturation in the active low-pass filter (for further out-ofband interference suppression), which is then followed by an amplifier and OOK demodulation circuits for RX data recovery.Nonetheless, due to the limit in the interference suppression, the bit error rate (BER) with concurrent HV output could be degraded by ∼1-2 orders of magnitude, when the RX input voltage is low (e.g., <20 mV PP ), compared with the scenario when HV output is disabled.
Fig. 16 shows the measured power consumption of the BS, where the driver outputs an 8.4V PP signal (with no FSK modulated data), at frequencies ranging from 20 to 80 MHz.With the HV driver being the most power-hungry block at BS, the charge-replenishing technique proposed leads to the overall BS power reduction.As the driver frequency increases and thus consumes higher power, the percentage of power reduction increases, reaching 31% at 80 MHz.
At the SN, the dual-ground-domain dc-dc converter efficiency is shown in Fig. 17.The first-stage conversion efficiency is measured to be over 90% at the output power ranging from a few microwatts to over 100 µW and over 70% at the output power of over 500 nW.To ensure the ground domain separation while measuring the second-stage power conversion efficiency, VDD RX is battery powered and different resistors are soldered across the VDD TX and GND TX to adjust the output power.A USB-powered picoscope is

B. On-Body System Measurements
The on-body system measurement is shown in Fig. 18.It covers three measurement categories: 1) BS; 2) SN; and 3) system measurements.The BS and SN are placed/held separately on two sides of the body, where wet electrodes are used to couple the signal onto and from the body.We ensure that the measurement equipment does not share common ground.For system operation verification (simultaneous downlink power delivery and uplink data communication), measurements are performed at both BS and SN simultaneously, which mandates oscilloscopes on both sides.It should be noted, though, that having equipment attached at both BS and SN sides with wirings could cause additional coupling, which may lead to more optimistic results (i.e., less path loss).Therefore, to minimize the equipment-induced couplings when measuring the BS or SN performance only (e.g., BS: data recovery and SN: power recovery), equipment is only attached to the device under test, whereas the other device (not being measured directly) does not have external equipment attached.
At the BS, the received uplink signal strength is measured when the downlink HV signal is transmitted concurrently.As shown in Fig. 19, measured along the wrist-to-wrist path, by suppressing the leakage and HV interference, the proposed techniques achieve > −45 dBV received signal strength at the RX input, compared with no effective uplink data signal observed otherwise.The measured BER of the uplink data receiver is illustrated in Fig. 20, when the downlink HV output is enabled concurrently (i.e., self-interference: 8.4V PP ).As the RX input voltage increases, the influence of HV interference reduces.
At the SN, to measure the input power leakage suppression (through the low-impedance data TX output path), the uplink data TX is first disabled.As shown in Fig. 21, without the proposed techniques, power recovery is unachievable due to leakage.In contrast, by suppressing the current flow between the two paths, the ground-domain separation achieves around 700 µW at 15-cm on-body distance and 4 µW at 120 cm.This is further improved by the tri-state buffer, achieving around 1 mW at 15 cm and 15 µW at 120 cm.Fig. 22 shows the measurement results of the concurrent power recovery while transmitting the uplink data.The overall power recovery is the sum of the optimal GND RX domain power extracted and the GND TX domain power consumed by the data TX.Without the proposed techniques, power recovery is insignificant due to leakage and the disruption of rectifier operation caused by backflow.In contrast, the proposed ground-domain separation and band-stop LC techniques enable the power recovery of 165 µW at 30-cm apart and 12.5 µW at 120-cm apart.
The transient measurements of the concurrent powering and uplink data transmission at the BS and SN are illustrated in Fig. 23.The downlink power delivery from the BS powers the SN wirelessly and regulates the VDD TX , which then enables the uplink data TX.The data RX at the BS recovers such uplink data concurrently.
The performance comparison with the state-of-the-art body area powering and communication system is summarized in Table I.Overall, this work achieves the concurrent BCP and BCC (uplink and downlink) via a single electrode, which has not been achieved before.Compared with [16] that integrates the BCP and BCC in a TDM-based alternating manner with switches for path selection, this work achieves the BCP and BCC concurrency, which is essential for the sustained BAN powering without disruptions of the data connectivity.Compared with [23] and [24] that separate the power TX and uplink data RX into two devices with multiple electrodes for downlink-uplink concurrency at the BS, this work achieves the concurrency in an integrated device via a single electrode, at both BS and SN.Compared with inductive- [33] or RF-based [34] systems that are constrained to certain on-body paths (e.g., line-of-sight and alignment), this work uses the body-coupled approach for wireless powering and communication, achieving the full body area coverage.

VII. CONCLUSION
To conclude, this work proposed the BAN BS and SN ICs that could achieve the concurrent BCP, uplink, and downlink BCC via a single electrode.At the BS, this is enabled by the adaptive SI-C with the band-stop LC techniques, which overcome the HV signal saturation and leakage, enabling 100 kb/s concurrent uplink data recovery.At the SN, the uplink and downlink concurrency is enabled by the ground-domain separation, band-stop LC, and tri-state buffer techniques, which overcome the leakage and backflow, enabling 12.5-µW power recovery at 120 cm while transmitting the uplink data.

Fig. 2 .
Fig. 2. Conventional BCP and BCC integration.(a) BCP and BCC uplink/downlink alternated.(b) BCP and BCC uplink alternated.(c) BCP and BCC uplink alternated at SN, with continuous BCP and BCC at BS.

Fig. 3 .
Fig. 3. Proposed system achieving the BCP and BCC (uplink and downlink) concurrency via a single electrode at both BS and SN.

Fig. 4 .
Fig. 4. Challenges for BCP and BCC concurrency at BS and SN.

Fig. 9 .
The driver stage consists of stacked transistors.The 4V DD supply, intermediate voltage levels (3V DD , 2V DD ), and the 4V DD -to-3V DD control signal swing are all generated on-chip from a four-stage charge pump.During the pull-down stage, the three intermediate nodes (nodes 1-3) fast transition from 4V DD to 3V DD , 2V DD , and 1V DD , respectively (enabled by MN1-3 and MP1-3), where charges are transferred from the parasitic capacitors (formed with the chip ground, at nodes 1-3) to C CP1 -C CP3 .During the pull-up stage, charges stored (on C CP1 -C CP3 ) are then used to assist in biasing

Fig. 18 .
Fig.18.On-body system measurement setup for system operations.

Fig. 20 .
Fig.20.BS: measured BER against RX input voltage at different rates, when 8.4V PP TX output is enabled concurrently.

Fig. 22 .
Fig. 22. SN: measured recovered power when SN data TX is on.

TABLE I PERFORMANCE
COMPARISON WITH THE STATE-OF-THE-ART BODY AREA POWERING AND COMMUNICATION SYSTEMS used to observe the output voltage (regulated around 1 V).Up to 89.1% conversion efficiency is measured at 75 k , and over 70% efficiency is observed at the loading from around 5-500 k .