Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance

In this article, a scalable inter-core-shaping multi-core oscillator is proposed to achieve low phase noise and high figure of merit (FoM) at millimeter-wave (mm-wave) band. Adjacent NMOS and PMOS cores generate common-mode (CM) resonance simultaneously, but with opposite signs; thus, differential capacitors can be used to create resonance at twice the oscillation frequency. Such a CM resonance limits flicker noise upconversion and reduces phase noise. The capacitors in differential mode (DM) and CM are all differential, which avoids the degradation of quality factor caused by the single-end capacitor. Besides, the magnetic coupling among the cores only operates in DM. In CM, the negative and positive mutual couplings cancel each other, which increases the CM inductance and its quality factor. Moreover, the topology shows low sensitivity to the parasitics in the return path and the mismatch among the cores, which makes it suitable for the massive-core extension. The 28-GHz quad-core and 20-core circuits are prototyped in a conventional 40-nm CMOS process. Occupying a core area of 0.06 mm2, the quad-core oscillator achieves 1-MHz FoM of 193.3 dBc/Hz. The 20-core circuit exhibits 1-MHz phase noise of −120.8 dBc/Hz at 28 GHz and 1-MHz FoM of 192.7 dBc/Hz.


I. INTRODUCTION
R EDUCING the phase noise is a long-term goal of high-performance local oscillator (LO), especially at millimeter-wave (mm-wave) frequency.The high-order quadrature amplitude modulation (QAM) and high-resolution radar put increasingly stringent requirements on the spectral purity of mm-wave oscillators.In general, lower phase noise corresponds to higher power consumption and larger chip area of the LO circuit.The commonly used figure of merit (FoM) and figure-of-merit area (FoM A ) [1] can be used to characterize the efficiency of energy and area, respectively.Therefore, the LO circuit with low phase noise as well as high FoM and FoM A is a great challenge in mm-wave frequency, especially in the bulk CMOS process.
The common-mode (CM) shaping techniques [2], [3], [4], [5], [6] are widely used to reduce the phase noise, suppress the flicker noise upconversion, and obtain a high FoM.The second-harmonic tail-filtering technique [2] minimizes the noise upconversion under the cost of chip area to accommodate the extra tail inductor.To avoid the extra chip area, implicit CM oscillators [3], [4] are reported, where the implicit CM resonance is excited by properly selecting the mutual coupling of the differential inductor and the ratio of single-ended and differential capacitance, as shown in Fig. 1.However, the inductor's quality factor in CM is reduced by the typically magnetic flux cancellation, which limits the achievable phase noise and FoM.Moreover, the quality factor of a single-ended switchable capacitor is inherently lower than the differential type once achieving the same tuning range.Since the single-ended capacitor works in both differential mode (DM) and CM, the performance is further limited.To circumvent these issues, the inverse-class-F oscillator [7] is reported to generate both first-and second-harmonic resonances in DM using a transformer-based two-port resonator.Nevertheless, such a resonator is not easy to realize in mm-wave frequency.At mm-wave band, the oscillator using single-turn multitap inductor [8] achieves an FoM higher than 191 dBc/Hz by utilizing multiple resonances and positive CM coupling.However, the single-ended capacitor and opposite polarity of magnetic coupling in DM and CM still limit the performance.To meet the low phase noise requirement in mm-wave frequency, the frequency multiplying scheme [9], [10], [11], [12], [13], [14] is a classic approach, since it is easier to obtain higher quality factor and better harmonic shaping effect for a low-frequency oscillator.However, low-frequency oscillator has large chip area, and the multiplying stage inevitably costs extra power consumption and area.Another method to obtain low phase noise is multi-core oscillator [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29].According to Lesson's phase noise equation [30], it is possible for an N -core oscillator to burn N times higher power and decrease the phase noise by 10 log(N ).Differing from conventional parallel connected multi-core oscillators based on extra coupling circuit, the circular-type multi-core oscillators [25], [26], [27], [28], [29] are attractive for high area efficiency.Compared with mm-wave single-core oscillators [31], [32], whose inductors may suffer the destructive coupling between traces, the larger diameter of the circular-type oscillator helps to obtain a higher quality factor.However, once the core number is increased, complex supply and decoupling networks are required [29].The unavoidable parasitics in supply and ground paths have adverse impact on the performance.Moreover, due to the limitation of layout plan, it is not easy to introduce the harmonic shaping operation in the circular-type oscillator.Thus, the FoM of mm-wave multi-core oscillator achieving 190 dBc/Hz or above remains a great challenge.
To mitigate the aforementioned issues of CM shaping and multi-core oscillators, this article proposes a scalable intercore-shaping multi-core oscillator, which aims to achieve low phase noise, high FoM, and high FoM A at mm-wave frequency.As shown in Fig. 2, the PMOS and NMOS pairs are utilized in the topology.The capacitors for DM and CM are all differential, which avoids the quality factor degradation due to the single-ended capacitor.The circular-type connection improves the quality factor of inductor.The destructive coupling in CM is canceled.Therefore, a larger coupling between the cores can be used to increase the passive quality factor without damping the quality factor in CM.Moreover, the proposed topology shows low sensitivity to parasitics in the supply path and mismatch among the cores, which has the advantage for the massive-core extension.
This article extends the work in [33] by providing an in-depth analysis of the inter-core-shaping multi-core topology.The DM and CM multi-core operation and configuration of the coupling are investigated.The CM return path is modeled to analyze the stability of CM resonance.The detailed circuit implementation and considerations of massive-core extension are offered.In Section II, the operation and characteristics of inter-core-shaping multi-core topology are analyzed.Section III focuses on the circuit and layout design of quad-core and massive-core oscillators.The influence of parasitics and mismatch between cores are also discussed in this section.Section IV reports the measurement results of the proof-of-concept quad-core and 20-core oscillators.Finally, a conclusion is drawn in Section V.

II. INTER-CORE-SHAPING MULTI-CORE OSCILLATOR
The CM signals at the two ports of the differential oscillator are the same.Therefore, in general, the single-ended capacitor is demanded to tune the CM resonance.The inherently low-quality factor of single ended limits the achievable performance of the conventional design.To circumvent this issue, our approach is to construct a differential relationship of the CM signals in different cores.Then, the differential capacitor can be used to excite the CM resonance between the cores, which achieves an improved effect of CM shaping in multicore oscillator.Therefore, the proposed method is called a inter-core-shaping technique.

A. Inter-Core-Shaping Operation
The operations of PMOS and NMOS CM shaping oscillators are illustrated in Fig. 3.The current and voltage of the two topologies are complementary.It has no impact on the DM signals but leads to different directions of CM response.Assuming that the CM current of the PMOS circuit flows from the active pair into the resonator, the NMOS's CM current flows from the resonator into the active pair.Therefore, once the CM response of the resonator at the second harmonic is resistive, the out-of-phase CM waveforms of NMOS and PMOS cores can be formed.The CM voltage waveforms of PMOS and NMOS cores are expressed as follows: where V CM is the amplitude of CM signal.Then, once reconnecting the single-ended capacitors and inductors between the alternately placed PMOS and NMOS cores, the DM and CM signals flowing in them are all differential.Thus, the single-ended capacitor can be replaced by differential type, while the connections to the power supply and ground in center taps are removed.The capacitor C D is kept in each core, since it is only seen in DM.Considering that the DM and CM signals in the reconnected inductors are all differential, the mutual coupling of the differential inductor leads to the same equivalent inductance in DM and CM.Therefore, the distributed coupling between two inductor chains is introduced Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.to obtain different equivalent inductances in DM and CM.Interestingly, this new type of coupling scheme nulls the destructive CM coupling while keeping the constructive DM coupling.In Section II-B, this phenomenon is discussed in detail.To prevent the potential mode ambiguity and latching up, metal resistors are used to connect the taps.The possible unwanted modes are damped due to the limited quality factor, as analyzed in [26].
The multi-core DM and CM operations are shown in Fig. 4. In order to highlight the multi-core resonant path, the active pairs are simplified, while resistors are omitted.In the DM shown in Fig. 4(a), the adjacent cores share the LC tank.Both C D and C C have differential waveforms on the two ends.The equivalent capacitance seen from each core is C D + C C .The currents flowing in the two inductor chains are in the same direction.Then, the equivalent inductance in DM is (1 + k)L.Therefore, the equivalent quality factor in DM is ω(1 + k)L/R s , where R s is the series resistance in the inductor.The resonant frequency in this mode is The multi-core CM operation is more noteworthy, as shown in Fig. 4(b).Each active pair has the same waveform on the two nodes, while the CM voltages of NMOS and PMOS pairs are out of phase.Then, L and C C can still form a differential tank between adjacent cores and, thus, excite the inter-core CM operation.Moreover, due to the opposite CM currents of NMOS and PMOS cores, the current directions in the inductors are alternately inverted.According to the distributed coupling scheme, each inductor couples one in-phase inductor and one anti-phase inductor.The positive and negative couplings cancel each other out.The equivalent magnetic coupling in CM is zero.Thus, the equivalent inductance in CM is L, while the equivalent quality factor is ωL/R s .Then, the resonant frequency in CM is Differing from the implicit CM technique, the equivalent coupling in CM is nulled in this topology.The ratio of equivalent quality factor , which leads to enhanced second-harmonic shaping effect, especially at mm-wave frequency.

B. Canceled CM Destructive Coupling
In order to dissect the influence of the canceled CM coupling, Fig. 5(a) lists the DM and CM parameters of the implicit CM oscillator and the proposed inter-core-shaping oscillator.Due to the change of magnetic coupling in CM, the parameters need to be adjusted to keep DM and CM resonances at the desired frequencies.To make the comparison intuitive, the DM and CM resonances of the implicit CM oscillator (i.e., dotted lines) and inter-core-shaping oscillator (i.e., solid lines) are plotted in Fig. 5(b).There are three steps from the implicit CM type to the proposed circuit. 1) Step 1: The magnetic coupling in CM is canceled.The DM response is not changed, while the CM resonance gets a higher quality factor but moves to a lower frequency.

2)
Step 2: Smaller inductance is chosen to increase both the DM and CM resonances.The CM resonance is tuned to the desired frequency, while the DM frequency is moved higher.

3)
Step 3: The coupling factor k is increased.The DM resonance moves back to the correct frequency without influencing the CM response.Then, the DM resonance achieves a higher quality factor due to the higher k.Therefore, the equivalent quality factors in both DM and CM are increased in the proposed inter-core-shaping oscillator.

C. Stability of CM Resonance
The supply and ground for RF circuits are not so straightforward, especially at mm-wave band.Once considering the connections in layout, the current return path is much more complex than schematic.The parasitics for connections to supply and ground often lead to unexpected effects on the circuit.Once the CM resonance is used in oscillator design, the CM return path gets more and more attention [4], [5], which carries the CM current from the drain to the source of the transistor and then back around.For the implicit CM circuit, the CM return path includes two parallel paths, as shown in Fig. 6(a).The first path includes the CM equivalent inductor Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.L CM , parasitic inductors for connections to the supply and ground (i.e., L tap and L tail ), and decoupling network, while the other consists of the CM capacitor C C and parasitic capacitance C p of transistor.Note that in order to simplify the analysis, the inductance in decoupling network is merged to L tap and L tail .Assuming the decoupling capacitor is large enough to short the supply and ground for ac signal, the CM resonator is formed by capacitance C C + C p paralleled with inductance L CM + 2L p , as shown in Fig. 7(a).Here, L p is the whole parasitic inductance in supply and ground paths (i.e., L p = L tap + L tail ).The CM frequency of implicit CM circuit considering the parasitics is Since the resonant path is totally open for the supply and ground, two times of L p are added to the CM inductance directly.Thus, the CM resonance is sensitive to the layout plan for supply and ground.In [5], the CM return path is carefully modeled to control the CM resonance of mm-wave oscillator.However, for multi-core oscillators, the supply and ground are much more complex.It is not feasible to maintain the consistency of the CM return paths among the cores.Fortunately, the inter-core CM operation of the proposed topology can alleviate this issue.The differential CM operation between NMOS and PMOS makes the main CM resonant path (i.e., L CM and C C ) closed to the supply and ground paths, as shown in Fig. 6(b).Considering the circuit is complementary, two half circuits can be obtained by connecting the center of the main CM path and the center of the return path.The half circuit for the differential CM path is shown in Fig. 7(b), where the parasitic inductance is half of the equivalent inductance in  the return path (i.e., L p ).Moreover, L p is connected to the main CM LC tank rather than the CM inductor.Then, the CM path becomes a two-order resonator.In practical circuits, the parasitics (i.e., L p and C p ) is smaller than the main parameters (i.e., L CM and C C ).Therefore, the first resonance is the critical element in this work.The CM frequency is calculated as (6), shown at the bottom of the page.
Fig. 8 plots the calculated deviation of CM frequency, when L p ranges from 0 to half of L CM .For the implicit CM circuit, L p /L CM = 0.5 corresponds to a huge frequency deviation of about 30%.Even if L p /L CM = 0.1, the frequency derivation of 8.8% is still large for CM shaping operation.For the proposed circuit, the CM frequency deviation is significantly reduced.Once C p is half of C C , the frequency deviation for L p /L CM = 0.1 is reduced to 0.5%.Moreover, smaller C p /C C leads to a smaller frequency deviation.Even if L p is half of L CM , the CM frequency deviation is only 0.2%, when C p is one-tenth of C C .To visually show the stability of CM resonance, Fig. 9 depicts the simulated CM response of implicit CM and proposed circuits.L CM is set as 80 pH with a quality factor of 20 at ω CM .C p /C C is chosen as 1/5.For the implicit CM circuit shown in Fig. 9(a) and (b), the CM resonance moves away from 2 f 0 quickly, once increasing L p .Meanwhile, the phase response at 2 f 0 is sensitive to the value of L p .Once the CM phase response at 2 f 0 is away from 0 • , the nonsymmetric waveform leads to the aggravated flicker noise upconversion.The CM impedance and phase response of the proposed oscillator are shown in Fig. 9(c) and (d).With the increasing of L p , the CM resonance only has little change, while the phase response at 2 f 0 stays around 0 • .Therefore, the operation of the second-harmonic shaping is much more robust.More importantly, the proposed topology exhibits the ability to support the second-harmonic shaping in multi-core oscillator without worrying about the consistency of each core's CM return path.

III. CIRCUIT DESIGN AND CONSIDERATION
To verify the proposed proof of concept, a quad-core oscillator is implemented first.Then, the design consideration for massive-core extension is discussed, and a 20-core oscillator is designed as a prototype.
A. Quad-Core Oscillator Fig. 10 shows the circuit implementation of the quad-core scheme based on the proposed topology.The inductors are distributedly coupled and placed as a circular geometry.The large diameter of the whole quad-core passive can mitigate the destructive coupling between the traces, especially in the case of small inductance at mm-wave frequency, thus enhancing the inductor's quality factor.The inner diameter of the quad-inductor passive is 135 µm.The space between the traces determines the coupling factor k. Based on the circuit analysis, a higher k benefits the equivalent quality Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.factor in DM.However, if the coupling is too high, the parasitic capacitance and skin effect limit the quality factor of inductor.The optimized inductance and coupling factor are about 100 pH and 0.41, respectively.The inductance, quality factor, and equivalent values in DM and CM are obtained by the electro-magnetic (EM) simulator EMX, as shown in Fig.  [34], [35].Therefore, the capacitors can be placed under the top thick metal directly.The electric field is enclosed in the shielding structure of the capacitor, which prevents substrate loss and the deviation caused by unexpected coupling.The terminals on the bottom metal are used to connect the switch.The simulated quality factor of a 5-fF 3-D capacitor cell is 210 at 28 GHz, as shown in Fig. 12.Each varactor has a size of 3 × 1.4/0.5 µm with quality factor from 10 to 32 at 28 GHz.A clearance of 25 µm is left between the inner devices (i.e., transistors and capacitor banks) and the inductors to minimize the undesired coupling and the impact on the quality factor.The center taps of each inductor are connected by the high-resistance metal line in order to avoid mode ambiguity and latching up.Realized by 0.24-µm M4 and M5 overlapping together, each metal line from the center tap to the intersection has a resistance about 30 .Considering the performance is not sensitive to the parasitics in the return path, the supply and ground are directly connected to the outside of the multi-core passive using thick metal.The decoupling network is placed outside the multicore circuit.In order to extract the DM and CM resonance in post-simulation, Fig. 13 depicts the quad-core resonator in DM and CM.Since the unwanted mode is suppressed by the high-resistance metal line, the DM is obtained as the four ports exciting in the same phase.Then, one-fourth of the DM impedance Z DM can be simulated according to the test bench, as shown in Fig. 13(a).When the DM of the four cores is synchronized, the CM resonance is excited from the differential operation across NMOS and PMOS.Therefore, by connecting the nodes of PMOS and NMOS, respectively, half of the differential CM impedance Z CM can be obtained, as shown in Fig. 13

B. Strategy of Massive-Core Extension
The parallel-type [23] and mesh-type [29] topologies are usually used to achieve many-core oscillators.However, the   mismatch between cores and complex decoupling network may limit the performance, increasing the complexity of design.Since the proposed topology is insensitive to the parasitics in return path, it has the potential to achieve high-performance massive-core oscillator.The strategy for massive-core extension is to adopt the array of quad-core 15.
Simulated voltage waveforms of (a) NMOS and (b) PMOS transistors.ISF and ISF eff of (c) NMOS and (d) PMOS transistors.
units.Considering the quad-core circuit as a unit, the units can be diagonally connected together to form the 4X -core array (i.e., X = 1, 2, 3, . ..).Then, the key challenge is to connect the quad-core unit without extra circuit.Fig. 16(a) shows the connection method in two diagonal directions.The inductors in the two quad-core rings are reconnected.The inductors connecting two units (i.e., L 1 ) and the inductors in each unit (i.e., L 2 ) are designed to keep the similar inductance and quality factor, as shown in Fig. 16(b).Note that the adjacent quad-core units have the opposite directions of NMOS and PMOS pairs, which ensures each inductor connects one NMOS pair and one PMOS pair.Based on this strategy, the 20-core oscillator is designed, as shown in Fig. 16.Compared with the quad-core circuit, the 20-core oscillator achieves an  improvement of phase noise about 6.8 dB in post-simulation with five times power consumption, which is only 0.2 dB lower than the theoretical value (i.e., 10log5) in the ideal situation.

C. Mismatch and Robustness Analysis
The mismatch between the cores is taken into consideration during the design.Although the inductances in each core are kept as consistent as possible, the EM environments for the inner and outer passive structures are inevitably different.In Fig. 17, the inner and outer inductors are marked green and blue, respectively.Fig. 18 shows the simulated phase noise with the mismatch between the two kinds of inductors increasing from 0% to 10%.Note that the two inductances are changed in opposite directions to minimize the impact of frequency variation.The variation of frequency is smaller than 0.5% under a 10% mismatch of passive.With a 10% mismatch, the simulated amplitude mismatch of fundamental signal and the second harmonic among the 20 cores are 16% and 22%, respectively.The largest phase variation of the fundamental signal among the cores is 4.4 • , while the phase difference of CM voltage between NMOS and PMOS cores varies from 167 • to 196 • .Under such mismatches of amplitude and phase, the deteriorations of phase noise at 100-kHz and 1-MHz offset are 1.2 and 0.4 dB, respectively.
Meanwhile, the impact of the transistors' mismatch is discussed.With a 10% mismatch between the transistors in inner and outer cores, the deteriorations of phase noise are 0.2 and 0.1 dB at 10-and 100-kHz offsets, respectively.At higher offset, the deterioration of phase noise is smaller than 0.1 dB.To investigate the robustness of the performance under different corners, Fig. 19 shows the simulated phase noise of the quad-core and 20-core oscillators, respectively.Both the phase noise in the thermal noise region and the flicker noise corner vary slightly, when the process corner is switched from SS to TT.The results of the Monte Carlo simulation of the quad-core and 20-core oscillators are shown in Fig. 20.After sampling 1000 points, the standard deviations of the 1-MHz phase noise for the two oscillators are 0.14 and 0.25 dBc/Hz, respectively.For both oscillators, the frequencies of most samples vary within 30 MHz.Besides, the influence of the return path is verified.The parasitic inductors in the supply and ground paths are intentionally added during the simulation.When the parasitic inductances for each core increase from 0 to 50 pH, the influence on the 1-MHz phase noise is smaller than 0.5 dB.Therefore, the proposed topology  exhibits low sensitivity to the mismatch among the cores and parasitics in the return path.

IV. MEASUREMENT RESULTS
The proposed quad-core and 20-core multi-mode oscillators are fabricated in a conventional 40-nm CMOS technology.Fig. 21 shows the micrographs of the prototypes.The two      20-core oscillator is only about 0.5 dB lower than the quadcore oscillator.Fig. 25 depicts the measured 1-MHz phase noise for all the capacitor settings.Once the CM resonance is misaligned, the largest variations of 1-MHz phase noise of quad-core and 20-core oscillators are 2.3 and 2.6 dB, respectively.The supply pushing of the quad-core and 20-core oscillators is −90 to −285 and −105 to −290 MHz/V, respectively, as shown in Fig. 26.
The measured results are summarized and compared with the state of the arts in Table I.The quad-core oscillator has state-of-the-art FoM and FoM A mm-wave band, which means good energy and area efficiency, respectively.The flicker noise corner is kept low for a multi-core oscillator.The 20-core oscillator shows the lowest equivalent phase noise at mm wave.It also exhibits good FoM and flicker noise corner.Figs.27 and 28 summarize and benchmark with prior arts operating at several tens of GHz.It is notable that the quad-core oscillator achieves state-of-the-art FoM at mmwave.The FoM A of quad-core circuit is higher than single-core oscillator.Meanwhile, the 20-core oscillator achieves state-ofthe-art FoM and absolute phase noise.

V. CONCLUSION
In this article, a scalable mm-wave inter-core-shaping multicore topology is proposed.All differential capacitors in DM and CM ensure high-quality factor of the capacitor bank.The circular connection increases the quality factor of inductor.The canceled CM destructive coupling increases the quality factor in both DM and CM and enhances the second shaping.Moreover, the topology shows low sensitivity of parasitics in the return path and the mismatch between cores.Thus, it is feasible for the massive-core extension.Prototyped in a conventional 40-nm CMOS, the quad-core oscillator achieves state-of-the-art FoM and FoM A , which demonstrates good efficiency of energy and chip area, simultaneously.To verify the capability of massive-core extension, the 20-core oscillator exhibits state-of-the-art phase noise at mm-wave band without sacrificing FoM.

APPENDIX
In order to clarify how the passive structure is mapped in the layout design, the implementation roadmap from the circuit model to the layout plan is shown in Fig. 29.

Fig. 1 .
Fig. 1.Diagram and operation of the implicit CM oscillator.

Fig. 3 .
Fig. 3. Evolution from the PMOS and NMOS implicit CM oscillators to the inter-core-shaping multi-core oscillator.

Fig. 4 .
Fig. 4. Current and waveform of the inter-core-shaping multi-core oscillator in (a) DM and (b) CM.

Fig. 5 .
Fig. 5. (a) Parameters and (b) impedances of the three steps from implicit CM oscillator to the proposed oscillator.

Fig. 7 .
Fig. 7. (a) CM tank of implicit CM oscillator.(b) Half circuit of the proposed oscillator's CM tank.

Fig. 8 .
Fig. 8. Calculated deviation of CM frequency for L p from 0 to half of L CM .

Fig. 9 .
Fig. 9. Simulated (a) CM impedance and (b) CM phase of implicit CM oscillator.Simulated (c) CM impedance and (d) CM phase of the proposed oscillator (L CM = 80 pH, C C = 85 fF, and C p = 17 fF).
(b).The switch capacitors of C D and C C are switched in one at a time to ensure ω CM = 2ω DM with the tuning of frequency.The simulated DM and CM resonances based on EM simulation of the passive connection and the switchable capacitor array are shown in Fig. 14.The loaded quality factor of the resonator is calculated as 20.3 at f max and 22.6 at f min .The simulated voltage waveforms of NMOS and PMOS transistors with the corresponding impulse sensitivity function (ISF) and effective ISF eff are shown in Fig. 15, respectively.Both the waveforms of NMOS and PMOS are shaped by the second harmonic.The flat regions of the drain node voltages lead to a near-zero value of the ISF, thus suppressing the thermal noise to pn upconversion.Besides, the dc value of effective ISF is minimized to suppress the flicker noise upconversion.

Fig. 13 .
Fig. 13.Test bench to simulate (a) DM and (b) CM impedance based on quad-core passive circuit.

Fig. 16 .
Fig. 16.(a) Connection methods of two quad-core units in two diagonal directions.(b) Simulated inductance and quality factor of two kinds of inductors.

Fig. 18 .
Fig. 18.Simulated phase noise with different mismatches between outer and inner inductors.

Fig. 26 .
Fig. 26.Measured supply pushing of (a) quad-core and (b) 20-core oscillators.respectively.Fig. 23 concludes the measured phase noise performance.The phase noise of quad-core oscillator is −113.1 to −115.6 and −133.8 to −136.4 dBc/Hz at 1-and 10-MHz offsets, respectively.For the 20-core oscillator, the phase noise ranges from −119.6 to −121.7 and −140.5 to −142.8 dBc/Hz at 1-and 10-MHz offset, respectively.As shown in Fig. 24, the best FoM of quad-core oscillator at 1-and 10-MHz offset is 193.3 and 194.0 dBc/Hz, respectively.The 20-core circuit exhibits the FoM of 192.7 and 193.4 dBc/Hz at 1-and 10-MHz offset.It is notable that due to the low sensitivity on the mismatch and return path, the FoM of

Fig. 29 .
Fig. 29.Implementation roadmap from the circuit model to the layout.
11.Each core has the capacitor bank C D , which is realized by four pairs of differential switch capacitors, one pair of varactors, and a fixed capacitor C D−FIX .The CM capacitor C C connecting the opposite PMOS and NMOS cores is formed by four differential switched capacitors and one differential fixed capacitor C C−FIX .Here, C D−FIX and C C−FIX are 60 and 20 fF, respectively.For the switchable capacitor in C D , C ON /C OFF of each cell is 12.5/3.8fF, while the size of switch is 12.5 µm/40 nm with R ON about 29 .For the switchable capacitor in C C , C ON /C OFF of each cell is 7.5/2.6fF, while the size of switch is 7.8 µm/40 nm with R ON about 47 .The capacitor in this design is 3-D shielded horizontal capacitor, which has the characteristic of self-shielding and intrinsic high quality factor

TABLE I PERFORMANCE
SUMMARY AND COMPARISON WITH STATE-OF-THE-ARTS