A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From40 °C to 85 °C After Accelerated Aging for 500 h at 125 °C

This article presents a temperature- and aging-compensated <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math></inline-formula> oscillator (TACO) in which the long-term drift of the main oscillator is compensated by periodically locking its frequency to that of the less-aged reference oscillator. To improve the long-term stability of the TACO, it employs techniques, such as the use of higher activation energy (<inline-formula> <tex-math notation="LaTeX">$E_{a}$ </tex-math></inline-formula>) resistors, switched dual <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math></inline-formula> branches to mitigate stress from dc-current-induced electromigration (EM), and duty cycling to slow down the aging rate of the reference oscillator. Using the proposed techniques, a prototype 100-MHz <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math></inline-formula> oscillator fabricated in a 65-nm CMOS process achieves an inaccuracy of ±1030 ppm from –40 ° C to 85 ° C after 500 h of accelerated aging at 125 ° C, with 5.1-<inline-formula> <tex-math notation="LaTeX">$\rm ps_{\mathrm{ rms}}$ </tex-math></inline-formula> period jitter and a power efficiency of 1.4 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula>/MHz.

Color versions of one or more figures in this article are available at https://doi.org/10.1109/JSSC.2023.3320709.
oscillators [22].Despite their exceptional performance, the lack of information on the aging behavior of RC oscillators and their inability to guarantee long-term performance limit their commercial deployment.
Resistor aging is the primary contributor to long-term frequency drift in RC oscillators, and p-poly resistors, commonly used as reference resistors in RC oscillators for their high sheet resistance, small area, and relatively low-temperature coefficient of resistance (TCR), are particularly prone to aging [25], [26].Accelerated aging tests on standalone p-poly resistors have shown that their resistivity can change by over 0.5% after 1000 h at 150 • C [27].To evaluate the effect of resistor aging on the oscillator's frequency, a temperature-compensated frequency-locked loop (FLL)-based RC oscillator prototype using a p-poly resistor was designed, and its long-term stability was measured by baking it at 125 • C. The results, plotted in Fig. 1, show that resistor aging significantly affects the oscillator's frequency, causing more than 5000-ppm drift after 1000 h [23].In addition, a 5000-ppm frequency drift of RC oscillators using a p-poly resistor was observed from an aging experiment at 150 • C for one week [24].To address this issue, this article presents circuit techniques to enhance the long-term stability of RC oscillators and compensate for frequency drift caused by aging Fig. 2.
Proposed aging compensation scheme and FLL-based TCO architecture.
without the need for external stable sources.A 100-MHz FLL-based RC oscillator prototype is fabricated in a 65-nm CMOS process, and it achieves an inaccuracy of ±1030 ppm from −40 • C to 85 • C after 500 h of accelerated aging at 125 • C, with 5.1-ps rms period jitter and a power efficiency of 1.4 µW/MHz.
The rest of this article is organized as follows.Section II presents the proposed architecture.Circuit implementation details of key building blocks are described in Section III.Experimental results from the test chips are shown in Section IV.Key contributions of this article are summarized in Section V.

II. PROPOSED ARCHITECTURE
A simplified block diagram of the proposed temperatureand aging-compensated RC oscillator (TACO) is shown in Fig. 2. The TACO consists of a main temperature-compensated oscillator (TCO), a reference TCO, and an aging compensation logic.The TCO operates continuously, while its long-term frequency drift due to aging is addressed by periodically synchronizing it with the less-aged reference oscillator.The main as well as the reference TCO both adopt an identical FLL-based architecture, which leverages two reference resistors (R 0 and R 1 ), as depicted in Fig. 2. The reference oscillator, however, is heavily duty cycled to prevent it from aging.

A. Techniques for Long-Term Stability Improvement
The TACO system uses various techniques to enhance its long-term stability.One such technique involves using reference resistors with higher activation energy (E a ) to increase their lifetime.Various resistors are available in standard CMOS technology, including poly, diffusion, and metal resistors, each governed by distinct aging mechanisms.The primary factor responsible for the shift in poly resistance is the depassivation of hydrogen at grain boundaries, coupled with hydrogen migration within an electric field [26], [27], [28], [29], [30], [31].On the other hand, the alteration in metal resistance predominantly stems from electromigration (EM), a phenomenon that propels the migration of metal atoms and consequently leads to the formation of voids within the resistor's structure [31], [32], [33].Despite the divergence in their aging mechanisms, these resistors' anticipated time to failure (TTF) can be empirically modeled as follows: where A is an empirically determined constant, J is current density (A/cm 2 ), n is the empirically determined current density factor, E a is the activation energy (eV), k is Boltzmann's constant, and T is the absolute junction temperature of the resistor during the aging stress.The TTF estimation can be achieved through Black's approach, as demonstrated by (1) [29], [31], [32], [33], or by employing an alternate model, as depicted in (2) [26], [29], [31] to accommodate low current density (J ) scenarios.E a represents a vital aging-associated parameter obtained by fitting aging experimental data with (1) or (2).Its value is influenced by the fabrication technique employed and the predominant aging mechanism of resistors.These equations illustrate that a resistor's TTF experiences exponential growth as E a becomes larger.The p-poly resistors have a low E a of 0.477 eV and suffer from higher degradation caused by aging stress [26], [27].Compared with p-poly resistors, n-poly resistors have a higher E a of 0.68 eV and longer TTF, making them more suitable for the better long-term stability of the oscillators [26].Metal interconnect or back-end-of-line (BEOL)-type resistors also have higher E a and exhibit smaller resistivity shifts under electrical and temperature stress than poly resistors [31], [34].For instance, the copper interconnects and VIA chains are characterized by E a values spanning from 0.82 to 0.93 eV [34].
Another technique is to design the reference resistors to have the current direction alternate periodically to reduce the stress caused by electromigration induced by the dc current.The TTF of poly resistors increases monotonically with the frequency of ac current stress [35].Electron wind induces the oscillation of dopant atoms by subjecting poly resistors to ac current stress.However, this oscillation does not result in the net movement of the dopant until it is trapped at a defect.The higher the frequency of the stress, the shorter the distance the dopant will travel, which reduces the probability of the dopant encountering a defect in the polysilicon, resulting in an improved TTF of the resistor [35].Metal-type resistors also show better TTF with ac current stress than dc stress [33].The circuit implementation for alternating current through reference resistors is described in detail in Section II-B.
The third technique involves using duty cycling to slow down the aging rate of the reference oscillator used to calibrate the main oscillator.The aging rate of poly and metal resistors in a standard CMOS process depends on the duty cycle.Lower duty cycles lead to slower aging rates of the resistors [30], [33].By reducing the on-time of the reference oscillator, the amount of time that a current flows through the active devices and interconnects decreases, which also can slow down the rate of specific aging mechanisms, such as hot carrier injection (HCI) and EM.

B. Detailed TCO Architecture
The TCO comprises two RC branches (R 0 C 0 and R 1 C 1 ), a G M − C integrator, a voltage-controlled ring oscillator (VCRO), a divider, differential voltage digital-to-analog converters (VDACs), a phase generator, and a modulator (DSM), as shown in Fig. 3.The VCRO clock is divided by N (=25) and fed to the phase generator, which generates clocks, CHG , RST , BUF , and INT .These clock phases are used to control the switching sequence in the RC branch, such that the difference between the track-and-held voltage V RC generated from the RC branch and V REF provided by VDAC represents the error between the desired frequency and VCRO (F OUT ) frequency.The error voltage, V ERR (=V RC − V REF ), is integrated by the integrator and used to drive the VCRO toward the frequency lock.To perform temperature compensation, the DSM generates mux select signal SEL, which enables either Path 0 consisting of R 0 C 0 branch and VDAC 0 when SEL = 0 or Path 1 consisting of R 1 C 1 branch and VDAC 1 when SEL = 1, as described later.The TCO operates in four phases, as illustrated in the timing waveforms in Fig. 3.The first phase commences with SEL = 0 and CHG = 0, during which the inverter of Path 0 resets C 0 to V DD when RST = 1 (reset phase).In the second phase, when BUF = 1, the buffer of Path 0 is activated and discharges C 0 via R 0 for T P duration to V RC0,DCHG = exp(−T P /R 0 C 0 )V DD , where greater than the target output frequency, and vice versa.The third phase occurs when RST , BUF , and INT are all zero, providing sufficient time for the redistribution of the charge stored in the parasitic capacitor of the resistor and for V RC to stabilize.In the final phase, INT = 1, and the integrator is enabled (integration phase); V ERR (= V RC0,DCHG − α 0 V DD ) is integrated for T P duration, generating the control voltage V C of the VCRO.In the subsequent cycle with CHG = 1, C 0 is reset to V SS and charged for a duration of T P , resulting in V RC0,CHG = (1 − exp(−T P /R 0 C 0 ))V DD , and then, V ERR (= V RC0,CHG − (1 − α 0 )V DD ) is integrated for T P duration.At CHG , the R 0 C 0 branch is chopped, and the first-stage output of the integrator is dechopped via the DECHOP signal.By reversing the current flow direction in resistor R 0 during periodic discharge and charge operations, the EM-induced stress is significantly minimized, and long-term stability is enhanced compared with unidirectional current flow.Furthermore, the discharge and charge operation occurs with an inherent duty cycle of 20% only when BUF = 1, which can decrease the aging rate of the resistor.
Assuming that SEL = 0 and Path 0 is selected, the output frequency, F OUT0 , of the TCO circuit is given by In the steady state with SEL = 0, V RC0,DCHG and V RC0,CHG are equal to α 0 V DD and (1−α 0 )V DD , respectively, due to feedback loop operation.Neglecting the TC and aging of C 0 and α 0 , the output frequency TC is determined by the TC and aging properties of R 0 alone.To compensate for the TC of R 0 , Path 1 , consisting of an R 1 C 1 branch and a VDAC 1 , is added.In the steady state with SEL = 1 and Path 1 selected, the TCO output frequency, F OUT1 , can be expressed as follows: Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
where the R 1 C 1 branch is designed to have the same time constant but exhibit a different TC from that of R 0 C 0 branch.The first-order temperature compensation is achieved by modulating the SEL signal with the first-order DSM.If R 0 C 0 and R 1 C 1 have opposite-sign TCs, the averaged V ERR is forced to zero in the steady state due to the high loop gain of the FLL and can be expressed as follows: where V ERR0 and V ERR1 represent the error between the TCO output frequency and F OUT0 and F OUT1 , respectively, and β is the average of the pulse-density-modulated SEL sequence.This equation can be rewritten as follows: assuming that R 0 C 0 and R 1 C 1 have similar time constants.
There exists an optimum β (β OPT ) at which F OUT is insensitive to temperature changes to the first order.However, if both R 0 C 0 and R 1 C 1 have positive TCs, the temperature dependency of F OUT cannot be compensated for by varying the average SEL sequence.To overcome this issue, the RC1_SIGN is added to the DECHOP signal logic, and by setting RC1_SIGN to one, the sign of integrator G M is reversed when SEL = 1, producing a negative sign in the second term of the averaged V ERR equation [see (5)], given by This equation can also be expressed as follows: Inverting the sign of integrator G M when SEL = 1 facilitates the implementation of first-order TC compensation through the utilization of distinct positive TC R 0 C 0 and R 1 C 1 branches.This action, however, introduces instantaneous positive feedback into the FLL loop, ultimately reducing its effective loop gain during the steady state.In Section IV, both simulation and measurement results revealed that for optimal first-order TC compensation, an optimal value of β (denoted as β OPT ) is approximately 0.02.This outcome is attributed to the substantial TC ratio between R 1 C 1 and R 0 C 0 .and R 1 C 1 have opposite sign TCs, then RC1_SIGN is set to zero, otherwise to one.A binary search is then conducted for β that causes F OUT = F TAR .These steps provide alpha and beta value estimates, which are then fine-tuned to obtain near-optimal values.The process of fine-tuning encompassed manually sweeping across the estimated alpha and beta values.The optimal alpha and beta values were subsequently obtained via linear interpolation.Finally, α 0 , α 1 , and β are truncated to 17-bit digital words D REF0 , D REF1 , and D SEL in Fig. 3, respectively.This trimming process is performed for both the main and reference TCOs.

D. FLL Design
The TCO's discrete-time operation can be represented as a linearized FLL, illustrated in Fig. 5, comprising a frequency-to-voltage (F2V) converter, an integrator, and a voltage-controlled oscillator (VCO).This model is utilized to determine loop parameters and ensure stable closed-loop operation of the TCO.The two RC branches, modulated by signal SEL with an average density of β OPT , act as a temperature-compensated RC branch that serves as F2V with the divided VCO clock F PHG (=F OUT /N = 1/T P ) as input and the error voltage V ERR (=V RC − V REF ) as output during integration phase ( INT = 1).F PHG is equal to F SS in the steady state.Since R 0 C 0 ∼ = R 1 C 1 and β OPT ∼ 0.02, the temperature-compensated RC branch's time constant is approximately equal to R 0 C 0 .When CHG = 0, V ERR of F2V can be expressed as follows: The gain of F2V, K F2V , can be derived as follows: Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
When CHG = 1, the V ERR and K F2V of F2V can be written as follows: ) where K F2V has the same magnitude of ( 14) but a negative sign.
The Miller effect, caused by C INT and the second-stage voltage gain (refer to Fig. 3), results in the integrator having a dominant pole at its first-stage output.This can be represented as a simple one-pole system, as shown in Fig. 5, with K INT and ω P denoting the voltage gain and the dominant pole of the integrator, respectively.As the integrator operates exclusively during the integration phase, and its first-stage output is dechopped by the DECHOP signal (see Fig. 3), the effective transconductance of its first-stage G M1,EFF is equivalent to 0.2G M1 when CHG = 0 and −0.2G M1 when CHG = 1, where G M1 is the transconductance of the first stage.The K INT and ω P are given as follows: where R O1 is the output impedance of the integrator's first stage and A 2 is the voltage gain of its second stage.From Fig. 5, the loop gain, LG(s), is given by where K VCO is the voltage-to-frequency gain of the VCO.Due to the chopping/dechopping operation, K F2V and G M1,EFF have the same sign, irrespective of CHG , resulting in the loop maintaining negative feedback.The closed-loop bandwidth of the loop can be approximated by its unity gain frequency in rad/s, denoted as ω UGF , which is equal to To achieve FLL stability and minimize quantization error, the unity gain frequency is set to approximately 1 kHz.

III. CIRCUIT IMPLEMENTATION
The schematic of the R 1 C 1 branch is illustrated in Fig. 6.It comprises a controllable resistor R 1 , a capacitor C 1 , a buffer for discharging/charging C 1 , and an inverter for resetting C 1 .To cope with process variation of the resistor R 1 , eight buffers are connected to eight taps of the segmented resistor R 1 , and one of the buffers is chosen by 8-bit select signal SEL_R1.This programmability allows tuning of R 1 C 1 to have comparable time constant to that of R 0 C 0 .
The reference voltage (V REF ) in Fig. 3 is produced through differential DACs illustrated in Fig. 7.The 17-bit digital input (D REF0/1 ) is first truncated to 1 bit via a second-order DSM that operates at a switching frequency of F OUT /10 (=10 MHz).Using a buffer and an inverter, it is then transformed into a pulse-density-modulated sequence S 0/1 .This process provides superior reference voltage accuracy (better than 8 ppm) and output frequency tuning resolution (22.5 ppm).To avoid potential aging effects, the supply and ground voltage levels (V DD and V SS ) are used for the 1-bit sequence conversion.The DSM employs the error feedback architecture shown in Fig. 7 and generates the second-order shaped quantization error, which is suppressed by third-order RC low-pass filters (LPFs) with 16-kHz 3-dB cutoff frequency.The differential VDAC outputs can be expressed as α 0/1 V DD and (1 − α 0/1 )V DD , where α 0/1 denotes the average of sequence S 0/1 .To prevent charge sharing between the parasitic capacitor located at the input of the integrator and the capacitors within LPF, the output of the unity gain buffer is connected to V REF in Fig. 3 when RST equals 1.This is done to charge the input capacitor of the integrator initially.Conversely, when RST equals 0, the unbuffered LPF output is connected to avoid inaccuracies stemming from the buffer's offset.
The integrator utilizes a two-stage G M − C topology, as shown in Fig. 8.The RC branches are chopped at 0.4-MHz CHG , and the first-stage output of the integrator is dechopped by the DECHOP signal to remove offset and flicker noise, thus improving the temperature stability and Allan deviation of the TCO.The transconductance of the first stage is 2 µS, and Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 9 displays the VCO schematic, which consists of three delay elements implemented with an inverter, a poly resistor, and controllable capacitors, along with a power-gating PMOS switch.The resistor and capacitors' sensitivity primarily determines the delay element's temperature sensitivity.The VCO's nominal frequency is coarsely tuned to 100 MHz using 5-bit binary-weighted metal-oxide-metal (MOM) capacitor arrays and finely tuned using MOS varactors.When the reference TCO is unused, the power-gating PMOS switch is turned off to reduce leakage current.
The schematic of the on-chip aging compensation logic is depicted in Fig. 10.A feedback loop is utilized to counteract  the frequency drift caused by aging in the main oscillator, which locks the main TCO's frequency to a less-aged reference TCO.The frequency error is measured by counting the number of main oscillator cycles within 2 16 periods of the reference clock C K PHG .This clock is obtained by dividing the reference TCO output clock by 25.Then, the ideal count represented by the 22-bit D CNT is subtracted from the counter output.The resulting error is accumulated by the digital loop filter (DLF) and is used to adjust the 17-bit digital word D REF0 , which tunes the main oscillator's frequency.

IV. MEASUREMENT RESULTS
The TACO prototype was fabricated in a 65-nm CMOS process and packaged in a plastic quad flat no-lead (QFN) package.Fig. 11 shows the prototype's die micrograph, and its active area is 0.22 mm 2 .To fully characterize the impact of resistor aging on frequency drift, RC branches with different resistors (a p-poly resistor, an n-poly resistor, an n-diffusion resistor, a silicided p-poly resistor, a metal interconnect resistor, a VIA resistor, and so on) were implemented in the prototype with the option of choosing any one or two RC branches out of them.Each RC branch comprises a 50-k resistor and a 7.2-pF capacitor implemented with an MOM capacitor situated beneath an MIM capacitor.If we count only the two RC branches that use n-poly and VIA resistors utilized in the experiment, the total area is reduced to 0.15 mm 2 .The VIA and metal resistors are implemented using a variable resistor labeled as R 1 , as shown in Fig. 6.This R 1 resistor is engineered to cover a range extending from 0.5 to 2 times the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.standard 50-k resistance, providing the capability to accommodate significant fluctuations in VIA and metal resistance.The VIA resistor implementation consists of 7980 individual unit segments, culminating in a total resistance of 100 k , all encapsulated within an area measuring 3500 µm 2 .Fig. 12 shows one such unit segment, which consists of VIA stacks and metal layers 1-6.Double VIAs connect the upper and lower routing metal layers instead of a single VIA to enhance reliability and minimize yield loss due to VIA failures.The metal resistor is constructed in a serpentine configuration, utilizing metal layers 1-6 to attain a resistance of 100 k .This resistor occupies a total area of 4050 µm 2 .
The prototype is powered by three external power supplies with the voltage levels of 1.15, 1, and 1 V for the analog, digital, and VCO blocks, respectively.The TCO's total power consumption is 121 µW, and its power breakdown is illustrated in Fig. 13.Digital blocks, such as dividers, phase generators, and DSMs, consume 58.0 µW (48%) from the 1-V supply.The VCO accounts for 39 µW (32%), while the RC branches, VDAC unity-gain buffers, and the integrator use 20% of the TCO power from the 1.15-V supply.The average power consumption of the TACO (including main and reference TCOs) is 142 µW with 21 µW of the power coming from the leakage current of the disabled reference TCO.When the aging compensation function enables, the TACO consumes 263 µW instantaneously.However, this increase has an insignificant effect on the TACO's average power consumption because of its 0.1% duty cycle.

A. Aging Test Using Standalone Resistor
An accelerated aging test was conducted on the TCO with different resistors to evaluate its aging behavior.During the testing phase, only one resistor was active at any given time, and the observed frequency drift and comparisons are illustrated in Fig. 14 and summarized in Table I.The continuous operation of the TCO with an n-poly resulted in a long-term frequency drift of within ±1033 ppm after 817 h at 125 • C, as indicated in Fig. 14(a).Conversely, the TCO with a duty cycle of 0.1% exhibited a frequency drift within ±385 ppm, highlighting the capacity of duty cycling to aging effects.Similarly, the TCOs employing various resistor types in Fig. 14 demonstrated reduced long-term frequency drift when subjected to 0.1% duty cycling compared with continuous operation.Analyzing the aging behavior of TCOs with different resistor types, TCOs equipped with p-poly resistors exhibited the most significant frequency drift of ±5200 ppm, as illustrated in Fig. 1.In contrast, duty-cycled TCOs employing alternative resistors displayed resilience in maintaining a stable frequency under aging conditions, as evidenced in Fig. 14.To investigate the impact of chopping/dechopping operation and alternating current direction through the RC branches on the frequency, the frequency drift of TCOs using VIA resistors without these techniques was measured for 817 h of aging at 125 • C, as illustrated in Fig. 15.The worst frequency drift was ±1630 ppm for the TCO with a duty cycle of 0.1% and within ±1230 ppm for the 100% duty-cycled TCO.These results demonstrate a significant frequency drift compared with the measurements in Fig. 14(d), indicating that the chopping operation and alternating current direction through RC branches can reduce the aging effect caused by long-term instability of integrator offset and dc-current-induced EM.

B. Aging Test After Two-Point Trim
The selection of resistors for the main and reference TCOs was based on the aging behavior of the TCOs described earlier.The frequency drift observed in the standalone aging test was similar among TCOs utilizing various resistor types, as depicted in Fig. 14.Nevertheless, TCOs employing n-poly and VIA resistors displayed superior frequency accuracy both before and after aging when compared with their counterparts.This advantage can be attributed to their smaller second-order TCs.Based on their superiority, in both TCOs, n-poly and VIA resistors were selected as R 0 and R 1 , respectively.The digital control words D REF0 , D REF1 , and D SEL were determined for each sample by trimming the TCOs at 85 • C and −40 • C for F OUT = F TAR = 100 MHz.The β OPT value was calculated to be ∼0.02, as the ratio of R 1 C 1 TC (1000 ppm/ • C) to R 0 C 0 product (20 ppm/ • C) was found to be large.The accelerated aging test was performed on the two-point trimmed TCOs for 500 h at 125 • C, and the results from 14 samples are shown in  Fig. 16.The inaccuracy at trim temperature points before aging in Fig. 16 is not zero, which we believe is limited by ±0.2 • C short-term temperature variation of our temperature chamber (TestEquity Model 107) during trimming.The frequency accuracy of the main TCOs before aging was ±770 ppm, but it degraded to ±1600 ppm after aging, indicating an 830-ppm degradation due to aging [Fig.16(a)].However, with the proposed aging compensation, which involves locking the frequency of the always-on main TCO to that of a 0.1% dutycycled reference TCO at 1-h intervals, the frequency accuracy of the main TCOs was ±800 ppm before aging.It degraded to ±1030 ppm after aging, indicating degradation of only 230 ppm due to aging [Fig.16(b)].The equivalent lifetime of the prototype can be estimated using the Arrhenius empirical prediction model as follows: where t life is the equivalent lifetime, t stress is the time the prototype was tested at the accelerated stress temperature T s , AF is the acceleration factor, E a is the activation energy, k is Boltzmann's constant, and T u is the temperature at normal use.With the assumption that the aging mechanism in the prototype is dominated by an n-poly resistor with an E a of 0.68 eV [26], along with a normal use temperature (T u ) of 50 • C, conducting 500 h of accelerated aging at 125  samples, wherein a p-poly resistor is substituted for R 0 in main (it is worth noting that the R 0 of the reference TCOs is represented by an n-poly resistor, while the R 1 of both the main and reference TCOs is a VIA resistor).This test provides a fair comparison with the state of the art, since most TCOs reported in the literature use p-poly resistors [16], [19], [20], [22], [36].Before aging, the inaccuracy of uncompensated main TCOs is ±870 ppm, while after 500 h of aging, it degrades to ±6210 ppm, as shown in Fig. 17(a).The degradation in accuracy appears to be mainly due to the aging of the p-poly resistor, as indicated by the comparison with the results shown in Fig. 16(a).However, with compensation, the main TCOs have a frequency accuracy of ±550 ppm before aging, which degrades to ±1070 ppm after the aging test.The   C. Supply Sensitivity and Output Clock Performance Fig. 18 shows that the supply sensitivity of ten samples on the analog supply, measured using n-poly and VIA resistors, was 1440 ppm/V over the supply range of 1.1-1.3V.The Allan deviation for a 1-s stride without chopping was found to be 40 ppm, but it was reduced to 8.1 ppm with chopping, as depicted in Fig. 19.The measured output period jitter of the open-loop ring oscillator was 5.8 ps rms [see Fig. 20(a)], while the closed-loop TCO shows a lower period jitter of The performance of the TACO is summarized in Table II, where it is also compared with state-of-the-art RC oscillators.The proposed TACO exhibits a good power efficiency of 1.4 µW/MHz, and its frequency inaccuracy is comparable to that of state-of-the-art oscillators, even in the presence of aging.

V. CONCLUSION
The presented RC oscillator is a temperature-and aging-compensated design that mitigates the long-term drift of the main oscillator by periodically locking its frequency to that of a less-aged reference oscillator.To improve the long-term stability of the oscillator, several techniques are employed.The first technique involves using higher activation energy resistors, because they exhibit smaller resistivity shifts under temperature stress.The second technique involves switching dual RC branches to mitigate the stress from dc-currentinduced electromigration.Finally, the duty-cycling method is employed to slow down the reference oscillator's aging rate.Because of these techniques, the proposed TACO achieves a frequency inaccuracy of ±1030 ppm from −40 • C to 85 • C, even after 500 h of accelerated aging at 125 • C. The oscillator exhibits a period jitter of 5.1 ps rms and a power efficiency of 1.4 µW/MHz.The proposed TACO is suitable for use in low-power micro-controller applications that require good frequency accuracy even when aging effects are present.

Manuscript received 14
May 2023; revised 19 August 2023; accepted 16 September 2023.Date of publication 11 October 2023; date of current version 28 November 2023.This article was approved by Associate Editor Drew Hall.This work was supported by Semiconductor Research Corporation (SRC) under Grant GRC Task 2810.036.(Corresponding author: Kyu-Sang Park.)

Fig. 4 Fig. 4 .
Fig.4illustrates the two-point trimming process, which first calibrates both α 0 and α 1 of TCO to the target frequency F TAR at 85 • C and then switches to −40 • C to calibrate β for the first-order TC compensation.The detailed steps of this process are as follows.Initially, Path 0 is chosen by setting the SEL signal to zero.Then, a binary search is conducted for α 0 of VDAC 0 to attain the target frequency F TAR with F OUT = F OUT0 = F TAR at a temperature of 85 • C. Subsequently, Path 1 is selected by setting the SEL signal to one, and a similar search is performed for α 1 of VDAC 1 to achieve F OUT = F OUT1 = F TAR .The process is completed by setting the temperature to −40 • C. If R 0 C 0

Fig. 15 .
Fig.15.Measured frequency drift of TCOs using VIA resistors without chopping and without alternating current direction in RC branches.

Fig.
Fig. Measured frequency inaccuracy of main TCOs using n-poly and VIA resistors before and after aging (a) without the aging compensation and (b) with the compensation.

Fig. 20 .
Fig. 20.Period jitter of (a) open-loop ring oscillator and (b) closed-loop TCO.5.1 ps rms [see Fig. 20(b)], because dominant open-loop VCO phase noise is suppressed by the FLL loop.The performance of the TACO is summarized in TableII, where it is also compared with state-of-the-art RC oscillators.The proposed TACO exhibits a good power efficiency of 1.4 µW/MHz, and its frequency inaccuracy is comparable to that of state-of-the-art oscillators, even in the presence of aging.

TABLE II PERFORMANCE
SUMMARY AND COMPARISON WITH STATE-OF-THE-ART ON-CHIP RC OSCILLATORS Fig. 17.Measured frequency inaccuracy of main TCOs using p-poly and VIA resistors before and after aging (a) without the aging compensation and (b) with the compensation.