A 117.5–155-GHz SiGe ×12 Frequency Multiplier Chain With Push-Push Doublers and a Gilbert Cell-Based Tripler

In this work, we present a fully integrated <inline-formula> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula>-band <inline-formula> <tex-math notation="LaTeX">$\times 12$ </tex-math></inline-formula> SiGe-based frequency multiplier chain. It comprises two frequency doubling and one frequency tripling stage. Each stage uses an architecture that ensures high harmonic rejection at its output and, thus, ultimately, at <inline-formula> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula>-band frequencies. The focus of this work is on describing the generation and propagation of harmonic components in the multiplier chain. Measurements show a maximum output power of 3.5 dBm and a 3-dB bandwidth of 37.5 GHz covering the range from 117.5 to 155 GHz. Over the entire <inline-formula> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula>-band, the output power varies by 9 dB. The power consumption equals 0.64 W. The harmonic rejection at the center frequency is approximately 24.5 dBc and within the 3-dB bandwidth, always above 19.5 dBc.

A prime example of a high-resolution imaging and distance/velocity measurement system is given in [4], which uses a single reference signal to drive numerous channels in multiple monolithic microwave integrated circuits (MMICs) in a synchronous MIMO configuration. If one were to apply this reference signal directly as a D-band signal, high distribution losses in terms of transmission and signal division in conjunction with a more demanding signal generation/less tunable VCO are to be expected [1], [5]. Both culminate in an increased design effort for high-frequency sources compared with similar performing frequency-multiplied lower frequency sources. Hence, the latter is often used despite its higher area consumption. This economic shortcoming can be partially offset using lower cost laminates and cheap commercially available frequency sources. However, a need for spectrally pure, high-performing multiplication stages becomes undeniable, typically met by cascading frequency doubling (x2) and tripling stages (x3).
To accentuate the potential of frequency multipliers regarding spectral purity, output power, and bandwidth, a x12 multiplier chain designed in Infineon's 130-nm SiGe BiCMOS technology B11HFC [6] showcases a cascade of two x2 stages and one x3 stage. The target frequency range corresponds to the D-band.

II. SYSTEM CONSIDERATIONS
When using high multiplication factors, a careful design is essential to reach the desired spectral purity. For each frequency, multiplication generates harmonic components called spurs in addition to the desired harmonic. When multiplying a signal with a frequency f 0 , the spurs appear at h · f 0 , where h is the harmonic number, excluding the desired multiplication factor. A higher factor is needed to reach a desired output frequency with a lower fundamental frequency f 0 . The higher the multiplication factor, the lower f 0 , and the more spurs appear in or near the target frequency range. Fig. 1 illustrates this relationship, with the hatched area displaying the D-band as the target frequency range and differently sized arrows representing either the desired harmonic or its spurs. Since two vastly different multiplication factors, ×4 and ×12, are showcased, the spurs' total number and the frequency difference between neighboring spurs differ  substantially. Hence, unwanted harmonic components appear in the target frequency range and cannot be filtered out in the case of ×12 multiplication.
Achieving very high harmonic rejections on a chip is mainly restrained by the reduced quality factors of passives and filters [7] when compared with discrete or waveguidebased components. Nevertheless, through careful design considerations, high spectral purity is accomplished in this work using an ×12 multiplier chain. It consists of a cascade of two ×2 multipliers and one ×3 multiplier in accordance with Fig. 2. While each of those stages exhibits harmonic spurs that may lead to undesired mixing and intermodulation products, high harmonic rejections at the output of each stage diminish the influence.

III. PUSH-PUSH DOUBLER FUNDAMENTALS
Push-push doublers are used multiple times in the ×12 multiplier chain for frequency doubling. The theory of these doublers is described in several works. However, they refer only to either small-signal operations [8] or use the idealized assumption that the circuit's load corresponds to an ideal resonator tuned to the 2nd harmonic of the excitation frequency [9]. Hence, we explain the theory for the largesignal operation without an output resonator in the following.
Ideally, a frequency doubler would only double the frequencies applied to its input. However, a push-push doubler has the inherent characteristic of generating additional harmonics. By considering the simplified schematic of a pushpush doubler, as shown in Fig. 3, the output voltage is Similar to the derivations in [8] and [9] to determine a push-push doublers' output voltage, using Shockley's equation resolves the currents I C1 and I C2 Therein, I S is the reverse bias saturation current, V T is the thermal voltage, and n is the ideality factor. If the differential monofrequent signal V IN with f IN = (ω IN /2π ) is applied, the voltages V BE1 and V BE2 can be expressed by the same Fourier series but with one being delayed by half a period of their fundamental frequency compared with the other one This mathematical approach considers any nonlinearities in V BE1 and V BE2 . Using the Taylor series of the exponential function for the currents I C1 and I C2 , the sum I C1 + I C2 can be expressed with the use of (3) and (4) Reducing leads to Consequently, the sum of the currents is By substituting (9) into (1), the output voltage results in Every summand in (10) contributes to one harmonic, whose order is h = k m=1 l m . All the summands are multiplied by 1 + (−1) h , which equals zero for all odd h. In addition, each summand is multiplied by (1/k!), which results in terms with a large k having only minor influence. Consequently, (10) shows the inherent characteristics of push-push doublers. Only Schematic of a push-push doubler to explain the principle of operation. Fig. 4. Block diagram of stage 1. A single-ended input signal is converted into a differential signal through a 1st balun and buffer. This signal is frequency-doubled with a push-push doubler. A 2nd active balun with a subsequent amplifier generates a differential output signal. even harmonics of a differential monofrequent input signal are generated, and the relationship between harmonic number and amplitude is opposing. Therefore, push-push doublers are suited for integration in circuits with cascaded multipliers.

IV. DESIGN AND IMPLEMENTATION
A. Stage 1 Fig. 4 illustrates the block diagram of stage 1. This stage's input is single-ended to simplify a possible off-chip signal distribution in a system with multiple MMICs. The 1st active balun and its subsequent buffer convert an input signal into a differential signal and amplify it. Together, both the components take up significantly less area than passive baluns at the corresponding frequencies. Following the 1st balun/buffer sequence, the same reasoning applies for the push-push doubler compared with, e.g., bootstrapped Gilbert cells because they would ideally require a λ /4-line [10], [11].
Finally, the single-ended and frequency-doubled output signal is converted into a differential signal and amplified by the 2nd active balun and its subsequent amplifier.
For the ensuing simulation results of the first stage, the nominal MMIC supply voltage V CC = 3.3 V was used, while −7.5 dBm of the input power was applied with a 50 port. For differential usage, the output was terminated with a 100  port. Each plot displaying a single-ended net will henceforth be normalized to 50 , whereas differential nets will have a normalized impedance of 100 . In addition, as for all the simulation results presented in this work, Sonnet EM-verified models were used for the transmission lines.
The circuit diagram of the 1st balun and its subsequent buffer is displayed in Fig. 5. For simplicity, the current mirrors are illustrated as ideal current sources. The buffer amplifies the signal and improves the amplitude imbalance and the phase difference between both parts of the differential signal. Fig. 6(a) shows the simulated amplitude imbalance and phase difference at the output of the 1st active balun and its successive buffer. Prior to the buffer, an amplitude imbalance and phase difference of 6.4-7.5 dB and 136-148 • , respectively, are present. The values could be improved with higher impedance bias networks or a current source at the common-base node of the cascode stage. However, almost constant values of 1.45 dB and 184 • are yielded at the output of the buffer. Aside from the showcased parameters, the spectral purity is presented in Fig. 6(b), which shows the relationship between the power of all the relevant harmonics, in this case, the 3rd and the 1st. From it, a minimum rejection of at least 26 dB can be determined.
For the push-push doubler designed in this work [ Fig. 7(a)], the inherent characteristics according to (10) can be observed in Fig. 7(b). Mainly even harmonics are generated, and the relationship between harmonic number and amplitude is opposing. While the 4th harmonic has a minimum difference of at least 13 dB from the 2nd harmonic, the 6th harmonic already has a difference of over 24 dB. The 1st harmonic also appears in the output spectrum since the input signal of Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. the doubler is not ideally differential [ Fig. 6(a)]. A crucial difference between the doublers in Figs. 3 and 7(a) is that the latter uses a current source, which is realized as a current mirror. This was used because it offers the advantage of setting a more stable operation point. Assuming that the current source would force a constant output current, a frequencydoubled output signal would not occur. However, this is not the case because both the transistors in the current mirror and the transistors in the differential pair have parasitic capacitances to ground. This makes the principle of operation between the doublers in Figs. 3 and 7(a) comparable.
To provide a differential signal with increased power to the next stage, the 2nd active balun and its subsequent amplifier, shown in Fig. 8, are used. To estimate the quality of the differential signal, Fig. 9(a) displays the amplitude imbalance and phase difference at the output of the 2nd active balun and its subsequent amplifier. Especially the amplitude imbalance between both parts of the differential signal is improved by the amplifier.
For the center frequency, the imbalance changes from >3 dB at the input to <0.4 dB at the output of the amplifier. Furthermore, Fig. 9(b) indicates that the 3-dB bandwidth of the amplifier's output signal exceeds the frequency range while providing a maximum power of 4 dBm to the second stage.
The amplifier's load TL 1 , which is a transmission line, introduces a filter characteristic because it realizes a frequency-dependent impedance. Its length of 710 µm corresponds to an electrical length of about (λ /10) at the center frequency of the desired 2nd harmonic and acts inductive. For frequencies in the approximate range from 51 GHz to 102 GHz, the corresponding electrical length roughly changes from (λ /4) to (λ /2), which leads to the transmission line characteristic approaching lower impedance values for higher frequencies. This is particularly apparent in the decreasing power of the 6th and 8th harmonics with an increase in frequency. In addition, the minimum rejection of the spurs to the 2nd harmonic is enhanced from 13 dBc at the output of the doubler to 17 dBc at the amplifier's output.

B. Stage 2
This stage also realizes frequency doubling and could have been realized with a mixer requiring two input signals for both its RF and LO, a modified mixer architecture as is the case with the bootstrapped Gilbert cells, or a push-push doubler. An architecture with a push-push doubler was chosen since such a doubler mainly generates even harmonics of all the applied input signal frequency components, as shown in (10).
One concept to obtain a differential output signal is to use a balun at the output of the doubler. However, for this stage, a different concept is used. As the block diagram in Fig. 10 illustrates, the input signal is converted into an IQ signal through a poly-phase filter (PPF). To compensate for the losses of the PPF, a preamplifier to each of the following pushpush doublers is used in both the I and Q paths. Note that the components in both the paths have an identical design. The frequency-doubled single-ended output signals of both the doublers considered together result in a differential signal.
The concept of frequency doubling through IQ signal generation, however, results in a high harmonic rejection differential output signal [8]. For example, assume that the output voltage of one doubler is V OUT,I and that of the other is V OUT,Q , respectively. Consequently, the differential output voltage is Assuming the in-phase voltages are covered by (3)-(10) and V OUT,I is given by (10), the quadrature voltages are Performing calculations similar to (5)-(10), (12) and (13) result in Substituting (10) and (14) into (11) leads to the output voltage 10. Block diagram of stage 2. A PPF generates an IQ signal, which is frequency-doubled by push-push doublers, resulting in a differential output signal. Analyzing (15) Consequently, not all even harmonics are present in the differential signal, but every 2nd even harmonic is eliminated. Hence, with the architecture chosen for stage 2, the 4th harmonic, which a push-push doubler inherently generates and is also its dominant spur, does ideally not appear. This is also the main advantage of the used concept compared with a frequency doubling concept, with one push-push doubler and a subsequent balun.
The generated IQ signals of the PPF do not necessarily have the same amplitude or exhibit a phase difference of precisely 90 • . To estimate the influence of these nonidealities, the amplifier and subsequent doubler are considered first. Fig. 11 shows the circuit diagrams of both the components. Due to the connection between the PPF and the preamplifier, the amplifier possesses a 385-µm differential transmission line at its input. Furthermore, akin to the doubler in stage 1, the 2nd push-push doubler has a current source to set a stable operation point.
Stage 2 is first simulated without the PPF to determine the aforementioned influence. Instead, a 100-port is applied at each preamplifier input and the differential output. The ports at the inputs always provide an added input power of −8 dBm. Fig. 12(a) shows the output power of the desired harmonic and its 4th harmonic rejection versus the phase difference of the input signals at the center frequency. Both are presented for an amplitude imbalance of the differential input signals of 0 and 1 dB, respectively. The output power and 4th harmonic rejection are maximum if the ports generate an ideal IQ signal. The output power varies by less than 1.2 dB for a phase difference in the range of 60 • -120 • . In the case of no amplitude imbalance, the 4th harmonic rejection is greater than 30 dBc in the range of 77 • -103 • . Both the output power and  the rejection are insensitive to amplitude imbalance. To show that no other spurs with relevant power occur, Fig. 12(b) displays the output power of the most significant harmonics for an ideal IQ input signal. The output power of the desired 2nd harmonic is in the range of −9.4 to −5.5 dBm over the entire bandwidth and always provides a harmonic rejection greater than 33.7 dBc.
The layout of the two-stage PPF is inspired by [12] and resembles a ring structure, as depicted in Fig. 13(a). TaN resistors and MiM capacitors, which are both located within the upper layers of the metal stack, were used for the layout. Fig. 13(b) shows the simulation results of the depicted layout obtained using Sonnet EM. The insertion losses S 21 and S 31 amount to 14.5 dB on average and their difference never exceeds 0.5 dB. In the worst case, the phase difference between the differential output signals has a maximum deviation of 13 • from the ideal IQ value. However, the layout of the PPF might be prone to process variations. Therefore, a Monte Carlo simulation of the PPF was performed to be able to determine their influence. Due to the scope of the Monte Carlo simulation, the PPF was simulated with lumpedelement models for the resistors and capacitors instead of with Sonnet EM. The corresponding results for the amplitude imbalance and phase difference are shown in Fig. 14. Process variations in 3σ can result in a phase difference of about 78 • at the center frequency, and thus a 4th harmonic rejection of about 28 dBc [see Fig. 12(a)]. The results of the PPF, obtained with Sonnet EM, are used in all the following simulations. Fig. 15 shows the simulation results of the second stage, where an input signal with a power of 3 dBm is fed to Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.   the input of stage 2/the PPF. The output power of relevant harmonic signal components at the output of one preamplifier is illustrated in Fig. 15(a), and the power at the differential output of the stage is shown in Fig. 15(b). At the output of the amplifier, the 3rd-order intermodulation product occurs with a minimum rejection of 30.5 dBc to the desired signal component. Due to frequency doubling, the desired 2nd and undesired 6th harmonics occur at the output of stage 2. As the signals generated by the PPF are not ideal, the 1st and especially the 4th harmonics also appear with a relevant maximum power of −46 dBm and −35 dBm, respectively. This results in a minimal harmonic rejection of 26.7 dBc.
However, these results are obtained by applying an ideal input signal, which is not the case considering that stage 1 provides a signal with multiple harmonics at its output, Fig. 17. Block diagram of stage 3. Two signal paths that lead to a Gilbert cell are generated using two Wilkinson dividers. In one of the two paths, the frequency is doubled, resulting in a frequency-tripled output signal. as shown in Fig. 9(b). To evaluate how stage 1 and stage 2 interact, both the stages are connected to each other. The according simulation results are displayed in Fig. 16. Here, an input power of −7.5 dBm was applied with a 50-port to the input of stage 1. The output of stage 2 was terminated with a differential 100-port. At the output of the preamplifier and at the output of stage 2, significantly more harmonics than in the sole stage 2 simulation results depicted in Fig. 15 are present. By comparing the stage 2 input signal in Fig. 9(b) with an output signal of one preamplifier in Fig. 16(a), it is noticeable that mostly the same harmonics occur and that the minimum harmonic rejection increased by 8 dB. The rejection has increased due to the frequency-dependent insertion losses of the PPF and frequency-dependent amplification of the preamplifier. The output signal of stage 2, as illustrated in Fig. 16(b), contains a large number of harmonics, e.g., caused by intermodulation and mixing in active components. Nevertheless, even harmonics are mainly prevalent in the output spectrum due to the push-push doublers in both the stages.

C. Stage 3
By means of stage 3, frequency tripling is achieved. One way to realize a frequency tripler is to apply a large input signal to an active component/amplifier to generate harmonics of the input frequency. The 3rd harmonic at the output of such a harmonic-based frequency tripler is then amplified and all other harmonics are filtered out. An example of this is given in [13]. Operating transistors in the large-signal regime, however, requires a meticulous design because effects such as self-biasing or power-dependent impedances must be considered. Consequently, a broadband design of such a circuit is very challenging. Therefore, a different multiplication scheme based on the Gilbert cells is used instead. Fig. 17 illustrates the corresponding block diagram.
Using two identical Wilkinson dividers, the differential input is divided into two paths. One divider, whose layout is based on lumped elements as in [14], and the magnitude of its relevant S-parameters are illustrated in Fig. 18.
Up to frequencies of about 120 GHz, the magnitudes of S 21 and S 31 are each above −4 dB. Both the paths created by the Wilkinson dividers lead to a Gilbert cell. To ensure that a frequency-tripled signal is obtained at the output of the Gilbert cell, a frequency doubler is placed in one of the two paths. The architecture of a bootstrapped Gilbert cell was   chosen for the frequency doubler. Since the signal frequencies in this stage are higher than in the previous stages, the required λ /4 line is less area-demanding than before. In addition, a bootstrapped Gilbert cell may exhibit gain and thus might increase the gain of the whole stage. As depicted in the schematic in Fig. 19, the bootstrapped Gilbert cell is connected to the RF input of the Gilbert cell. An amplifier precedes each frequency converter. The inputs of both the amplifiers are isolated from each other through the Wilkinson dividers. Both the amplifiers are in a fully differential cascode architecture with a resistive load and provide a wideband signal with sufficient power to their respective subsequent frequency converter.
To characterize the described frequency tripling architecture, the input of both the Wilkinson dividers and the output of the Gilbert cell are terminated with a 100-port. Fig. 20(a) shows the corresponding conversion gain. It exceeds 0 dB even at input powers below −20 dBm and reaches a peak value of 3.8 dB at an input power of −13 dBm. In addition, the Gilbert cells' output provides a variation in output power below 5.3 dB over the frequency range considered in Fig. 20(b). The minimum 1st and 5th harmonic rejection equals 15.5 and 20.5 dBc, respectively. The 1st and 3rd harmonics would provide the same output power when assuming an ideal mixer instead of the Gilbert cell. However, the load of the Gilbert cell is realized by transmission lines. As a result, the load possesses a frequency dependence and therefore realizes a lower impedance for lower frequencies.
The frequency-dependent load leads to the output impedance of the Gilbert cell being significantly lower at low frequencies.
An illustration of this is given in Fig. 21, showing a Smith chart including the Gilbert cell's output impedance and its subsequent amplifier's input impedance for both the 1st and 3rd harmonics. The output match of the Gilbert cell at the desired 3rd harmonic has a significantly better match to an impedance of 100 .
The amplifier is located at the output of the MMIC. It has a transmission-line-based load and is used to increase the output power of the broadband signal provided by the Gilbert cell. As can be seen in Fig. 21, the Gilbert cells' output and amplifiers' input are highly mismatched regarding the 1st harmonic.
For a final compact representation of all the stages, the circuits' complete block diagram with its most important quantities is shown in Fig. 22. Fig. 23 shows the measurement setup for the output power and the output spectrum of the ×12 multiplier chain. The chip input was fed by a Keysight PSG signal generator and a 40A GS Picoprobe. Accordingly, the only difference between the setups is present at the chip's output. The power was measured using a D-band Infinity waveguide GSG probe from FormFactor, a VDI Erickson PM5B power meter, and a taper. Two measurements with different setups were performed with a UXA spectrum analyzer from Keysight to determine high-frequency harmonic components. To measure spectral components in the D-band, an Infinity waveguide GSG probe, a WR6.5 SAX from VDI, and a 20-dB attenuator were used.  For the frequency range of 140-220 GHz, a T-Wave 220 GSG probe from FormFactor and a WR5.1 SAX from VDI with its corresponding 20-dB attenuator were used instead.

B. Results
A chip micrograph of the ×12 multiplier chain with an overlay of the block diagram is given in Fig. 24. The current consumption and power consumption were determined to be 195 mA and 0.64 W, respectively.
The measured and simulated power of the output signal is shown in Fig. 25. Due to the single-ended equipment used for measurement, a 3-dB correction was applied. Any losses incurred by the probe and waveguide were also considered through de-embedding. A comparison of the simulation and measurement results reveals a high degree of agreement up to frequencies of 160 GHz. The 3-dB bandwidth of the system   was determined to be 37.5 GHz, with a center frequency of 136.25 GHz. The output power displays a deviation of 9 dB across the entire D-band and a maximum output power of 3.5 dBm.
As illustrated in Fig. 26, a harmonic rejection at the center frequency of approximately 24.5 dBc is demonstrated. For input frequencies ranging from 9.25 to 13.8 GHz, the harmonic rejection exceeds 10 dBc. In comparison to Fig. 20(b), significantly more harmonic signal components are present at the output because the signal at the input of stage 3 is not monofrequent [see Fig. 16(b)]. Especially, the 6th and 8th harmonics, resulting from the inherent characteristics of the push-push doublers, lead to additional intermodulation products. As a result, the 14th and 16th harmonics are observed at the output of the ×12 multiplier. Alongside these harmonics, the 8th harmonic exhibits comparatively low rejection, particularly at high frequencies. Above an input frequency of 13.8 GHz, the rejection is less than 10 dBc. As the frequency decreases, however, the rejection increases. It is thus expected that the 8th harmonic has a rejection higher than 25 dBc at input frequencies below 13.3 GHz. Due to the  limitations and changes in measurement equipment, gaps in the curves of some harmonics can be observed. Fig. 27 shows the output power of different harmonic signal components versus the input power for three different input frequencies. According to Fig. 27(b), the maximum observed gain is 19 dB. For the most part, the input power has little effect on harmonic rejection and output power. For input powers above −15 dBm, the performance of the ×12 multiplier chain only changes marginally.
Different D-band frequency multiplier chains are considered in Table I. The ×12 multiplier chain presented in this work provides a comparably high 3-dB bandwidth. The output power is in the same order of magnitude as that of the other multiplier chains. Regarding the power consumption of frequency multiplier chains with a factor of 8 or higher, the ×12 multiplier chain consumes above average. The harmonic rejection at the center frequency and within the 3-dB bandwidth is competitive to all the multiplier chains despite the higher multiplication factor.

VI. CONCLUSION
This article presented an ×12 multiplier chain based on two frequency doubling stages and one frequency tripling stage. For each stage, an architecture was chosen that is suitable in terms of area consumption and also generates an output signal with a high harmonic rejection.
The 1st stage is based on active baluns and a push-push doubler. According to the presented push-push doubler theory, even harmonic spurs are mainly prevalent at the stages' output. For the 2nd stage, an architecture with a PPF and two pushpush doublers was chosen. A mathematical derivation and the corresponding simulations of the circuit show that, for example, the 4th harmonic of the input signal does ideally not occur at the output. Adopting this architecture, the 2nd stage generates an output signal with a high harmonic rejection of at least 23.7 dBc. The 3rd stage realizes frequency tripling using one bootstrapped Gilbert cell and one mixer implemented as a Gilbert cell. This architecture enables a robust design compared with the harmonic-based frequency triplers, which operate in the large-signal regime. The Gilbert cell provides a wideband output signal and, due to its architecture, a minimum harmonic rejection of more than 15 dBc.
On account of the design of each stage, the ×12 multiplier chain generates a wideband D-band output signal with a high harmonic rejection. Measurements show a maximum output power of 3.5 dBm and a 3-dB bandwidth of 37.5 GHz. At the center frequency, which is 136.25 GHz, the minimum harmonic rejection equals 24.5 dBc. Even though the multiplier chain has a higher multiplication factor than other D-band multiplier chains, the results indicate a competitive performance. Regarding the usability of the multiplier chain in MIMO systems with multiple channels, it must be individually assessed whether the power consumption of 0.64 W is of concern.
Pascal Stadler received the B.Sc. and M.Sc. degrees in electrical engineering from Ruhr University Bochum, Bochum, Germany, in 2019 and 2022, respectively, where he is currently pursuing the Ph.D. degree in accordance with the Universities TopIng Program and the Institute of Integrated Systems.
In 2019, he was a Student Assistant at the Institute of Photonics and Terahertz Technology, Ruhr University Bochum. Since 2019, he has been a Research Assistant with the Institute of Integrated Systems, Ruhr University Bochum. His current research interests include packaging technologies for automotive systems and integrated circuits for mmWave applications.
Mr. Stadler received the ESCRYPT Young Talent Award and the Intel Award for one of the best bachelor's degrees in the electronic specialization in 2020.
Tobias Welling (Graduate Student Member, IEEE) received the B.Sc. degree in electrical engineering from Ruhr University Bochum, Bochum, Germany, in 2019, where he is currently pursuing the Ph.D. and M.Sc. degrees in accordance with the German TopIng Program and the Institute of Integrated Systems.
Since 2018, he has been a Research Assistant with the Institute of Integrated Systems, Ruhr University Bochum. His current research interests include system design for D-band radar sensors and integrated circuits for millimeter-wave (mm-wave) applications.
Mr. Welling received the ESCRYPT Young Talent Award and the Krohne Award for one of the best bachelor's degrees in the Information Technology Specialization in 2020.
Klaus Aufinger (Member, IEEE) received the Diploma and the Ph.D. degrees in physics from the University of Innsbruck, Innsbruck, Austria, in 1990 and 2001, respectively.
From 1990 to 1991, he was a Teaching Assistant with the Institute of Theoretical Physics, University of Innsbruck. In 1991, he joined the Corporate Research and Development, Siemens AG, Munich, Germany, where he investigated noise in submicrometer bipolar transistors. He is currently with Infineon Technologies, Neubiberg, Germany, the former semiconductor group of Siemens, Munich, working in the field of device physics, technology development, and modeling of advanced SiGe technologies for high-speed digital and analog circuits. He also gives lectures on analog bipolar technology at the Technical University of Munich, Munich. He has coauthored more than 200 publications in scientific journals and conferences.
Dr. Aufinger was a member of the Technical Program Committee of the IEDM. He serves as a Reviewer for several journals and the EUMW. From 2006 to 2011, he was a Research Assistant with Ruhr University Bochum, where he was involved in integrated circuits for millimeterwave (mm-wave) radar applications. In 2011, he became an Assistant Professor with Ruhr University Bochum. In 2013, he became the Head of the Department of mm-wave radar and highfrequency sensors with the Fraunhofer Institute for High Frequency Physics and Radar Techniques, Wachtberg, Germany. In 2016, he became a Full Professor of integrated systems with Ruhr University Bochum. He has authored or coauthored more than 200 scientific papers and has issued several patents. His current research interests include ultrawideband mm-wave radar, design, and optimization of mm-wave integrated SiGe circuits and system concepts with frequencies up to 300 GHz and above, and frequency synthesis and antennas. Prof