A 37–43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD

This article introduces a high-accuracy phase and amplitude detection circuit for 5G phased-array calibration. By utilizing a 39 GHz–150 kHz down-conversion scheme, the phase and amplitude information are detected separately with a phase-to-digital converter (PDC) and an analog-to-digital converter (ADC). In addition, to reduce the number of reference signals, a divide-by-4 injection-locked frequency divider (ILFD) using a transformer-based injection-enhancing technique is implemented for wideband reference signal generation. This ILFD realizes a wide locking range of 16.3–23.4 GHz (35.8%) with 5.05-mW power consumption. The detection circuit achieves less than 0.049° and 0.036-dB detection rms errors at 39 GHz. The wideband high-accuracy detection is also achieved from 37 to 43.5 GHz. The total power consumption is 50 mW with a 1-V VDD. The total core area is 1.43 $\text {mm}^{2}$ in a 65-nm CMOS process.


I. INTRODUCTION
R ECENTLY, the data rate of wireless communication has been increasing exponentially.In 5G, a more than 10-Gb/s data rate is one of the targets to achieve massive channel communication for the increasing future applications, such as the internet of things (IoT), factory automation, and self-driving.Thus, wideband communication using a frequency of frequency range 2 (FR2) is necessary.The FR2 band realizes high-data-rate communication due to the large wideband frequency resource.However, these frequencies also have huge free-space path loss, which The authors are with the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan (e-mail: yamazaki@ssc.pe.titech.ac.jp).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/JSSC.2023.3272829.
In phased-array transceivers, the high-resolution phase and amplitude control with low errors is required for creating flexible beampatterns and preventing null degradation for multiinput and multioutput (MIMO) communications.However, the on-chip implementation of the transceiver is sensitive to the mismatch caused by process, voltage, and temperature (PVT) variations.Fig. 1 shows the phased-array beampattern with phase and amplitude mismatches between each TRX element.Ideally, the beam angle θ is determined by the phase difference φ between each element output.On the other hand, in an actual condition, each output signal has amplitude mismatch α and phase mismatch β, shown in Fig. 1.These mismatches cause sidelobe growth, beam pointing errors, and null degradation.
To calibrate these errors, a high-accuracy phase and amplitude detection circuit should be implemented [12], [13], [14], This work is licensed under a Creative Commons Attribution 4.0 License.For more information, see https://creativecommons.org/licenses/by/4.0/Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.[15], [16], [17], [18], [19], [20].In recent research, there are two detection types of circuits for phased-array calibration.One is the I/Q modulation technique, shown in Fig. 2(a) [13], [14], [15], [18].This detection technique realizes phase and amplitude detection with low power and small area consumption.However, this technique has large detection errors due to the large I/Q mismatch in the circuit.The other one is the phase-to-digital converter (PDC)/analog-to-digital converter (ADC) detection technique shown in Fig. 2(b) [12], [17], [21].This technique achieves less than 0.1 • and 0.1-dB detection accuracy with the independent phase and amplitude detection.Fig. 2(c)-(d) shows the simulated beampattern with I/Q modulated detection and PDC/ADC detection using MATLAB.The simulation is performed at 39 GHz with eight array elements and an array spacing of λ/2.The simulation applies phase and amplitude Gaussian errors on the output of each element corresponding to the detection accuracy.The pattern with I/Q detection is plotted based on the accuracy of [14].From these simulation results, the PDC/ADC detection technique achieves high-accuracy phased-array calibration, compared to the I/Q modulated technique.As a result, [12] realizes a high-accuracy beampattern in the 39-GHz phasedarray transceiver using PDC/ADC detection.However, the detection circuit needs 35 and 4 GHz off-chip signals for the calibration.Moreover, the calibration can only operate within a limited frequency band due to the narrowband characteristics of the detection circuit.
This article presents a high-accuracy phase and amplitude detection circuit with PDC/ADC detection technique for the calibration of phased-array beamforming [22].This detection circuit is designed to extend [12] and enable the high-accuracy and wide-range detection around 39 GHz.A 37-43.5-GHz detecting operation is achieved by utilizing a divide-by-4 Ring injection-locked frequency divider (ILFD) Fig. 3. Detailed architecture of the proposed phase and amplitude detection circuit for a phased-array calibration system.using a transformer-based injection-enhancing technique [23].In addition, a more detailed explanation of the PDC/ADC detection technique is provided in this article.The highaccuracy phased-array calibration using the proposed detection circuit is discussed in Section II.The detailed circuit implementations including the proposed ILFD are demonstrated in Section III, followed by the measurement results presented in Section IV.Finally, this work is concluded in Section V. II.SYSTEM CONSIDERATION Fig. 3 shows the detail of the proposed phase and amplitude detection circuit for phased-array calibration.In this figure, the mismatch calibration of the transceiver 1 element is presented.In calibration mode, a 39 GHz + 150 kHz signal is input to TRX1, and the output signal is sent to the detection circuit through the calibration path.Then, the phase and amplitude of the TRX1 output signal could be relatively detected by the proposed detection circuit.Finally, the mismatch calibration of TRX1 could be performed by tuning the VGA and phase shifter, based on the detected digital values.Similarly, the other elements could also be calibrated in the calibration mode.The required size of the Cal.LUT varies depending on the number of elements and the resolution of the beam steering for phased-array transceivers.For example, in [24], an eightelement phased-array transceiver capable of beamforming with 8-bit patterns is realized.The LUT in this transceiver consists of 256-bank SRAM for storing beam ID, and conversion tables for 256-level amplitude setting and 256-level phase setting.In Fig. 3, Cal.LUT and TRX Bias Ctrl.are shared with the phased-array control part.In the calibration mode, the Cal.LUT is updated by comparing the detected values with the original phase and amplitude values at each beam pattern.Fig. 3 explains the case where the detection circuit is implemented in a conventional phased-array transceiver.On the other hand, this detection circuit can also be implemented in a dual-polarized phased-array transceiver.In that case, Det.IN and Det.local oscillator (LO) signals can be easily input using the H and V paths without additional signal paths for calibration.
In the proposed detection circuit, a 39 GHz -150 kHz down-conversion scheme is utilized.The 39 GHz + 150 kHz signal is downconverted to a detection signal around 150 kHz by mixing with a 39-GHz LO signal.The 150-kHz detection signal is then sent to the ADC and Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.limiting amplifier (LA)-PDC chain.With a low-frequency detection signal, high-accuracy detections with 12-bit PDC and 10-bit ADC are achieved easily.Furthermore, to remove the requirement of an additional reference signal for the PDC/ADC, an on-chip clock signal generation scheme is also presented.A clock signal with around 600 MHz is generated from the 39-GHz LO signal with the divider-chain circuit, which divides the LO by 64.This clock signal is directly input to the PDC and is input to the ADC after the frequency is reduced to about 20 MHz internally.
As shown in Fig. 4, the 39 GHz-50 kHz down-conversion scheme is applied for high-resolution phase and amplitude detection with low errors.The generation of the low-frequency detection signal from 39 GHz + 150 kHz (=ω RF ) to around 150 kHz (=ω RF − ω LO ) is represented as follows: where BB is the down-converted 150-kHz detection signal and α is the conversion gain of the mixer with an LO voltage A LO .The values of phase and amplitude in the detection signal are θ Det and A Det , respectively.The part of ω RF + ω LO frequency is ignored because a low-pass filter (LPF) in the next stage will filter it out.This equation shows that the phase and amplitude information of the RF output signal can still be maintained with θ Det and A Det , after this down-conversion.
In amplitude detection, the 150 kHz can easily be detected by using an ADC with high accuracy.In phase detection, the phase information of the 150-kHz signal also becomes much easier for detection than the 39-GHz counterpart.At 39 GHz, a phase shift of 1 • corresponds to a very short time of 71 fs.Therefore, it is very difficult to detect the phase of a 39-GHz signal with high resolution.On the other hand, 1 • of the 150-kHz signal corresponds to 18 ns, which is much easier for detection.Therefore, high-accuracy phase detection can be realized with low errors by down-converting the 39-GHz signal down to 150 kHz.

III. BUILDING BLOCK DESIGN CONSIDERATION AND MEASUREMENT
A. High-Accuracy Detection Circuit Architecture Fig. 5(a) shows the detail of the 39 GHz-150 kHz downconversion block.This block consists of a 39-GHz two-stage preamplifier, a 39 GHz-150 kHz single-balanced mixer, and an LPF.The 39-GHz two-stage preamp amplifies the detection signal with low input power.To achieve high-linearity detection at large input power, a 1-bit attenuator is added in the preamp.The amplified detection signal is input to a single-balanced mixer for 39 GHz-150 kHz down-conversion.And then, the 150-kHz signal is input to the LPF to remove the unwanted mixing components.This down-conversion block is designed to suppress the degradation of the phase and gain linearity for wide dynamic-range demonstration.The simulated amplitude-modulation phase-modulation (AMPM) and amplitude-modulation amplitude-modulation (AMAM) characteristic is less than 0.03 • and 0.03 dB in 37-43.5 GHz, as presented in Fig. 5(b).The maximum input power is −12 dBm for high-accuracy detection.Fig. 5(c) expresses the detailed characteristics of the simulated down-conversion block.The flat gain and low input reflection are realized from 37 to 43.5 GHz by the matching circuit using transmission lines in the 39-GHz preamp.The LPF has a 300-kHz cutoff frequency and a gain of 13 dB.
In Fig. 6, the amplitude detection with 10-bit successive approximation register (SAR) ADC is presented.The amplitude information of the detection signal is output with its rms value.Furthermore, the average amplitude value is also detected in the ADC to compensate for the unbalance of the differential input.With a large input power, the dc offset causes clipping.Thus, the clipping calibration is performed before the amplitude rms detection.This clipping calibration ensures accurate amplitude detection for a wide dynamic range.Fig. 7(a) shows the block diagram of the 39-GHz LO distribution.The LO signal is used for both mixing operation and reference signal generation.A multistage buffer is used in the LO circuit.The impedance matching is realized by transmission lines at each stage.In addition, a 39-GHz balun is applied to generate the differential LO signal for a singlebalanced mixer.The simulated output power for the LO distribution for the mixer and the ILFD are shown in Fig. 7(b).
Fig. 8 presents the block diagram of the PDC.The PDC consists of a 12-bit counter, an edge detector for the 150-kHz detection signal, and a 12-bit D flip flop (DFF) for the output of the digital phase value.The detailed relationship between the input RF frequency f RF , the LO frequency f LO for down-conversion, and the detection frequency f Det can be represented with the following equations: where f Det is finally selected at around 150 kHz considering the desired detection accuracy.For example, when f Det = 149 kHz, values of f LO and f RF are determined to be 39.059456 and 39.059605 GHz, respectively.The PDC is designed to operate with a clock frequency of 2 12 times f Det , which is around 600 MHz.In the PDC, the input phase of the detection signal is converted to the counter output, which is a value from 0 to 4095.Thanks to the PDC, the phase value could be relatively detected.The PDC can realize phase detection with 0.088 • resolution corresponding to the 12-bit accuracy.In addition, to generate the clock signal, a frequencydivider-chain circuit is utilized, as shown in Fig. 9(a).The divider chain consists of a divide-by-8 digital frequency divider, a divide-by-2 LC ILFD, and a divide-by-4 Ring ILFD.Fig. 9(b) presents the digital divider, which consists of a three-stage cascade DFF with an inverter loop.An approximate 600-MHz clock signal is generated from the 5-GHz input.Usually, the digital divider can only be used at a few GHz frequency divisions.However, at a much higher frequency such as 39 GHz, the ILFDs are usually applied.To divide the 39-GHz LO signal, a divide-by-2 LC ILFD is first utilized for low-phase-noise characteristics, as shown in Fig. 9(c).In [17], a Ring ILFD using a dual-step injection technique is used for reference signal generation.However, the conventional ILFD cannot cover a large enough locking range due to the degradation of the injection signal at high frequency.As a result, the operating frequencies of the detection circuit become a narrow band.Next, a divide-by-4 Ring ILFD using a transformer-based injection-enhancing technique is introduced in Section III-B.

B. Transformer-Based Injection-Enhanced ILFD
A Ring ILFD can achieve high-division-ratio operation with the harmonic-signal mixing technique [25], [26], [27].However, the locking range is limited because undesired harmonic signals will interfere with the oscillator's injection locking.In recent research, ILFDs using a dual-step injection approach Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.are presented for removing undesired harmonic signals in divide-by-4 operation [28], [29], [30].However, the operation at higher frequencies is limited due to the degradation of the injection signal by the large parasitic capacitance of transistors.
In this work, a divide-by-4 dual-step-injection ILFD using a transformer-based injection-enhancing technique is implemented.Fig. 10 shows the schematic of the proposed divideby-4 ILFD.It consists of a 4-stage differential ring oscillator and two area-efficient transformers for injection enhancement.The differential input signal, whose frequency is about four times the oscillation frequency (4 f 0 ), is injected from INJP and INJN.The signals are sent to each stage of the ring oscillator through transformers.Then, the oscillation frequency is synchronized to the divide-by-4 injection frequency.Fig. 11(a)-(b) shows the block diagram of the dual-step injection ILFD with the conventional approach and with the proposed approach.As shown in Fig. 11(a), which refers to [29], the 4 f 0 injection signal is first mixed with the harmonic signal of two times frequency (2 f 0 ) generated from each  common node of differential inverters.And then, the generated 2 f 0 signal is mixed with the fundamental oscillation frequency.This dual-step injection ILFD could eliminate the unwanted harmonic signal that disturbs the injection locking operation.However, the locking range at higher frequencies is limited due to the degradation of both 4 f 0 and 2 f 0 injection signals by the large parasitic capacitance of transistors.On the other hand, Fig. 11(b) presents the proposed ILFD that applies the area-efficient transformer for impedance matching with parasitic capacitance to enhance both 4 f 0 and 2 f 0 injection signals.These injection signals are therefore increased, and the locking range could be extended.Fig. 12(a) demonstrates the transient waveform of the divide-by-4 operation with the dual-step injection technique and the proposed injection-enhancing technique.The locking range of the Ring ILFD is expanded by enhancing the dual-step injection approach with the proposed technique.Fig. 12(b) demonstrates an increase in the 4 f 0 and 2 f 0 current to the inverter stages with the injection-enhancing technique.These simulation results are obtained with an injection power range from −20 to 5 dBm and an injection frequency of 20 GHz.Thanks to the proposed technique, both the 4 f 0 and 2 f 0 currents are increased at the same injection power.
Fig. 13(a) shows the 4 f 0 and 2 f 0 signal input operation to the area-efficient transformer.In general, inductors are used for high-frequency impedance matching with parasitic capacitance.However, these inductors consume a large area for matching.In the proposed ILFD, a highly area-efficient injection enhancing technique is realized using two area-efficient multilayer transformers.In the ring oscillator, the second harmonic signals are generated at a common node of each inverter stage.At each transformer, the 4 f 0 injection signal and the differential 2 f 0 harmonic signal are inserted.The  2 f 0 harmonic signals with 0 • and 180 • , 90 • and 270 • are combined, respectively.Fig. 13(b) presents the simulation results of the impedance matching at port1 and port2 in Fig. 13(a).The 4 f 0 injection signal is sent to port1 and the 2 f 0 harmonic signal is sent to port2.According to the S-parameter simulation, port1 achieves wideband 4 f 0 frequency matching, which is from 20 to 80 GHz and port2 achieves 2 f 0 frequency matching from 0 to 30 GHz.As a result, wideband injection signal enhancement is realized for both 4 f 0 and 2 f 0 signals simultaneously for each transformer.
Fig. 14(a) shows the detailed layout of the area-efficient transformer at each layer.The transformer consists of L1 for four-times injection signal input and L2 for second harmonic signal input.The coupling coefficient between L1 and L2 is shown by k 12 .In Fig. 14(b), the equivalent circuit from the injection node to the common node of the differential stage is presented.The input capacitance C1 for removing dc, the parasitic capacitance of tail transistor Ctail, and the parasitic capacitance Cp at the common node of the differential inverter are shown.Z S and Z L the input impedance and the common-node impedance, respectively.P IN is the injection power the proposed ILFD.I INJ is the injection current to According to this equation, the injection current can be improved by maximizing k 12 , L 2 , and minimizing L 1 at the same injection power P IN .The simulated injection current against different L 1 and L 2 is demonstrated in Fig. 15(a).
To optimize L 1 and L 2 regardless of k 12 , the lumped transformer is used for simulation.They are swept from 0.38 to 1.9 nH and from 0.15 to 0.60 nH, respectively.Equation (4) shows that it is possible to inject the largest current by lowering L 1 and increasing L 2 .However, in the actual layout, k12 decreases dramatically as the L1 value decreases.Increasing L2, the area consumption of the transformer becomes large.Thus, L 1 and L 2 are optimized to 0.70 and 0.48 nH, respectively.Fig. 15(b) shows the simulated injection current to differential inverter stages with and without the proposed technique.The ILFD without the technique reuses the design of the conventional dual-step-injection ILFD [29].Injection power is kept constant at 0 dBm.In this figure, the current values are plotted in a divide-by-4 operation (i.e., 10-60 GHz injection frequency).The value of k 12 is swept from 0.19 to 0.63 by electro magnetic (EM) simulation.At k 12 = 0.63, the injection current is increased by more than three times at a higher frequency range compared with the conventional method.
The measured locking range around 20 GHz with fixed bias condition is shown in Fig. 16.At 0-dBm injection power, the proposed ILFD achieves a locking range of 16.3-23.4GHz, which is an absolute locking range of more than three times larger than the conventional technique.The power consumption is 5.05 mW at 1-V VDD.Fig. 17   frequency is summarized in Fig. 17 Compared with the conventional ILFD, this result is greatly improved with the transformer injection.Note that the measured locking range was limited to less than 67 GHz due to the operating frequency range of the used signal generator.Thus, this ILFD could work at an even higher frequency.
IV. DETECTION MEASUREMENT Fig. 18 shows the die micrograph of the proposed detection circuit.This work is fabricated in a 65-nm CMOS process, which minimizes the manufacturing cost.The total area including pads is 1.41 × 1.46 mm 2 .The core area is 1.43 mm 2 , and the power consumption is 50 mW at 1-V VDD.To perform the detection over a larger frequency range, the divide-by-4 Ring ILFD using a transformer-based injection-enhancing technique is implemented.The PDC and ADC readouts are sent to the external side by the serial peripheral interface (SPI) block.Measurement results of (a) phase and (b) amplitude detection accuracy, and the detection errors of (c) phase and (d) amplitude detection at 39 GHz.Table I presents the comparison table of state-of-theart detection circuits for phased-array calibration.The high-accuracy phase and amplitude detection is realized by using the PDC/ADC detection technique in this work.In addition, the proposed divide-by-4 Ring ILFD achieves wide-range high-accuracy detection in 37-43.5 GHz.

V. CONCLUSION
In this article, a 37-43.5-GHzhigh-accuracy phase and amplitude detection circuit for 5G phased-array calibration is introduced.In the proposed detection circuit, the PDC/ADC detection technique is applied for high-accuracy detection.To realize high-accuracy and low-cost detections, the 39 GHz-150 kHz down-conversion and the reference signal generation scheme is also applied.In addition, to realize the wideband operation of the detection circuit, the divide-by-4 Ring ILFD using a transformer-based injection-enhancing technique is implemented.The measured rms phase and amplitude detection errors are 0.049 • and 0.036 dB at 39 GHz, respectively.The wideband high-accuracy detection is also performed in 37-43.5 GHz with 50-mW dc power consumption at 1-V VDD.The total core area is 1.43 mm 2 in a 65-nm CMOS process.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

Manuscript received 20
January 2023; revised 23 March 2023; accepted 21 April 2023.Date of publication 18 May 2023; date of current version 26 September 2023.This article was approved by Associate Editor Minoru Fujishima.This work was supported in part by the Ministry of Internal Affairs and Communications in Japan under Grant JPJ000254, in part by the Japan Society for the Promotion of Science (JSPS), in part by the Tokyo Tech Advanced Researchers (STAR), and in part by the VLSI Design and Education Center (VDEC) in collaboration with Cadence Design Systems, Inc., Mentor Graphics, Inc., and Keysight Technologies Japan, Ltd. (Corresponding author: Yudai Yamazaki.)

Fig. 1 .
Fig. 1. 5G phased-array beamforming in actual conditions with phase and amplitude mismatches between each element.

Fig. 2 .
Fig. 2. Phase and amplitude detection circuit (a) with I/Q modulated detection technique and (b) with PDC/ADC detection technique, and beampattern simulation (c) with I/Q modulated detection accuracy and (d) with PDC/ADC detection accuracy.

Fig. 5 .
Fig. 5. (a) Schematic of the 39 GHz-150 kHz down-conversion circuit chain with (b) simulated AMPM and AMAM characteristics from 37 to 44 GHz and (c) more detailed characteristics.

Fig. 6 .
Fig. 6.Clipping calibration for accurate amplitude detection in the proposed circuit.

Fig. 12 .
Fig. 12.(a) Divide-by-4 operation using the dual-step injection approach and (b) values of 4 f 0 and 2 f 0 currents with and without the proposed injection-enhancing technique.

Fig. 13 .
Fig. 13.(a) Operation of four-times and two-times signal input and (b) S11 and S22 simulation results with the proposed area-efficient transformer.

Fig. 14 .
Fig. 14.(a) Layout and (b) equivalent circuit of the area-efficient transformer in the proposed technique.

Fig. 15 .
Fig. 15.(a) Simulated injection current for optimization of L1 and L2 and (b) from 10 to 60 GHz frequency range with varying k 12 values.

Fig. 16 .
Fig. 16.Measurement results of the locking range around 20 GHz with and without the proposed technique.
(a) demonstrates the total operating range with different bias settings of the ring oscillator.A 1.8-67-GHz operating range can be achieved at a 0-dBm injection power.The locking range at each center Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

Fig. 17 .
Fig. 17.(a) Measured operating range with variable bias settings and (b) measured locking range at each center frequency with and without the proposed technique.

Fig. 18 .
Fig. 18.Die photograph of the proposed phase and amplitude detection circuit.
(b).Locking ranges of 26.1-33.7 GHz (25.4%), 36.8-44.8GHz (19.6%), and 61.1-67 GHz (10.5%) are also achieved with each fixed bias setting.These measurement results of the stand-alone ILFD are provided by a signal generator (Keysight E8257D), which is connected to an external RF balun to generate differential signals.The output signal is observed by a spectrum analyzer (Keysight E4448A) in this work.

Fig. 19
Fig.18shows the die micrograph of the proposed detection circuit.This work is fabricated in a 65-nm CMOS process, which minimizes the manufacturing cost.The total area including pads is 1.41 × 1.46 mm 2 .The core area is 1.43 mm 2 , and the power consumption is 50 mW at 1-V VDD.To perform the detection over a larger frequency range, the divide-by-4 Ring ILFD using a transformer-based injection-enhancing technique is implemented.The PDC and ADC readouts are sent to the external side by the serial peripheral interface (SPI) block.Fig. 19 presents the measurement setup for the phase detection with PDC.The Det. IN and the Det.LO signals are generated from the external signal generators in this measurement.The input phase of Det.IN is changed by an external phase shifter.In addition, an external mixer and an oscilloscope are used to check the input phase value.Fig. 20 shows the waveform of the

Fig. 19 .
Fig. 19.Measurement setup of the proposed detection circuit for around 39-GHz signal detection.

Fig. 23 .
Fig. 23.Measured amplitude detection with the Det.IN step of 0.5 dB at the different bias settings of the attenuator in the 39-GHz preamp.

TABLE I PERFORMANCE
COMPARISON OF THE DETECTION CIRCUIT FOR PHASED-ARRAY CALIBRATION Fig. 21.