A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

This article presents a digital polar Doherty switched-capacitor power amplifier (SCPA) using on-chip self-calibration technique with storage capacitor array (SCA) to compensate the amplitude modulation (AM)–phase modulation (PM) distortion automatically for high data-rate signals. Such a self-calibration technique detects the AM–PM distortion at output and generates the related phase compensation in PM signals. The SCA is proposed to store control voltages of phase shifter for different amplitude code and decrease the settle time for high data-rate, which achieves fast locking of the calibration loop. Based on the proposed self-calibration with SCA, a polar Doherty SCPA is designed and fabricated in conventional 40-nm CMOS technology. This chip achieves 28.9-dBm peak output power ( $A{P}$ sat) and 43.9% peak drain efficiency (DE) at 1.8 GHz. It supports 100-MHz 64-QAM/10-MHz 1024-QAM signal with 22.6-/21.3-dBm average output power and 33.9%/32.1% average DE without digital pre-distortion (DPD).

On-chip hardware calibration techniques are also reported [43], [44], [45], [46], [47], [48] instead of DPD. The AM replica feedback linearization technique is proposed to regulate the PA bias voltage with an analog feedback loop to minimize the distortion in the AM path [43]. It requires additional digital-to-analog converter (DAC) to generate the RF envelop for the linearization, which increases the area and power consumption. The built-in AM-PM distortion selfcompensation technique utilizes feed-forward capacitors and digital PA biasing scheme to minimize the PA output capacitor variations over a wide range of PA output power [44]. Such a method achieves good AM-PM linearity for current-mode digital PA. An AM-PM self-compensation method is realized based on the opposite AM-PM distortion variation of currentand voltage-mode digital PAs [45]. This operation is only applicable for phase compensation of hybrid-mode digital PAs, which limits the application range. Moreover, the AM and the PM distortion are related to many parameters, such as frequency and process, voltage, and temperature (PVT). Thus, for different kinds of PAs, the adaptive linearization with low cost is still a great challenge.
In this article, a self-calibration technique with storage capacitor array (SCA) for AM-PM distortion of digital PA is presented [49]. The self-calibration technique proposed in this work reduces the AM-PM distortion by detecting phase in output and generating compensation in phase shifter. Thus, the proposed self-calibration technique can be used for both voltage-and current-mode DPAs. A switched-capacitor PA (SCPA) with the proposed self-calibration technique is designed and fabricated in 40-nm CMOS technology as a proof of concept, which shows good performance of both AM-AM and AM-PM linearity without DPD for 64-/256-/1024-QAM. This article is organized as follows. Section II introduces the theory of the self-calibration with SCA and the operation details of calibration process. Section III describes the architecture and circuits implementation of the proposed selfcalibration SCPA with SCA. Section IV gives the measurement results and comparison table. Section V draws the conclusion.

II. AM-PM DISTORTION SELF-CALIBRATION TECHNIQUE
The concept of the proposed AM-PM distortion selfcalibration technique is shown in Fig. 1, which is consisted of four building blocks, i.e., phase detector, operational transconductance amplifier (OTA), M-bit SCA, and vector-sum phase shifter. The AM-PM distortion is generated by the amplitude control word (ACW) controlled digital polar PA array. The phase detector compares the phase between digital PA output signal and REF signal and converts AM-PM distortion into voltage V phase . This voltage is converted to current I charge by OTA to charge the SCA. The SCA is comprised of switched capacitors controlled by decoded amplitude code S<i> (i = 1, . . . , 2 M ). One capacitor is selected by S<i> to be charged by I charge . Therefore, SCA generates variable voltage according to amplitude information from baseband, which controls the phase shifter. Phase shifting for input PM signal is produced by the phase shifter determined by V control . Thus, the AM-PM distortion is detected and calibrated by the proposed selfcalibration technique.
In the self-calibration process, the typical behaviors of each building block are shown in Fig. 2. Before the self-calibration, the typical states for building blocks are marked in red. V control from SCA and phase compensation from phase shifter are both 0. During the calibration, V phase and I charge change toward the target states with 0 AM-PM distortion (V phase = 0, I charge = 0). With continuous charging of SCA by I charge , V control is increasing, which leads to a growing phase compensation. Once the AM-PM distortion is compensated exactly, the calibration process is ended, while AM-PM distortion, V phase , and I charge are all decreased to 0. Besides, V control <i> is stored in SCA to keep the phase compensation.
A. Analysis of Self-Calibration Building Blocks 1) Phase Detector: The proposed phase detector is used to convert phase distortion into different voltages for  self-calibration. The concept of proposed phase detector is shown in Fig. 3(a), which is comprised of two switches, a parallel capacitor C P and two parasitic capacitors C par , which are the parasitic capacitors at the two output nets, i.e., V phase+ and V phase-. Note that V phase is the difference of V phase+ and V phase-. Since the control signals of switches are complementary rail-to-rail reference signals, i.e., Ref and Ref, the two switches turn on alternatively. Meanwhile, due to the PA output signal carrying PM information, the phase of feedback V F is composed of PM and phase distortion, which increases the complexity of phase distortion detection. To avoid undesired influence of PM, the input PM signal is used to generate Ref and Ref. Hence, the phase difference between reference and output signals is only related to the AM-PM distortion. Considering the ON-resistance of switches (i.e., R ON ), Fig. 3(b) shows the equivalent circuits of the proposed phase detector.
According to the detailed derivation in Appendix A, V phase is comprised of two components (i.e., V phase, dc and V phase, non-dc ), which represent the desired dc component and undesired nondc component, respectively. The non-dc component introduces swings in V phase and decreases the stability of phase compensation, which should be suppressed in circuit implementation. Note that the influence of undesired V phase, non-dc is jumped here due to the suppression in circuit implementation. Thus, V phase is replaced by the dc component V phase, dc , which is expressed as where Equation (1) is the dc component of derivation results in Appendix, which is converted from the phase distortion θ d . V ac is the amplitude of the feedback signal V F , and θ AM-PM is the AM-PM distortion in V F . Meanwhile, θ AM-PM includes a fixed phase difference between V F and differential refereneces (i.e., Ref and Ref). G C and θ RC are the amplitude coefficient and phase delay caused by the RC network of phase detector, which are related to R ON , C P , and C par as given in the Appendix. According to (1), the behavior descriptions for phase detection with different phase distortion are shown in Fig. 4. The waveform at nets V phase± is related to the ON/OFF of switches and phase delay of RC. Within the phase detection range of ±90 • , the converted dc component V phase, dc varies following θ d . When θ d = 0 • , V phase, dc decreases to 0, which means that the phase distortion is compensated exactly. Moreover, V phase, dc is simultaneously affected by the amplitude (V ac ) and phase (θ d ) of feedback signal. The sign of V phase, dc is only affected by θ d . Therefore, θ d determines whether the OTA charges or discharges the capacitor in SCA. The magnitude of V phase, dc affects the charging time of calibration process. When the phase self-calibration is completed, V phase, dc is decreased to 0. However, the magnitude of V ac is limited at small codes, which makes V phase, dc close to 0. Therefore, to improve the phase detection accuracy especially at small codes, the high sensitivity OTA is needed to small input voltage.
2) Operational Transconductance Amplifier: The OTA is introduced to convert phase-dependent voltage V phase, dc into current I charge , which charges capacitors in SCA. As shown in Fig. 5, the conversion from voltage to current is achieved by differential pair with current source, which limits the saturated output current. This conversion is necessary to lock the calibration result when the self-calibration is finished, as shown in Fig. 2. After the calibration process with I charge of 0, V control is kept constant leading to a fixed phase shifting of the phase shifter. If V phase, dc directly controls vector-sum phase shifter, the required control voltage for phase compensation is conflict with V phase, dc after calibration. Such calibrated V phase, dc is decreased to 0, when the AM-PM distortion is compensated. The conversion of differential pair in Fig. 5 from V phase, dc to I charge is derived as where I S and V t are the saturated output current and threshold input voltage of differential pair, respectively, and γ dp is a constant coefficient related to circuit parameters of the differential pair.
3) M-Bit SCA : The circuits of M-bit SCA and charging processes with various control voltages are shown in Fig. 6. The M-bit SCA is composed of N (N = 2 M ) identical capacitors and 2N switches. In the calibration process, S<i> decoded from the baseband amplitude signal of the digital PA chooses a capacitor C<i> to be charged and store V control as V<i>. The charging process of each capacitor for the initialization of self-calibration is expressed as where γ SCA is constant coefficient related to the equivalent capacitance in the charging process, including the storage capacitor and parasitic capacitors of switches. I charge (V phase, dc ) represents the varied charging current, as a function of V phase, dc . t init is the charging time. 4) Vector-Sum Phase Shifter: Fig. 7(a) shows the vectorsum phase shifter, which is introduced to generate phase compensation for AM-PM distortion. The desired phase shifting is achieved by combining the quadrature signals, i.e., V I+ and V Q+ (V I-and V Q-), as shown in Fig. 7(b). Thus, the phase shifting is related to the amplitude of V I± and V Q± , which are produced by multiplying V control± and PM_I ± (PM_Q±). Meanwhile, PM_I± and PM_Q± are converted from input PM signals to keep the PM information in PM Cal± . Since the amplitudes of V I± (V Q± ) are assumed as γ m V control+ (γ m V control-), θ ignoring variation in γ m is derived as For the compensation of AM-PM distortion, the required θ is expressed as By determining θ, the corresponding V control± can be calculated.

B. Fast Locking Self-Calibration
The transmitting of high data-rate modulation signals requires fast changing amplitude codes, which demands shorter loop response time. Fig. 8 compares the loop response time with SCA or fixed capacitor. C par1 and C par2 are the parasitic capacitors for SCA and fixed capacitor C S , respectively. Suppose that C<i>= C S , and C par1 and C par2 are much smaller than C<i>. After S<i> selects C<i>, C<i> is charged to target V<i> for AM-PM compensation. When C<i> is de-selected after the initial charging, it still stores V<i>. Therefore, after the initial charging of all capacitors in SCA, only C par1 needs to be charged between different voltage levels when switching S<1> to S<2>. For the fixed capacitor, both C S and C par2 should be charged. The response time for both cases can be determined by It can be concluded that t 1 ≪ t 2 . Therefore, the SCA with initialization decreases the loop response time of selfcalibration significantly.

A. Architecture
The block diagram of the proposed self-calibrated SCPA with SCA is shown in Fig. 9(a). The proposed SCPA is designed as 2 × 10 bit to support high-order modulation schemes. Doherty operation is used to enhance the average efficiency at power back-off (PBO). SCPA is utilized for the inherently high AM linearity.
The main and auxiliary sub-PA arrays compose the Doherty architecture. Each sub-PA array consists of 6-bit MSB and 4-bit LSB, which are controlled by thermometer and binary codes, respectively. The output signals of SCPA are combined by a 4-to-1 current combining transformer. The output matching network includes the transformer and matching capacitors C m1 and C m2 . The output of the PA is feedback to the selfcalibration circuits by a dc bias block, which is constructed, as shown in Fig. 9(a). The simulated transient voltage of RF out and V F at saturated power is shown in Fig. 10. The phase detector is implemented using thick-oxide transistors. When the proposed DPA delivers the output power of 29.4 dBm, V F is limited within 0-2.6 V, which will not overstress the phase detector. The simulated drain efficiency (DE) and saturated output power with/without the self-calibration and dc bias block are compared in Fig. 11(a) and (b) respectively. It can be seen that the proposed self-calibration and dc bias block lead to maximal 0.16% degradation of DE and 0.04-dB degradation of saturated output power in the operation frequency range of 1.4-2.8 GHz.
The ACWs of PA cells are converted from the input amplitude baseband signals by deserializers and decoders. The 11-bit amplitude codes are converted to 2 × 10 bit ACW signals for main and auxiliary PAs and deserialized by four 1:5 deserializers. Then, each 10-bit ACW is converted into 6-bit thermometer codes and 4-bit binary codes by decoders, which control unit cells of sub-PA arrays. The input signal BB_SCA is deserialized and decoded to the control signals of SCA, i.e., S<8:1>. The delay generator converts differential PM signals to quadrature types (PM_I±, PM_Q±) for phase shifter and references (i.e., Ref and Ref) for phase detector with the control of D IQ and D Ref . PM Cal is the differential calibrated PM signal, which is produced by the vector-sum phase shifter. Meanwhile, the PM level shifter converts PM Cal (0-V DD2 ) into two signals with different amplitudes, i.e., PM Cal_L with 0-V DD and PM Cal_H with V DD -V DD2 .
The 3-bit SCA is adopted to achieve coarse calibration and compact circuit size. Two 10-bit SCPAs with Doherty operation are divided into eight parts corresponding to the    AM-PM distortion of the SCPA can be carefully compensated by self-calibration loop during the amplification process.
B. SCPA Unit Cell Fig. 9(b) shows the circuits of SCPA unit cell, which consists of level shifter, AND gates, buffers, and stacked inverter. The schematic of level shifter is shown in Fig. 9(c), which shifts the voltage of the ACW from 0-V DD to V DD -V DD2 . The dimensions of NMOS and PMOS in level shifter are 0.5 µm/40 nm and 1 µm/40 nm, respectively. The AND gates combine the ACW signals (i.e., ACW_L and ACW_H) and PM signals (i.e., PM Cal_L and PM Cal_H ), which drive the stacked inverter with buffers. The stacked inverter is used to deliver higher output power with increased supply. The dimensions of NMOS and PMOS are 32 µm/40 nm and 64 µm/40 nm, respectively. The output capacitors of the SCPA unit cell are 330 fF for 6-bit MSB and 165, 82.5, 41.2, and 20.6 fF for 4-bit LSB. However, the nonlinearity is caused by the ON-resistance mismatch of NMOS and PMOS switches [50].

C. Phase Detector
As shown in Fig. 12(a), the phase detector is comprised of two transmission gates (TGs) and a parallel capacitor C P . TGs With R ON = 2.9 k of TG and C par = 2fF at output nets, the calculated V phase, dc according to (1) is normalized and compared with the simulated result, as shown in Fig. 12(b). It is seen that the calculation result matches the simulation.
Moreover, the simulated transient waveform of V phase with different initial θ d is shown in Fig. 13. The four bright lines are simulated V phase with undesired non-dc component, which introduces swings in waveform. The four dark lines are set as the dc component V phase, dc , which are calculated from V phase by averaging. The simulated response time is shown in Fig. 13, which exhibits the charging and calibration process of V phase with different phase distortion. Larger phase distortion leads to larger V phase , which requires longer initialization time for phase compensation. When the phase distortion is compensated, V phase, dc is decreased to 0.06 V. Fig. 14(a) shows the schematic of the OTA, which is composed of bias circuits, core OTA, output stage, and commonmode feedback circuit (CMFB). It uses conventional 2.5-V thick-oxide MOSFET and the dimensions of transistors are shown in the bottom of Fig. 14(a). The OTA converts V phase into I charge , which charges capacitors in SCA to generate V control for phase compensation. The simulated I charge versus V phase is shown in Fig. 14(b). The OTA shows high sensitivity to small input voltage (i.e., V phase ) to improve the detecting accuracy at small ACW codes with limited magnitude of V phase, dc . The improved linear range can lead to decreased calibration time. To suppress the influence of swings in I charge caused by V phase, non-dc , small output current (i.e., saturated I charge < 10 µA) is used. As shown in Fig. 15, the openloop gain of the OTA is simulated as 51.11 dB. The 3-dB   bandwidth is 6.69 MHz, while the unit gain bandwidth is 1.33 GHz.

E. Storage Capacitor Array
The circuit of the 3-bit SCA is shown in Fig. 16, which is comprised of eight unit cells. Each unit cell is composed of a capacitor C S and two TGs, which is controlled by a complementary switch code S<i> and S < i >. Here, S <8:1> is generated from SCA<2:0> by a 3-to-8 decoder, which converts 3-bit binary code into 8-bit one-hot code. To decrease the impact of swings in I charge caused by V phase, non-dc , the capacitance of SCA is increased to further suppress its influence. Thus, C S is 2 pF to get a stable V control for vector-sum   Fig. 17 shows V control for initialization stage with different phase distortion, which shows that the influence of V phase, non-dc is suppressed effectively. The corresponding V control values are different with various initialization time from 100 to 250 ns for initial phase distortion from −10 • to −40 • . Larger phase distortion leads to higher control voltage, which increases the initialization time with limited charging current. When the phase distortion is fully compensated, I charge decreases to 0 and the control voltage reaches a stable level. Fig. 18 compares the simulated response time for initialized SCA and fixed capacitor. When the phase distortion is switching between −40 • and −10 • , the response time with initialized SCA is much smaller than fixed capacitor. Thus, the modulation data rate of the proposed self-calibrated SCPA with SCA can be increased.
Besides, the self-calibration loop operates in both initialization process and amplifying process. In the initialization process, the calibration loop charges the capacitors to store the calibration states. In the amplifying process, the calibration loop is used to finely tune the phase compensation and refresh the stored voltage. The stored voltage affected by leakage current is re-charged by the self-calibration loop. Thus, the self-calibration loop is continuously running to hold the charge in capacitor.

F. Vector-Sum Phase Shifter
The schematic of the vector-sum phase shifter is shown in Fig. 19, which is based on NMOS and PMOS Gilbert cells. The vector-sum phase shifter uses conventional 2.5-V thick-oxide MOSFET, while the dimensions of transistors are shown in the bottom of Fig. 19. V control± determines  the current of Gilbert cells and multiplies with quadrature PM signals. Thus, the output signals, i.e., PM Cal± , achieve phase shifting by vector sum. Since the quadrature PM signals (i.e., PM_I± and PM_Q±) are generated from the input PM signals, the PM information is kept in PM Cal± after phase shifting. Fig. 20 shows the simulated phase shifting versus V control for the vector-sum phase shifter, which achieves ±45 • phase shifting range. Due to the threshold voltage of transistors for conduction, the effective variation range of V control for phase shifting is suppressed.

G. Delay Generator
As shown in Fig. 21(a)   i.e., the aimed calibrated RF out is fully covered by the phase shifting range, as shown in Fig. 21(b). The aimed calibrated RF out is the green solid line, which is orthogonal with Ref and Ref. The red distorted RF out can be fully compensated due to the cover. Case B is set that the phase shifting range cannot cover the aimed calibrated RF out , as shown in Fig. 21(c). For the covered part of aimed RF out , the phase distortion is calibrated. For the uncovered part, the AM-PM distortion exists in the shifted RF out , i.e., the red solid line at the boundary of phase shifting range. To solve this problem, Ref and Ref are tunable to shift the aimed RF out back to the phase shifting range. As shown in Fig. 21(d), with tuned D Ref , the aimed RF out is shifted back to phase shifting range, which means that the phase distortion is fully compensated.

IV. MEASUREMENT
The proposed SCPA using on-chip self-calibration technique with SCA is fabricated in conventional 40-nm CMOS technology. As shown in Fig. 22 23 shows the measurement setup. The arbitrary waveform generator (AWG) is utilized to generate the baseband signals and the differential PM signals. The sampling rate of baseband signals is 400 MHz. The RF out is attenuated by a 10-dBm attenuator and measured by a spectrum analyzer. D Ref and D IQ for delay generator are generated by MATLAB in PC and fed to the chip through a USB-SPI adaptor. The power supply of chip is 1.2 and 2.5 V for digital domain signals and PM/RF signals, respectively. All tests are performed without any pre-distortion.
With a continuous-wave (CW) signal, the peak output power, peak DE, and peak power added efficiency (PAE) are measured and shown in Fig. 24. The proposed digital PA achieves 28.9-dBm peak output power, 43.9% peak DE, and 37.2% peak PAE. The 3-dBm bandwidth is 1.4-2.8 GHz, i.e., 67% fractional bandwidth (FBW). The power consumption of the calibration loop is measured as 42.4 mW, which includes the self-calibration circuits and dc bias block. In Fig. 24, the reported PAE is calculated as the ratio of output power to total dc power consumption, which includes the power consumption of calibration loop.
The AM linearity and AM-PM distortion versus normalized AM codes at 1.8 GHz are shown in Fig. 25(a) and (b), respectively. The integral nonlinearity (INL) using normalized output voltage as a unit and the differential nonlinearity (DNL) using LSB as a unit of the AM-AM distortion are shown in Fig. 26(a) and (b), respectively. V out is approximately  linear with the input code, due to the good inherent AM-AM linearity of SCPA. The maximum AM-PM distortion is about 4.4 • with normalized code varying from 0 to 1. For normalized code larger than 0.22, it has ≤ 1.3 • AM-PM distortion. Note that the initial phase is set as 0 • . Fig. 27 shows the comparison of AM-PM distortion with/without proposed self-calibration at different frequencies. The proposed DPA shows maximal 11.1 • , 15.7 • , and 18.9 • phase variations without the selfcalibration at 1.6, 1.8, and 2.4 GHz, respectively. The maximal  AM-PM distortions are reduced to 3.9 • , 4.4 • , and 8.6 • with the self-calibration, which are decreased by 64%, 71%, and 54% at 1.6, 1.8, and 2.4 GHz, respectively. Note that the case without self-calibration is measured open loop. For discussion about the self-calibration effect across frequency, please refer to Appendix B.
The PBO DE of the digital PA is measured at 1.8 GHz and shown in Fig. 28. Due to the Doherty architecture adapted in the digital PA, it achieves an efficiency peak at 6-dB back-off in theory. The peak shifting from 6-to 5.2-dB PBO is caused   Fig. 30(a) and (b) shows the out-of-band (OOB) spectra of 25-MHz 256-QAM and 10-MHz 1024-QAM signals. Spectrum images exist due to the 400-MHz sampling rate of baseband signal [51]. Since the RF signals are generated from digital baseband signals based on zero-order hold (ZOH) interpolations, the spectral images are introduced at integer multiples of the sampling frequency, which worsen the OOB spectrum noise floor [52]. The higher sampling frequency (i.e., oversampling) can move the images to a higher offset and greatly attenuates the spectral images [34]. Besides, the firstorder hold (FOH) interpolation can be adopted in DPA design to suppress spectral images [51]. The far-out spectrum of CW signal of 1.8 GHz is measured and shown in Fig. 31. The proposed DPA operating at 1.8 GHz shows −41.9-dBc suppression for the second harmonic and −28.9-dBc suppression for the third harmonics.
The measured performance of the proposed SCPA is summarized and compared with the state-of-the-art digital polar PAs in Table. I. The proposed self-calibration SCPA achieves 28.9-dBm peak P out , 43.9% peak DE, 37.2% peak PAE, and 4.4 • AM-PM distortion. Besides, the proposed SCPA exhibits higher average efficiency with larger data rate and more than twice modulation bandwidth compared to the counterparts. Moreover, without any pre-distortion, the SCPA supports complex modulation signals, such as 100-MHz 64-QAM, 25-MHz 256-QAM, and 10-MHz 1024-QAM sig-

V. CONCLUSION
In this article, a prototype of self-calibration SCPA is presented with SCA for high data-rate signals. The self-calibration technique is proposed to compensate the AM-PM distortion of digital polar PAs. The SCA is introduced to decrease calibration response time to support high data-rate signals. The measurements demonstrate 28.9-dBm peak PA output power at 1.8 GHz, 43.9% peak PA DE, and 4.4 • AM-PM distortion. The modulation tests with 100-MHz 64-QAM, 25-MHz 256-QAM, and 10-MHz 1024-QAM signals exhibit high linearity with the proposed self-calibration technique without any pre-distortion.

A. Detailed Derivation of Phase Detection
The equivalent circuit of the phase detector is shown in Fig. 32, which has two states at different periods of Ref and Ref. Suppose that the period time is expressed as nπ + ωt, n = 0, 1, 2, . . . , 0 ≤ ωt ≤ π. It is assumed that when n = 2k, k = 0, 1, 2, . . . , Ref is logic high. Oppositely, when n = 2k + 1, k = 0, 1, 2, . . . , Ref turns to logic high. Thus, the feedback signal V F is fed to two-port alternatively and charges the RC circuit, which is comprised of R ON , C P , and C par . Due to the voltage division of series capacitors, this charging generates a voltage difference V phase , which is varying following V F . Note that the variation of V phase is increasing periodically because of the periodic switching. Meanwhile, the stable V phase is related to the phase difference between V F and switch signals of TGs. At first, the feedback signal V F is assumed as where V dc and V ac are the component and the amplitude of ac component, respectively. nπ + ωt varies from 0 to ∞. θ AM-PM is composed of a fixed phase difference between V F and control signals and the AM-PM distortion. Note that PMs are canceled because the reference signals are also phase modulated. For the two states, the circuits are both RC circuits with the same ON-resistance and effective capacitance. Thus, the voltage at output net of RC circuit is set as V ON and the output net of series capacitors is set as V OFF , respectively. They are calculated as where C e = C par + C par C P C par + C P With continuous switching, V phase+ and V phase-change between V on and V off alternatively. Based on these conditions, the phase detection process is analyzed as follows. Fig. 33 shows the variation of V phase+ and V phase-when n varies from 0 to 3.
At the beginning, at n = 0, ωt = 0, it is assumed that the voltage difference between V phase+ and V phase-is 0, i.e., V phase+ = V phase-= V dc + V ON sin(θ AM-PM ) During n = 0, 0<ωt<π, the voltages at net V phase+ and V phase-are set as V phase+,0 (ωt) and V phase-,0 (ωt), respectively. Thus, they are calculated as and the voltage difference is set as V phase,0 (ωt), which is derived as This voltage difference is stored in C P , which leads to a charging process after switching TGs. When n = 1, the connection between V phase± and V ON/OFF is switched. Then, the voltages at net V phase+ and V phase-are set as V phase+,1 (ωt) and V phase-,1 (ωt), which are derived as and V phase,1 (ωt) is derived as At n = 2, these voltages are updated as At n = 3, these voltages are updated as The formula of (25), (26), (27) is similar to (19), (20), (21), respectively. It is predictable that this similarity exists in all the following formulas. Thus, assuming these voltages are periodic, V phase,n (ωt) and V phase,n+1 (ωt) at n = 2k, i.e., k → ∞ are derived as V phase,n (ωt) = V phase,n-1 (π ) With the periodic condition of 2π, there is Based on the difference between (28) and (29), V phase,n (π ) is derived under the condition of (30), which is expressed as This approximate is reliable when the product (R ON C e ) is small enough to finish the charging process in 0 ∼ (π/ω). Thus, V phase,n (ωt) is expressed as Moreover, V ON introduces additional phase shifting in phase detection, i.e., θ RC . Therefore, the final format of V phase (ωt) is derived as V phase,n (ωt) = −(1 + γ C )G C V ac sin(θ AM-PM − θ RC ) where −(1 + γ C )G C V ac sin(θ AM-PM − θ RC ) is the converted dc component V phase, dc . The latter two components form the V phase, non-dc , which affects the stability of phase compensation. Due to 0<γ C <1, the swings of the latter two components in (33) are smaller than the converted dc voltage. According to (2), γ C is influenced by C P and C par . Thus, the capacitance of C P and dimensions of switches should be chosen carefully.

B. Analysis of Phase Detector Versus Frequency
The measured results show that the calibrated performance changes across frequency, which is caused by the phase detector. The schematic of the phase detector and driver is shown in Fig. 34(a). Here, Ref is the differential rail-to-rail square waveform signal, which controls the switches between ON-and OFF-state through the driver cells. The increasing parasitic of phased detector at higher frequency reduces the switching speed and deteriorates the phase detection accuracy. The simulated maximal phase detection error versus frequency is shown in Fig. 34(b) and (c). The phases of V F in the range of 0 • -360 • are simulated with a step of 10 • to obtain the maximal phase detection error. Fig. 34(b) and (c) shows the effect of transistor sizes of phase detector and driver on phase detection error, respectively. To extend the operation bandwidth (i.e., to reduce phase detection error at higher frequency), minimized transistor size of phase detector and larger driver cells are needed. Since 2019, she has been a Faculty Member with the State Key Laboratory of Electronic Thin Films and Integrated Devices, UESTC, where she is currently an Associate Professor. She has authored or coauthored more than 70 journals and conference papers. She holds more than 20 patents. Her research interests include microwave/millimeter-wave transceivers, mixed-signal power amplifiers, reconfigurable passive circuits, and on-chip array systems.