A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A third transformer coil is added for the inter-core coupling with the source terminals of the switching transistors. We identify that the inter-core coupling in quadrature oscillators causes an asymmetric flicker noise current, thus degrading flicker PN. As a remedy, we propose a deliberate drain-to-gate phase shift of the switching transistors by means of capacitive loading to fix this asymmetry. The ±90° I/Q mode ambiguity is also resolved by introducing another phase shift in the source-coupling; it is explained by a simplified analysis with phasor diagrams. Fabricated in the TSMC 28-nm LP CMOS, the prototype achieves PN of −112 dBc/Hz and figure-of-merit (FoM) of −185 dB at 1-MHz offset of 25.7 GHz. The measured flicker PN corner is 140–250 kHz and image rejection ratio (IRR) >47 dB over the whole 18% tuning range (TR). To the best of the authors’ knowledge, it is the best reported PN and IRR for a mm-wave quadrature oscillator.

To construct an I/Q carrier signal, the designers can choose from a multi-phase oscillator (e.g., ring oscillator), a quadrature generation block (e.g., poly-phase filters (PPFs), ÷2 dividers), or an LC quadrature oscillator (QOSC). Poor PN and low resonating frequencies make ring oscillators unsuitable for mm-wave applications. Operating oscillators at 2× frequency followed by a ÷2 divider is a suitable solution but only in the sub-6-GHz bands since doubling the operating frequency in mm-wave oscillators worsens the PN significantly [14], [15], [16]. Recently, a PPF seems to be a promising scheme for mm-wave I/Q generation [17], [18], [19], [20] since it would barely degrade the LO's PN. Nevertheless, a real-time I/Q calibration circuit [17] is required to maintain its I/Q accuracy against process, voltage, and temperature (PVT) variations. Furthermore, that approach tends to occupy a considerably large die area and requires power-hungry mmwave LO isolation buffers.
On the other hand, the PN of QOSCs [31], especially the flicker PN, may suffer from a >10-dB degradation when compared with that of a single core [43]. Generally, active injection devices are commonly regarded as the main contributor to the flicker PN [30], [41]; however, QOSCs with passive coupling (e.g., transformer coupling with fundamental [44], [45], [46], [47], [48] or super-harmonics [32], [49], [50], or capacitive coupling [51], [52]) still exhibit poor 1/ f 3 PN. Recently, an introduction of additional capacitive coupling paths [53] in a series-coupled QVCO [22] demonstrated a low flicker PN in the single-gigahertz RF range with a balanced flicker noise injection from the switching devices. However, such progress has yet to be achieved for mm-wave QOSCs (see Fig. 1). As for the flicker PN theory of QOSCs, Andreani and Mazzanti provided pioneering analyses based on a time-invariant method [33] and a time-variant impulse sensitivity function (ISF) [34]. More details of the ISF-based analysis for QOSC are found in [53]. However, such analysis mainly focuses on the current-biased QOSCs in the RF range (e.g., <5 GHz) and/or a simplified flicker noise model in long-channel devices (e.g., 0.35 μm) with a sinusoidal ISF model, which may not be suitable to explain the flicker noise upconversion in the voltage-biased mm-wave QOSCs, especially in advanced CMOS. For example, the common-mode (CM) return path has been demonstrated as having a large influence on mm-wave oscillator's flicker PN [54], [55], while its relevant discussion in QOSCs is still conspicuously absent. With the supply voltage decreasing in advanced CMOS, it is inevitable that the transistors that generate the negative resistance in QOSCs will enter the triode regions for some time [56], thereby generating higher harmonic voltage content with more complex ISFs [also must consider both differential-mode (DM) and CM tank voltages]. Therefore, a mm-wave QOSC achieving low flicker PN at same level as its non-quadrature counterpart [10], [54], [57], [58] is highly desired. To ease the learning curve for the designers, we further attempt to make the new theory analysis compatible with the recent progress in the flicker PN theory of non-quadrature (i.e., single-core) oscillators [55].
In this article, we propose a mm-wave class-F quadrature DCO using phase shifts between the drain-gate-source nodes to simultaneously achieve the I/Q exactness and suppress the flicker PN. Compared with [12], [59], this article focuses on the theoretical analysis of phase shifts to resolve the mode ambiguity while reducing the flicker PN, and with further detailed discussions on the CM return path. The rest of the article is organized as follows: Section II clarifies the mode ambiguity in the conventional QOSCs and introduces a gate-source phase shift technique for the proposed class-F QDCO with a simplified phasor-based explanation. Section III discusses the flicker noise upconversion mechanism resulting from the quadrature coupling in the proposed QDCO, which is suppressed by an induced drain-to-gate phase shift. Section IV discloses the design details. The experimental setup and results are shown in Section V. Fig. 2(a) depicts a classic LC-tank QOSC [21]. It consists of two nominally identical oscillators coupled to each other in an "anti-phase coupling" manner [60], [61], ensuring that their phase separation will be 90 • . Such "anti-phase coupling" may require four parallel injecting transistors (i.e., M 5 -M 8 ) inter-connecting the two oscillator cores. However, it is wellknown that any "anti-phase coupling" manner in QOSCs [22], [30], [44] could result in a two-mode ambiguity, e.g., V QN can either lead or lag V IP by 90 • (see the blue and red waveforms in Fig. 2(a), respectively).

A. Mode Ambiguity in Conventional QOSCs
To clearly analyze the two-mode ambiguity in the conventional LC-QOSC in Fig. 2(a), we assume V IP = V 0 ·sin ω 0 t as a voltage reference and no frequency mismatch between the two LC-tanks, and thus Then, considering initially no excess phase shift associated with the coupling (i.e., φ = 0), we portray the current phasor diagrams with I T = I osc + I inj 1 in these two modes in Fig. 2(b) and (c) (similarly as in the art of injection locking [62], [63]), where I T , I osc (chosen as a phasor reference), and I inj are the phasors of tank current, intrinsic current, and injecting current, respectively. Since I osc and I inj are generated by V IP and V inj through M 1 and M 5 (i.e., I osc = g m1 · V IP and I inj = g m5 · V inj without considerations of other higher harmonics), we obtain I osc = V IP and I inj = V inj = V QN + φ. It can be further derived that I osc must enter the pure resistive path of the LC-tank, since it is in-phase with V IP .
In Fig. 2(b), I inj leads I osc by 90 • , suggesting I inj must enter the purely capacitive path of the LC-tank to generate the same tank voltage V T (=V IP − V IN ) as I osc entering the resistive path. Accordingly, the phase shift between the tank current and voltage, α (= I T − V T = I T − I osc ), is greater than 0, and so I T partly enters the capacitive path, implying the oscillation frequency ω 0 = ω H > 1/ √ LC. We define this mode as "ω H mode," while the other mode in Fig. 2(c) is a ω L (< 1/ √ LC) mode with α < 0 and I T partly entering the inductive path.
In a practical design, φ < 0 due to the RC delay of coupling wires and parasitics, which results in I inj rotating clockwise with φ in Fig. 2(d) and (e). This causes the total tank current |I T | to increase in the ω H mode and to decrease in the ω L mode. 2 In the ω L mode, the decreasing negative φ could make I inj perpendicular to I T , reaching the most negative α (i.e., Since α depends on the frequency deviation between ω 0 and 1/ √ LC, α min represents the lowest stable ω L (i.e., ω min ). Any further decrease in φ will kill the ω L mode, quenching the oscillation, while the ω H mode with a negative φ in Fig. 2(d) operates even stronger with larger I T . In other words, once the QOSC will only work in the ω H mode. This conclusion was first derived in [39] based on complex differential equations, but we demonstrate it here in a simplified phasor circle diagram. 3 On the other hand, we could push the QOSC to operate at the highest stable frequency ω H , as illustrated in Fig. 2(f), where φ > 0 and I inj is perpendicular to I T with the most positive α (i.e., α max ). In theory, the QOSC could also operate in the region between the two blue dashed lines in the ω H mode, but it is unachievable in the conventional QOSCs due to the φ < 0 condition.

B. Resolving Mode Ambiguity in the Proposed QDCO
In a conventional mm-wave class-F oscillator [65], its drain tank (comprising L D , C D ) and gate tank (comprising L G , C G ) are mutually coupled (by k GD coefficient) to boost the third-harmonic voltage (e.g., at 3ω 0 = 3 × 2π × 10 GHz) for an efficient mm-wave frequency generation [12], [15], [54]. This benefits from the core oscillator operating at a lower frequency (e.g., ω 0 = 2π ×10 GHz) to exploit the good quality (Q)-factor of switched capacitors (sw-caps). 4 In the proposed QDCO shown in Fig. 3(a), an additional source tank (L S , C S ) is added [68] (thus making it a three-coil transformer [68], [69], [70]) to each of the two class-F DCOs [59] to form "antiphase coupling" from one transistor's drain node to another transistor's (i.e., its antipodal) source node (by k SD ), thereby generating quadrature phases (like source-coupling in [44]). Specifically, the transconductor (−G m ) switching devices are reused as injecting devices, eliminating the significant contribution of flicker PN from the conventional injecting transistors (i.e., M 5 -M 8 in Fig. 2).
The L D coil (e.g., in the I-core) is regarded as the primary coil, generating a magnetic field that is then independently sensed by two secondary coils: L G (in the same I-core) and L S (in the opposite Q-core). Thus, there is no need to consider coupling from L G to L S by k SG in the phase shift analysis. It is further supported by the fact that the V G,{IP/IN/QP/QN} waveforms show almost perfect quadrature 4 Another benefit is the much reduced injection pulling from the following PA that now operates at 3ω 0 [66]. The reduction in pulling due to the superharmonic 3ω 0 → ω 0 coupling appears an interesting research problem [67]. relationship between each other, 5 which are not affected by the L S coupling through k SG . Thus, we could only consider two transformer-based tank models associated with M 1 (neglecting k SG ) for easier understanding of the two possible modes (ω L , ω H ) in the proposed oscillator, as shown in Fig. 3(b). As indicated within "XFRM-GD," the intrinsic current in M 1 is assumed as I osc = g m V G,IP . Note that there exists a small phase shift φ GD = V G,IP − V D,IP between the coupled gate and drain tanks. In "XFRM-SD," on the other hand, the quadrature voltage (e.g., V D,QN ) is coupled by k SD to the source node of M 1 (i.e., V S,QN ) with a small phase shift of φ SD = V S,QN − V D,QN , generating the injecting current I inj = −g m V S,QN . Accordingly, the total tank current is I T = I osc + I inj .
To be able to remove the ±90 • mode ambiguity in Fig. 3(b), we analyze the relationship between I osc , I inj , and φ SG around M 1 , with the latter serving the same purpose as φ in Fig. 2. We can control φ SG through its individual components: passive phase shifts of drain-to-gate (φ GD ) and drain-to-source (φ SD ) windings of XFMR-GD and XFMR-SD transformers, respectively, as follows: As we demonstrate in [64], φ GD can be controlled by the gate-drain capacitance ratio X as follows: and the corresponding normalized oscillation frequency 1 (with respect to the resonant frequency ω G of the gate tank) as follows: where k GD is the coupling factor between L G and L D coils, n = √ L G /L D is the effective turns ratio of the transformer in XFMR-GD, and ω 0 is the oscillation frequency that depends on C G and C D for a given transformer. Accordingly, φ GD (X) could be derived as follows: indicating that it is a monotonically decreasing function of X. Intuitively, a large capacitance presented on the gate side of XFRM-GD would tend to delay the coupled waveform across the windings.
On the other hand, to introduce the required φ SD , the source capacitance C S is added. It barely affects the oscillation frequency ω 0 (unlike with C G and C D ). Similarly, we define which mainly depends on the absolute capacitance rather than a capacitance ratio. In an analogy to (6), φ SD is which is also a monotonically decreasing function of C S (intuitively, the heavier the loading by C S , the greater the tendency to the phase delay). Thus, considering (3), (6), and (8) for a given X (i.e., fixed φ GD ), φ SG is also a monotonically decreasing function of C S . In other words, I inj will rotate clockwise with an increase in C S to quench the ω L mode, as shown in Fig. 3(c).
To verify this proposed technique, we sweep C S from 150 to 750 fF in our class-F DCO with X = 3 (e.g., C G = 337.5 fF, C D = 112.5 fF, ensuring strong V H3 /V H1 of ∼40%). It can be observed in Fig. 4(a) that the QDCO first operates at ω L (≈2π × 9.9 GHz, V D,QN leads V D,IP by 90 • ) but then it switches the mode to ω H (≈2π × 10.4 GHz, V D,QN lags V D,IP by 90 • ). This validates our analysis in Fig. 3(c), which is further supported by the numerical verification of φ GD and φ SG in Fig. 4(b).  Fig. 4(a).
Interestingly, the PN of the proposed class-F QDCO, especially its flicker PN (i.e., PN at 10 kHz), improves drastically upon the switchover from ω L to ω H , 6 as illustrated in Fig. 4(c). At the same time, it warns against the excessively large C S as it can ruin the close-in PN at 10 kHz. Therefore, we select C S = 350 fF [with φ SG around 2.5 • at ∼10 GHz; see Fig. 3(c)] 7 for our design. Fig. 5 shows plots of the simulated frequency and PN at 10 kHz over the entire tuning range (TR) for two values of C S . Fixing C S at 350 fF completely solves the mode ambiguity problem.

III. FLICKER PN IN CLASS-F QUADRATURE OSCILLATORS
In this section, we study the flicker noise upconversion mechanisms in both the modes (i.e., ω L and ω H ) of the class-F QOSCs and propose a negative drain-to-gate phase shift technique to suppress the flicker PN.

A. Flicker Noise Upconversion in ω L and ω H Modes
First, let us start with analyzing the PN of the proposed class-F QDCO in the ω H mode with C S = 350 fF. By sweeping X, 8 Fig. 4(d)-(f). Interestingly, the class-F operation by itself does not necessarily ensure a significant improvement in PN (although independently useful for the third-harmonic extraction in mm-wave frequency generation [15], [54]), since its thermal PN (i.e., PN at 10 MHz) stays almost constant from X = 1 (with V H3 /V H1 ≈ 6%) to X = 4 (with V H3 /V H1 = 30%). This is because the thermal PN caused by the 4kT γ g m noise is roughly reduced A GD times [64], [71] (rather than by the class-F itself), while gets saturated when X is large enough [see Fig. 4(e)].
Furthermore, we observe a correlation between the reduction in flicker PN (i.e., PN at 10 kHz) and negative φ GD . This differs from the situation in [72] and [64] where X is set to <0.4 so as to introduce positive φ GD for the flicker PN suppression. To further quantitatively study the flicker PN in QOSCs, we use a periodic transfer function (PXF)-based flicker PN theory framework introduced in [54], [55], [73], and [74]. The flicker PN (caused by a single MOS transistor, e.g., M 1 in Fig. 3) is calculated as follows: where I 1/ f, rms (t) 9 (unit: A/ √ Hz) is the periodically modulated rms value of the flicker noise current at a low offset frequency ω (e.g., 2π × 10 kHz), T 0 (=2π/ω 0 ) is the oscillation period, and h DS (t) (unit: rad/C) is the non-normalized ISF [75] associated with V DS , describing the phase response of V DS against current impulse perturbations. 10 The intuitive understanding and simulation methods of I 1/ f,rms (t) and h DS (t) [based on the periodic transfer function (PXF)] were provided in [55] and [73] for numerical verification according to (10). Obviously, decreasing the net integral area under h DS · I 1/ f,rms is the key factor in suppressing the flicker PN [55], rather than the long-standing myth [75] of only relying on the oscillation waveform symmetry.

B. Flicker PN Reduction by Negative Phase Shift
Three representative cases are simulated and numerically verified in Fig. 6. In the ω L mode in Fig. 6(a), I 1/ f,rms shows less exposure to the falling edge of V DS than to its rising edge, leading to the positive net area of h DS · I 1/ f,rms [see Fig. 6(b)] and, ultimately, to the flicker upconversion. In contrast, in the ω H mode, I 1/ f,rms is exposed less at the V DS 's rising edge [see To gain better insight into the above phenomenon, we should first study the terminations of second-and thirdharmonic currents, which are the key factors causing the oscillator waveform asymmetries that lead to the non-zero net integral area of h DS · I 1/ f,rms in non-quadrature oscillators [55], [64]. As shown in Fig. 7(c), the CM current enters the inductive path in all the cases (in both the ω L and ω H modes), while the third-harmonic DM current entering the 9 This can be roughly modeled by periodically modulated transconductance G m and drain current I D ; hence, it mainly depends on V GS around the saturation region of MOS transistor (e.g., large V GS with large I 1/ f, rms ) [54]. 10 Sharper rising or falling edges in V DS are more robust to noise (i.e., presenting the narrow (in time) and small (in magnitude) h DS in these edges), while its less steep edges (also implying longer noise exposure time) are more vulnerable to noise (i.e., showing wide and large h DS ). On the other hand, V DS 's peak and bottom are immune to the noise (i.e., h DS = 0 in these time instances).  resistive path with X = 3 or V H3 is fully suppressed by X = 0.07. Obviously, proper terminations of the second-and third-harmonic currents cannot explain the persistent presence of flicker noise upconversion in QOSCs.

C. Numerical Verification and Discussion
We identify that it is the quadrature coupling voltage that causes different exposure strengths of I 1/ f,rms to V DS 's rising and falling edges, changing the picture of flicker PN upconversion. To verify our claim, we first simulate I 1/ f,rms (based on the simulation method in [55]) without taking into consideration the coupling source waveform V S,QN (i.e., setting V S,QN = 0), which shows similar I 1/ f,rms in the two modes [see Fig. 7(a) and (b)]. Then, with V S,QN engaged, in the ω L mode, the peak of I 1/ f,rms at t ≈ 30 ps (i.e., exposure to the V DS 's falling edge) gets significantly reduced, while in the ω H mode, it decreases the peak of I 1/ f,rms at t ≈ 70 ps (i.e., exposure to the V DS 's rising edge). For easier understanding of this phenomenon, we draw the time-domain shapes of V G,IP and −V S,QN inside the boxes in Fig. 7(a) and ( Obviously, in the ω L mode, it is the bottom of the quadrature coupling waveform −V S,QN that reduces the rising edge of V GS of M 1 and lowers the corresponding I 1/ f,rms , when compared with the case without V S,QN coupling. On the other hand, in the ω H mode, the bottom of −V S,QN lowers the falling edge of V GS , resulting in the decreasing I 1/ f,rms . 11 Thanks to the controllable φ GD in the transformer-based oscillator, we could fine-tune the I 1/ f,rms exposure in either the V DS 's falling or rising edge by moving the peak of V GS toward V DS 's falling or rising edge to obtain the null net area of h DS · I 1/ f,rms . All the simulated PN results are also verified with calculations based on (10), thus demonstrating the efficacy of the above analysis.
The simulated PN of the proposed class-F QDCO and the single-core class-F DCO [15] is plotted in Fig. 8, indicating that the flicker PN in the single-core case suffers from the ill-behaved second-harmonic voltage with an undefined CM return path [54]. The proposed quadrature class-F oscillator achieves ∼3 dB better thermal PN (i.e., at 10-MHz offset) due to the two cores' coupling (the thermal noise of the equivalent parallel resistance gets reduced by half [37]) and a ∼8-dB PN improvement at 10-kHz offset, thanks to the proposed phase shifting technique.

IV. CIRCUIT IMPLEMENTATION
The schematic of the implemented oscillator was shown earlier in Fig. 3(a). The QDCO core resonates at ∼10 GHz but the differential signal at the drain nodes in each of the I/Q cores is rich in the third-harmonic component and so it is fed to a harmonic extractor (HE), which is a differential amplifier operating at ∼30 GHz and is re-used from [54]. The HE is then followed by another amplifier stage to drive the 50external load of the test equipment. The two cores are connected using the "anti-phase coupling" routing, and the source coil of the I-core is placed inside the Q-core for coupling, and vice versa. L S degrades Q D and Q G by 0.7 (5.5%) and 1.6 (10%), respectively, which has little influence on the oscillator's thermal PN.

A. Transformer Design Details
As a convenient rule of thumb, the width of the coil could be set to ∼10× skin depth at the operating frequency (e.g., 10 μm at 10 GHz) as a starting point for the Q-factor optimization. The spacing between the coils is about 6 and 10 μm for, respectively, k GD = 0.63 (boosting thirdharmonic voltage for further extraction [15]) and k SD = 0.25 (weak quadrature injection). The size of the transformer is optimized for the intended operating frequency to achieve high Q-factor but without excessive coupling to the substrate, whose self-resonant frequency (where k GD vanishes) is around 5× the operating frequency. The dummy filling with the native layer ("NT_N" layer for high substrate resistivity [76] and extended in all the directions by 30 μm away from the coils) is reused from the inductor's process design kit (PDK) for easily passing the design rule check and minimizing the Q-factor loss.

B. QDCO's CM Return Path and Decoupling Scheme
A well-defined CM return path is necessary for achieving low flicker PN, especially in mm-wave oscillators [54]. Surprisingly, the CM return path in a QOSC is altogether different from that in the conventional single-core [55] or dual-core oscillators (see [77, Fig. 13]). As shown in Fig. 9, the secondharmonic currents (representing CM) generated by M 1,2 are anti-phase with those by M 3,4 (absorbing each other) since their fundamental voltage waveforms are in quadrature. This eventually results in the supply (V DD ) and ground (V SS ) nodes being in-phase for the CM currents on each side. For the purpose of completing the CM return paths and saving the I/O pads, we connect the two sets of V DD /V SS /V B routings of the I/Q cores by the on-chip decoupling capacitance. It should be noted that no CM currents enter these on-chip decoupling capacitors 12 (as well as the sw-cap banks), so they are merely used to stabilize the dc voltages. These shared I/Q supply lines were extracted by the EMX simulator together with the main transformers for accurate CM analysis. A "T-type" RC filter is used for V B lines to enhance the CM stability at either high frequencies (considering the parasitic CM inductance of the transformer) or low frequencies (considering L bond ).

C. Switched-Capacitor Banks and I/Q Imbalance Sources
To cover the >15% TR target with sufficient resolution, the sw-cap banks are organized as shown in Fig. 10(a). The two 7-bit coarse-tuning sw-cap banks are put at both the gate and drain nodes and tuned together, ensuring X ≈ 3 for the strong V H3 /V H1 [see Fig. 4(d)] across the TR (i.e., C G,max /C D,max ≈ C G,min /C D,min ≈ C G /C D , see [54]). The 8-bit IQ calibration bank and 9-bit fine-tuning bank are put only at the drain nodes for precise control of IQ mismatch and frequency, respectively, while their small capacitance ranges have little influence on X.
The coarse-tuning unit with a 13-MHz LSB uses a resistor-biased structure [78], as shown in Fig. 10(b), for enhancing the Q-factor and lowering parasitics. The resistors' bottom terminals (i.e., at the drain-source nodes of the switch) can experience a significant swing when the main switch is OFF. The disturbance can propagate to the joint upper terminal due to the layout imbalance; thus, the resistors' top terminals are connected to CW coarse , rather than to CW coarse . This arrangement could avoid any disturbance coupling back to the switch transistor's input, ultimately affecting the flicker PN due to the sw-cap banks. The 9-bit fine-tuning sw-cap bank uses a single-ended structure with biasing via transistor channel leakage for area-saving and routing ease, as depicted   in Fig. 10(c). Thanks to the custom MoM capacitor, the unit provides C = 50 aF, corresponding to f = 70 kHz.
For the design of the I/Q calibration banks, we should consider the sources of I/Q mismatch, which mainly include: 1) local process mismatches between the two resonant tanks and 2) mismatches due to the asymmetric layout routing. The I/Q mismatch can be calibrated quite easily, without any PN degradation, by providing a small offset between the tuning codes of the two calibration banks. The Monte Carlo simulations were performed for the coarse bank (dominant capacitance), with results shown in Fig. 11: the standard deviation of capacitance σ global = 23.8 fF when "global" (i.e., die-to-die) variations are applied, corresponding to a coefficient of variation (CV = σ/μ) of 4.6%. Considering only 'local' mismatches (i.e., within a die), σ local = 112.3 aF, which translates to a CV of 0.02%, thus being much less than the global mismatch. An alternative PPF-based quadrature generation [17], [18] would have to cover the global mismatches (and process corners) of both the resistance and capacitance, while the resistance can vary hugely from die to die, similar as in Fig. 11(a). However, for our QDCO, it only needs to consider the local mismatch of capacitance, while its global mismatch would not cause any I/Q mismatch. The inductance mismatch could be safely neglected, as the transformer dimensions are very large compared with the possible manufacturing error. On the other hand, based on the comparisons between different levels of EMX extraction, we identify that the routing mismatches (see Fig. 9) lead to around 0.6 • of phase mismatch, while the weak magnetic coupling between the two transformers in the I-and Qcore [79] introduces a ∼1 • quadrature error.
The two I/Q calibration sw-cap banks are located within the I-and Q-cores. They provide 8-bit resolution, supporting the ±12.8 fF de-tuning (3σ local ). The phase sensitivity of the QDCO is ∼1 • /fF at the third-harmonic as per simulations. Thus, the I/Q calibration sw-cap bank can cover around ±12.8 • phase mismatch. The entire sw-cap arrangement occupies a considerable area, as shown in Fig. 9. To ensure simulation accuracy, the proposed QDCO is simulated based on an EMX black-box flow, where all the transformers (I-core and Q-core) with all the routings are extracted as an S-parameter model, while the G m and sw-cap banks are regarded as black-boxes and post-extracted by Calibre. High metal layers are only considered once in EMX, and the contact ports between the two models are carefully considered. Several iterations of tuning the sw-cap ratio may be needed to further enhance the third-harmonic voltage in the final post-layout simulation.

V. EXPERIMENTAL RESULTS
The prototype of the proposed QDCO is implemented in a TSMC 28-nm LP CMOS process, occupying an area of 0.26 mm 2 , as shown in Fig. 15.

A. PN Measurements
The PN measurements are performed based on an equipment combo of Keysight E5052B signal source analyzer,   E5053A microwave downconverter, 11970A harmonic mixer, and 11636C power divider. The output of the QDCO is down-converted by 11970A and then E5053A, and finally fed into E5052B. The three levels of capacitor banks at the drain and gate nodes cover the measured TR from 25.7 to 30.7 GHz (17.7%). When operating at 25.7 GHz [see Fig. 12(a)], the measured PN is −111.5 dBc/Hz at 1-MHz offset, with an excellent 1/ f 3 PN corner of 140 kHz. At the highest frequency of 30.7 GHz, as shown in Fig. 12(b), it achieves −109.2 dBc/Hz at 1-MHz offset, with a 250-kHz flicker PN corner. Fig. 12(c) illustrates the PN performance of the QDCO over the whole TR. The PN at 1 MHz steadily increases with frequency, whereas the flicker PN corner ranges from 140 to 250 kHz. With a power supply of merely 0.6 V, the power consumption over the TR is around 29 mW, including 10 mW consumed by two third-harmonic extractors (HE). This results in the best-in-class FoM of −185 dB and it varies only within 1 dB over the TR. The measured frequency pushing at 0.6 V is merely 24.7 MHz/V.

B. IRR Measurements
IRR measurements are based on an I/Q frequency upconversion scheme [39], [80], as shown in the setup in Fig. 13(a). A two-wire I/Q baseband signal at ω BB = 2π × 50 MHz is generated by Keysight 33 600A, which is then converted into a four-wire differential version by two BALH-0010 baluns. The RC-bias network on the PCB sets the dc signal level before feeding it internally on-chip. In the on-chip I/Q mixer, the baseband signal cos ω BB is mixed with sin ω LO while sin ω BB is mixed with cos ω LO 13 ; afterward, these two components are summed. This arrangement cancels out the ω LO − ω BB component while leaving only the ω LO + ω BB component. Assuming that the baseband signals are free from any mismatches, the I/Q imbalance of the LO (i.e., the QDCO under test) will cause the residue (i.e., image) signal at ω LO − ω BB . The power ratio of the desired signal to the image signal is defined as IRR. The single-ended I/Q mixer output is monitored by R&S FSW-85 signal analyzer. A schematic of the on-chip double-balanced current-mode mixer for the IRR testing is shown in Fig. 13(b), where the differential component outputs are combined and converted into single-ended by an on-chip transformer.
The measured IRR spectra at the two ends of TR are shown in Fig. 14(a) and (b), exhibiting IRR of 47.6 and 50 dB at f LO,min and f LO,max , respectively. They maintain IRR > 46 dB across the whole TR, as illustrated in Fig. 14(c). While sweeping the power supply level of the QDCO, the measured IRR maintains >46 dB, as plotted in Fig. 14(d) without any real-time calibration, as commonly used in PPF [17], [18]. The large LO leakage was identified to be caused by the LO signal's coupling to the power supply of the mixer, which could be normally avoided by a more careful layout and isolation.
The performance of the proposed QDCO is summarized in Table II and compared with the state-of-the-art mm-wave QVCOs/QDCOs and also mm-wave quadrature signal generation circuits in which LO is off-chip. To the best of the authors' knowledge, the QDCO achieves the lowest PN of −110 dB/Hz at 1-MHz offset from 30 GHz, the record-low flicker PN corner with a state-of-the-art FoM. In terms of I/Q imbalance, our QDCO also features the highest level of IRR.

VI. CONCLUSION
Accurate quadrature frequency generation with low PN in mm-wave (e.g., 28/39 GHz) bands is necessary for supporting large-bandwidth (e.g., 800 MHz) and complex modulation schemes (e.g., 256-QAM). Compared with the poly-phase filter (PPF) approach, the conventional QOSCs are more robust to PVT variations but suffer from significant flicker noise upconversion. In this article, we propose a low flicker PN mmwave class-F quadrature digitally controlled oscillator (DCO) with a third-harmonic extraction. We demonstrate that the quadrature coupling voltage itself causes different exposure strengths of flicker noise current to the rising and falling edges of the oscillation waveform, leading to the flicker noise upconversion, which is solved here by a negative drain-to-gate phase shift (thereby tuning the exposure strength of flicker noise current). At the same time, a deliberate phase shift is introduced in the transistor-source I/Q coupling path to avoid the ±90 • mode ambiguity. This is supported by a complete analysis on the basis of a simple phasor diagram.