A 23–40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA

This article presents a 23–40-GHz phased-array receiver (RX) capable of reconfiguring to achieve fine phase step and high gain range. Such phased-array RX consists of a 14-bit phase-gain manager and a wideband noise-canceling low-noise amplifier (NCLNA). The proposed phase-gain manager includes two 7-bit variable gain amplifiers (VGAs) in radio-frequency (RF) domain, two pairs of mixers, and two variable gain sign-map (VGSM) circuits in intermediate-frequency (IF) domain. The proposed phased-array RX can not only provide a maximum 14-bit phase-tuning operation and >35-dB gain variation range but also achieve an improved calibration-free image rejection ratio (IRR) by introducing the dual-mode image rejection operation. Based on the aforementioned structure, a four-element phased-array RX is implemented and fabricated in a 40-nm CMOS technology. The whole circuit size is 2.2 $\times $ 1.3 mm, while consuming 52 mW per element. The measured result shows a state-of-the-art minimal noise figure (NF) of 3.8 dB, which supports 3 Gb/s, 64-QAM and 2.4 Gb/s, 256-QAM modulation signal.

The wideband RX operating in a complex environment would suffer from the multiple interferences, especially the image signal located in the radio-frequency (RF) passband. Thus, the suppression of image signal is a great challenge for the wideband RX array to support high data rate transmission. In general, the image rejection (IR) is usually performed using the in-phase and quadrature (I/Q) mixing architecture [35], while the image rejection ratio (IRR) is depended on the phase and amplitude imbalances of I/Q signal generator. The conventional I/Q generators based on the coupler [36] or poly-phase filter (PPF) [37] are limited by the related narrow frequency range with good phase and amplitude balance. The phase and amplitude calibration technique is introduced to improve the IRR [22]. Nonetheless, the additional phase and amplitude-tuning devices are required in the I/Q generator, while the calibration loop and related control circuits increase the complexity of the RX system. The wideband I/Q generator improves the phase and amplitude balance hence achieving high calibration-free IRR within a wideband, in sacrifices of the related large circuit size [38]. Therefore, the design of a wideband phased-array RX with the reconfigurable This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ phase-gain-tuning capability and high calibration-free IRR still remains great challenge.
This article is an extension of the authors' previous work [39], which presents a 23-40-GHz phased-array RX in a 40-nm CMOS technology. The proposed phased-array RX consists of a 14-bit phase-gain manager and a noise-canceling low-noise amplifier (NCLNA). Such phase-gain manager consists of radio-frequency variable gain amplifier (RFVGA), mixer, and variable gain sign map (VGSM), which features two advantages.
1) The amplitude control bits of RFVGA and VGSM are flexibly reconfigured to provide the gain-tuning and vector-sum-based phase-shifting operation. Compared with previous work with a fixed phase-gain-tuning module [40], the gain-tuning range and phase resolution in the proposed RX are adjusted to meet the requirements of high dynamic range or high beam-scanning accuracy in different applications, as shown in Fig. 1(a). 2) Fig. 1(b) exhibits that the proposed RX with phase-gain manager is adjustable between two sign-map modes for upper and lower bands IR. Compared with the singlemode IR architecture [41], the RF bandwidth (BW) with high IRR is extended in the dual-mode RX without any calibration in local oscillation (LO) signal.
Based on the aforementioned mechanisms, the proposed phased-array RX is designed and implemented in a 40-nm CMOS technology for verification, while the measured result exhibits a state-of-the-art performance. The article is organized as following. The prototypes with principle and theoretical analysis of the phased-array RX and the phase-gain manager are discussed in Section II, while Section III presents the circuit implementation. In Section IV, the proposed phasedarray RX is fabricated, measured, and compared with the stateof-the-arts. The conclusion is summarized in Section V.
II. PRINCIPLE AND OPERATION Fig. 2(a) shows a typical configuration of the conventional Hartley IR down-converter with vector-sum-based phase shifter. In the Hartley IR down-converter, a pair of mixers driven by quadrature LO signals are connected with a PPF to achieve high IRR. Meanwhile, the vector-sum-based phase shifter consists of two RFVGAs, two sign-control circuits, a 90 • phase shifter, and a combiner. The 360 • phase-shifting is divided into four quadrants by the sign-control circuits, while the phase-shifting in each quadrant is depended on the various gains of two RFVGAs. The 90 • phase shifter in the vector-sum phase-shifting architecture includes some drawback for ON-chip implementation, such as high loss, narrow bandwidth, and large area. As shown in Fig. 2(b) [22], the I/Q mixing architecture is used to replace the 90 • phase shifter, which avoids the lossy RF path caused by the 90 • phase shifter. Meanwhile, two mode selectors are connected to the quadrature mixer. Using the mode selector to change the polarity of mixer output signals, a dual-mode IR operation is introduced to reject the upper and lower bands of image signal, respectively. With such dual-mode operation, the RF bandwidth with high IRR is improved without a bulky wideband I/Q generator. However, such RX architecture requires two different LO signals to drive the mixers in the separated phase shifter and IR down-converter, while the signcontrol circuit increases the complexity of the RF signal path and introduces additional parasitic. Therefore, Fig. 2(c) shows the architecture of the proposed phase-gain manager with the dual-mode IR. The sign-control circuit and IR mode selector are merged into a single sign-map circuit, which feature two advantages.
1) The sign-control circuits of the i -and r -paths are shifted to intermediate-frequency (IF) domain, which reduce the complexity and undesired parasitic of the RF signal path. Therefore, enhanced gain and noise figure (NF) are obtained in RF front-end.
2) The phase-shifting and dual-mode image rejection functions are achieved in a single module, which reduce the control complexity. By tuning the polarities of signcontrol codes (i.e., SI, SQ, SIO, and SQO), the proposed RX covers 360 • phase-shifting in four quadrants and achieves dual-mode image rejection, simultaneously. Meanwhile, such sign-map circuit is designed with variable gain, which increases the control bits of the vectorsum-based phase shifter for the phase-tuning resolution enhancement. Fig. 3(a) exhibits the simplified configuration of the proposed phase-gain manager. The RF input signals are transmitted to two RFVGAs (i.e., A i1 and A r1 ) to generate RF r and RF i signals, respectively. Assuming two RF signals at lower and upper sidebands with amplitudes of A L and A H are injected into the RFVGA, as shown in Fig. 3(a). The RF r and RF i signals are expressed as Here, ω L and ω H are the angular frequencies of lower (i.e., ω L = ω LO − ω IF ) and upper sidebands (i.e., ω H = ω LO + ω IF ), respectively. Then, RF r , RF i signals and the quadrature LO signals (i.e., LOI and LOQ) are mixed in the mixer, which provides four IF signals (i.e., IFI i , IFQ i , IFI r , and IFQ r ) with the amplitude weights i and r , and quadrature phases I and Q. Assuming the mixer is linear and provides unit conversion gain, the four IF output signals IFI i , IFQ i , IFI r , and IFQ r are calculated as IFI r and IFQ i are injected into the VGSM and combined as IFI output, while the IFQ output consists of IFQ r and IFI i . The IF signals with amplitude weights of A i1 and A r1 go through the VGSM with gains of A i2 and A r2 , respectively. The polarity of each IF signal is depended on the sign-control codes SI, SQ, SIO, and SQO. Then, the IFI and IFQ signals are expressed as To suppress the image signal and combine the desired signal, a 90 • phase-shifting is introduced in the IFI path before recombining with IFQ by a differential amplifier. Thus, the IF output signal is derived as From (9), the gain (i.e., A IFL and A IFH ) and phase (i.e., P IFL and P IFH ) of the lower and upper sidebands' input signals are derived as where A i and A r are the total gain of the i -and r -paths, respectively, which are expressed as Based on (10) and (11), the upper sideband signal is suppressed once SIO = SQ and SI = −SQO (i.e., IR mode 1), while the lower sideband signal is eliminated under the case of SI = SQO and SIO = −SQ (i.e., IR mode 2). Meanwhile, the quadrant of IF signal is determined by the sign-control code. Therefore, the control logic of the phase-gain manager to obtain the dual-mode IR and four quadrants' phase-shifting are derived, as shown in Fig. 3.
Equations (10)- (13) suggest that the amplitude and phase of the IF output signal are depended on the total gain of the i -and r -paths (controlled by VG i code and VG r code, respectively). Meanwhile, the amplitude controls of RFVGA and VGSM are configured to provide phase or gain control by changing the control logic. Therefore, the phase resolution and gain-tuning range are adjusted to meet the different requirements in various applications. As shown in Fig. 4(a), in gain-control operation, the gain is varied with constant phase-shifting by increasing or reducing the amplitude-control codes of the i -and r -paths, simultaneously. For the phase control, the phase in each quadrant is tuned by oppositely adjusting VG i code and VG r code. In quadrants 1 and 3, the phase is increased by tuning up VG i code and reducing VG r code, as shown in Fig. 4 Fig. 4(c) exhibits that higher phase-shifting is achieved in quadrants 2 and 4 by reducing VG i code and increasing VG r code.

III. IMPLEMENTATION
A phased-array RX is designed and implemented based on the aforementioned mechanism. The schematic of the proposed phased-array RX is shown in Fig. 5. Four identical RXs are combined to a single IF output, while a 1-to-4 low-loss Wilkinson power divider is loaded with four I/Q generators to provide the quadrature LO signals for each RX. Each RX consists of a wideband NCLNA, a 14-bit phase-gain manager, a PPF, and a differential IF buffer. The digital codes to control the 14-bit phase-gain manager are provided by the ON-chip decoder. Meanwhile, the RC-C R PPF is connected to the phase-gain manager with quadrature IF output, which recombines the desired signal and suppresses the image signal. Besides, a differential output buffer with a single-end output is used and connected to the RC-C R PPF.

A. Phase-Gain Manager With Coupler-Based I/Q Generator
As shown in Fig. 6, the 14-bit phase-gain manager includes two 7-bit RFVGAs, four mixers, and two VGSMs with 5-bit IFVGAs and 2-bit sign control. Meanwhile, the quadrature LO signals to drive the mixers are generated by an I/Q generator. Based on the discussion in Section II, the key component in the proposed phase-gain manager to achieve the four-quadrant phase-shifting function and dual-mode IR is the VGSM. Two identical VGSMs generate quadrature IF signals' output (i.e., IFI and IFQ) in the proposed phasegain manager, while the VGSM with IFI signal output is discussed as follows. The input signals IFQ i and IFI r are divided and injected into two pairs of IFVGAs, respectively. Besides, the gains of two pairs IFVGAs (i.e., A i2 and A r2 ) are depended on the 5-bit amplitude-control codes VG i 7:11 and VG r 7:11 , respectively. The IFVGAs in each pair are enabled or disabled by two sign-control codes with inverse logic level (i.e., SQ and SQ for A i2 pair, SI and SI for A r2 pair, respectively). Then, the aforementioned two IFVGAs with inverse control logic are connected to the plus and minus pins of the differential amplifier, respectively. Therefore, the  polarities of IF signals are depended on the sign-control codes. In the proposed VGSM, the IFVGAs and differential IF amplifiers are implemented using inductor-less configuration for compact circuit size, which feature a low-pass characteristic. Lower IF frequency leads to the improvement of gain and linearity. However, in the proposed RX with the dual-mode IRR operation, the RF bandwidth with high IRR is depended on the IF frequency (i.e., f IF ), as shown in Fig. 1(b). Higher IF frequency supports larger RF bandwidth without increasing the LO range. Therefore, to achieve performance trade-off among circuit size, gain, linearity, and RF bandwidth with high IRR, the IF frequency is chosen as 2 GHz in this work. The proposed 7-bit RFVGA is configured in a cascode topology, while the gain of RFVGAs in the RF i -and RF r -paths are controlled by the 7-bit VG i and VG r codes, respectively. A transformer-based gain-boosting technique is introduced to the CG FET of RFVGA, which improves the maximum gain without increasing the power consumption, and for detailed discussion, refer to Appendix A.
The system IRR is depended on the I/Q mismatches between IFI and IFQ signals [42], while the detail discussion is given in Appendix B. In the proposed RX, both the imbalances in the I/Q generator and phase-gain manager affect the I/Q mismatches of the IFI and IFQ signals. Note that the phasegain manager is implemented in a symmetrical architecture, which shows relatively slight amplitude and phase imbalances about 0.21 dB and −0.15 • , respectively. Meanwhile, the phase and amplitude imbalances' variations in the Monte Carlo simulation are negligible, as shown in Fig. 7. Therefore, the system IRR is mainly determined by the I/Q mismatches of the I/Q generator. Fig. 8(a) shows the configuration of the proposed coupler-based I/Q generator, which is folded to reduce the size. In general, the balance resistor of a couplerbased I/Q generator is 50 to achieve low I/Q imbalance. However, the I/Q imbalance increases rapidly once the output of the coupler is connected to a reactive load (i.e., mixer). The voltage gain and return loss of the coupler loaded with mixer are shown in Appendix B. As described in Fig. 8(b), a capacitor C B = 30 fF is in parallel with a resistor R B = 20 to combine as an optimized balance network with impedance of Z B . Fig. 8(c) exhibits that the I/Q balance is significantly improved by the optimized balance network.
As discussed in Section II, the proposed phase-gain manager provides two IR modes, while Fig. 4 in Section II reveals that the IR mode is switched by changing the sign-control logic. The phase-gain manager operates in mode 1 once SQ = SIO and SI = −SQO are satisfied, while works in mode 2 with the configuration of SQ = −SIO and SI = SQO. Therefore, a mode-control code (i.e., MC) is introduced into a mode selector for the required sign-control codes' generation, as shown in Fig. 9. By the dual-mode IR operation, the required LO range is 25-38 GHz for the RX system operating at 23-40 GHz. As described in Fig. 8(c), the phase and amplitude imbalances within the required LO range are smaller than ±4 • and ±1 dB, respectively. As shown in Fig. 10, the simulated phase-tuning range in each quadrant is about 90 ± 2 • , which reveals a good balance in four quadrants. Meanwhile, Figs. 11 and 12 reveal that in four quadrants covering the 360 • phase shifting range, the proposed RX with dual-mode IR operation achieves high calibration-free   IRR within the operation bandwidth of 23-40 GHz. Note that the dual-mode IR operation is not affected by the phase or quadrant settings, while the IRR variations in various quadrant and phase settings are mainly due to the I/Q mismatches in the phase-gain manager. The IRR under process and temperature variations is shown in Appendix B.

B. Wideband NCLNA and RFVGA
The wideband NCLNA is used in this work, which provides stable low NF within wideband compared with the cascode or common-source (CS) LNA topology [43], [44], [45], [46], [47]. The schematic of the proposed NCLNA is exhibited in Fig. 13, which is configured in a common   gate (CG) noise-canceling topology. The main path of the proposed NCLNA is composed of a CG amplifier (i.e., M 1 ) with a wideband T-shape interstage matching transformer and an amplitude-adjusting amplifier (i.e., M 3 ). Meanwhile, the auxiliary path of the NCLNA includes a CS amplifier (i.e., M 2 ) and an amplitude-adjusting amplifier (i.e., M 4 ). As shown in Fig. 13, the noise introduced by M 1 of the CG amplifier (i.e., modeled as noise current I n1 ) generates two out-ofphase noise voltages at its drain and source. The noise at the drain of M 1 is amplified by M 3 , and then canceled at the output transformer by the in-phase replica noise. Such inphase noise is generated from the source noise of M 1 , which is amplified by the auxiliary path before canceling. By properly adjusting the gains of M 3 and M 4 , the noise-canceling ratio is improved [48]. In the proposed NCLNA, the gain and operation bandwidth is determined by the performance of the main path. The CG amplifier in the main path provides intrinsic wideband input matching in sacrifice of a relatively small gain. Therefore, a transformer-based gain-boosting technique and a T-shape wideband interstage matching network are used in the main path, which improves the gain and extends the bandwidth of the proposed NCLNA, and for detailed analysis, refer to Appendix A. Fig. 14(a) shows the layout of the proposed gain-boosting transformer. The inductor L G connected to the gate of M 1 introduces a gain-peaking operation at higher frequency [49]. Therefore, L G is designed with relatively small inductance to avoid the stability issue at a higher frequency. The gain-boosting operation is depended on the coupling coefficient between L S and L G . In general, due to the parasitic capacitance coupling between primary and secondary windings of a transformer, the equivalent coupling coefficient is reduced with higher frequency. Such coupling coefficient variations degenerate the gain at higher frequency and compress the operation bandwidth. Therefore, in the proposed transformer, L G surrounds the outer coil of L S to reduce the capacitance coupling. Fig. 14(b) exhibits that the inductance of L G and L S is 165 and 282 pH at 30 GHz, respectively, while the coupling coefficient k 1 = 0.38 shows negligible variation from 20 to 45 GHz. Fig. 15(a) depicts the layout of the proposed T-shape wideband inter-stage matching network. As mentioned in the Appendix, a weak coupling between L 1 and L 2 extends the operation bandwidth of the matching network. Therefore, the inductor L 1 is partly coupled with L 2 to achieve a weak coupling. Such a partly coupled transformer provides greater design flexibility to obtain the required coupling coefficient once the inductances of L 1 and L 2 are allocated. Fig. 15(b) shows that the inductances of L D , L 1 , and L 2 at 30 GHz are  The output transformer of the proposed NCLNA combines the signal to a single-end RF output and suppresses the commonmode noise. Fig. 16 exhibits that the in-band input return loss |S 11 | is lower than −9.5 dB, while the stability factor is larger than 1.5 in the proposed NCLNA. The RF output signal of NCLNA is split and transmitted to the RFVGA. As shown in Fig. 17(a), the proposed NCLNA generates two transmission poles at 24 and 42 GHz. By connecting to the RFVGA with a maximum gain at 33 GHz, an RF front-end with a wideband frequency response is obtained. Meanwhile, Fig. 17(b) exhibits that compared with the conventional CGLNA + RFVGA, the in-band NF of the proposed NCLNA + RFVGA is improved. Here, the structure of CGLNA used in simulation is the main path of the proposed NCLNA.

IV. MEASURED RESULTS
Based on the aforementioned structures, the proposed phased-array RX is implemented and fabricated using a conventional 40-nm CMOS technology. Fig. 18 exhibits the micrograph of the fabricated phased-array RX, where the chip occupies an area of 2.2 × 1.3 mm. Then, the fabricated chip is measured for verification. The proposed phasedarray RX consumes 208 mW from a 1.1-V power supply. The performance of the single RX is obtained by ON-chip measurement. The IRR, NF, and linearity are measured under the maximum gain setting; the best IRR is 52 dB at 26 GHz in mode 1 and 43 dB at 29 GHz in mode 2, as shown in Fig. 19. Note that mode 1 achieves higher IRR at 20-27 GHz compared with mode 2. Therefore, the proposed RX is configured to operate in mode 1 at 20-27 GHz and mode 2 at 27-40 GHz. Using the proposed dual-mode IR operation, the frequency range with calibration-free IRR > 30 dB is significantly improved from 23 to 30 GHz (mode 1 only) to 23 to 36 GHz (mode 1 + mode 2). Fig. 19 reveals that the minimum NF is 3.8 dB, and the NF < 5 dB is achieved from 22.1 to 39.5 GHz. Besides, Fig. 20 exhibits that the in-band output 1-dB compression point OP 1 dB is varied from −1.2 to 3.3 dBm. The peak OP 1 dB = 3.3 dBm is obtained at 36 GHz, and the related input 1-dB compression point IP 1 dB is −26.8 dBm. Fig. 21 exhibits that the peak gain of each RX is 33 dB with 3-dB BW of 23-40 GHz, while a 35-dB gaintuning range is achieved under a 7-bit gain control (4-bit in RFVGA and 3-bit in IFVGA). Fig. 22 shows that under 7-bit gain control, the RX maintains 400-MHz BW 64-QAM with an EVM of 2.99%-5.71% from −52 to −20 dBm input power   (P in ), 500-MHz BW 64-QAM with an EVM of 3.65%-5.97% from −51 to −24 dBm P in , and 300-MHz BW 256-QAM with an EVM of 2.77%-3.89% from −49 to −20 dBm P in . Therefore, the proposed RX provides high dynamic range to support high data rate, which is applicable in short-range communication application with relatively large input power. Here, the 4-bit gain control in RFVGA with 14-dB tuning range is assigned to avoid the saturation of mixer and LNA with increasing input power, while 21-dB tuning capability is provided by the 3-bit gain control in IFVGA. Fig. 23(a) exhibits the 14-, 10-, and 7-bit phase-tuning at 28 GHz. The effective phase-tuning resolutions after digital pre-distortion (DPD) are 10-, 8-, and 6-bit, respectively. Meanwhile, the rms phase errors are 0.26 • at 14-bit phase control, 0.56 • at 10-bit phase control, and 1.88 • at 7-bit phase control. Here, the DPD for phase-shifting is performed by selecting the phase settings with ±0.5-dB gain variation for phase-control linearization, while the phase setting with relatively large gain variation is eliminated by the DPD procedure. Fig. 23(b) shows   that the phase-control linearity is improved after DPD, and the high phase-tuning resolution is attractive to achieve high beam-scanning accuracy in large-scale array for long-range communication.
The test circuit board of the proposed phased-array RX is shown in Fig. 24. The control codes of the phased-array RX are generated by an on-board control circuit, while four wideband antennas [50] are used for signal receiving. Such antenna is implemented in a separated printed circuit board 2 (PCB 2), while the control circuit, device under test (DUT), and power supplies are fabricated in PCB 1. PCB 1 and PCB 2 are bonded together with a glue layer. With the aforementioned fabrication procedures, the receiving mm-wave signals are isolated with the dc power and digital control signals. Then,  the proposed phased-array RX is verified in a 3-m over-the-air (OTA) measurement setup shown in Fig. 24. An OFF-chip LO signal with a power of 10 dBm is used to drive the phasedarray RX. The TX modulation signals are generated by a signal source and an arbitrary waveform generator (AWG), while a horn antenna is used to transmit the TX signal.
The test board of the proposed phased-array RX is clamped in the head of a tripod, and the incidence angle of the   TX signal is adjusted by the angle tuner of the tripod. The beam patterns are measured under the incidence angles of ±30 • , ±15 • , and 0 • . Fig. 25 shows that the 0.26-and 0.31 dB-amplitude variations are obtained after adjusting the gain of the RX array in the 28-and 37-GHz OTA measurements, respectively. Here, sidelobe suppression is relatively low at 37 GHz since the distance between each wideband antenna unit is about 0.9 λ in this case. As described in Fig. 26, the phased-array RX supports 3.0 Gb/s, 64-QAM and 2.4 Gb/s, 256-QAM modulation signals with the SNRs of 35.14 and 36.43 dB, respectively. Meanwhile, Fig. 27 reveals that the proposed phased-array RX supports high data rate at 24, 37, and 39 GHz, simultaneously. The performance summary of the proposed phased-array RX and the comparison with the state-of-the-arts are shown in Table I. Compared with previous work aiming for 5G NR at the 28-and 39-GHz bands, the proposed phased-array RX provides improved phase-tuning resolution and comparative gain-tuning range. Meanwhile, low NF and high calibration-free IRR are achieved within a wide operation frequency range covering the 24/28/37/39-GHz bands for 5G NR.

V. CONCLUSION
This article presents a phased-array RX. The key component of such phased-array RX is the 14-bit phase-gain manager, which provides fine phase step, high gain range, and high calibration-free dual-mode IR. Meanwhile, NCLNA with gain boosting and wideband interstage matching is presented to achieve low NF within a wide frequency range. Then, four RXs with the coupler-based I/Q generator are combined to the proposed phased-array RX. With the state-of-the-art performance, the proposed RX is attractive for wideband mm-wave wireless applications (e.g., 5G).

APPENDIX A
The transformer-based gain-boosting technique is used in CG FET of the proposed NCLNA and RFVGA. As shown in Fig. 28(a), by introducing an inverting gain (i.e., −A) between the gate and the source of M 1 , the effective transconductance (i.e., g m1 ) is boosted to [51] Larger g m1 leads to a higher gain, while the aforementioned inverting gain −A is implemented using a gain-boosting transformer, as shown in Fig. 28(b). Here, C gs and C p are the parasitic capacitors of M 1 and pad, respectively. The gainboosting transformer includes the inductors L S and L G , while the coupling coefficient between two inductors is k 1 . The effective inverting gain A of the gain-boosting transformer is expressed as [51] where ω is the angular frequency, and the equivalent inductor at the gate of M 1 (i.e., L G ) is calculated as The mutual inductance M k1 is the determined by the coupling coefficient of transformer k 1 , which is expressed as    Fig. 29 exhibits that g m1 is increased with k 1 . In the CG amplifier, higher g m1 provides larger voltage gain and smaller NF, in sacrifice of lower input impedance [52]. Since the input impedance can be compensated by an additional matching network, larger g m1 is required for low NF and high gain. However, due to the feature of the positive feedback function, the stability is reduced using the proposed gainboosting scheme. Meanwhile, the effect of parasitic capacitors leads to larger g m1 at higher frequency, which degenerates the stability factor. Therefore, appropriate k 1 should be chosen once L s and L g and the size of M 1 are allocated. In this work, k 1 is designed to provide high g m1 while maintaining the stability factor of the CG amplifier larger than 1 during circuit implementation. To achieve a wideband interstage matching between the CG amplifier and the following amplitude-adjusting amplifier, a T-shape matching network is used. Such T-shape matching network is consisted of inductors L D , L 1 , and L 2 . Meanwhile, the inductors L 1 and L 2 construct a transformer with coupling coefficient k 2 . The small-signal equivalent circuit of the T-shape matching network is shown in Fig. 30, while the input impedance (i.e., Z int ) is calculated using (18), as shown at the bottom of the next. Here, the loading impedance Z L is expressed as Z L = R L + s L s1 + (sC GS ) −1 , while M k2 = k 2 (L 1 L 2 ) 1/2 and R L = g m3 L s1 /C GS [53] are the mutual inductance of the transformer and equivalent input impedance of M 3 , respectively. Then, |S 11 | of the matching network is calculated from the input impedance [54]. As shown in Fig. 31, such T-shape network generates two resonant frequencies to achieve a wideband impedance matching. Meanwhile, the bandwidth with good impedance matching is extended by increasing the coupling coefficient k 2 slightly.

APPENDIX B
The IRR is depended on the phase and amplitude imbalances of the IFI and IFQ signals, which is expressed as [42] IRR = (1 + ε) 2 − 2(1 + ε) cos φ + 1 (1 + ε) 2 + 2(1 + ε) cos φ + 1 (19) where ε and φ are the amplitude and phase imbalances, respectively. Then, Fig. 32 exhibits the calculated IRR under various I/Q imbalances, and higher IRR is obtained with low phase and amplitude imbalances. The imbalances between the IFI and IFQ signals are mainly contributed by the I/Q generator in the proposed RX. Fig. 33 shows that the coupler-based I/Q generator provides a voltage gain of about 3 dB at the reactive load with high impedance. Meanwhile, the input return loss is improved once an optimized balance network (i.e., Z B = R B (1/(sC B ))) is used. Fig. 34(a) exhibits the simulated resistance and capacitance of implemented balance network under various process errors and temperatures. The temperature shows negligible influence on the capacitance and resistance, while the resistances with Z int = s s M 2 + L 1 (Z L + s L 2 ) + L D (Z L + s(L 1 + L 2 + 2M)) process corners of ff, tt, and ss are 17.7, 20.1, and 22.8 , respectively. Meanwhile, the self-shielded 3-D interdigital capacitor [55] is used, and the capacitances under +10%, normal, and −10% process errors of metal width are 34.8, 30.8, and 28.2 fF, respectively. Then, to investigate the effect of process errors on the system IRR, the I/Q mismatches of the coupler and related system IRR are simulated under three cases.