A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24–71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR

This article introduces a power-efficient 24.25– 71-GHz multi-band phased-array receiver supporting all allocated fifth-generation mobile network new radio (5G NR) frequency range 2 (FR2) bands at 24/28/39/47 GHz and the potential 5G NR-U bands in unlicensed 57–71 GHz. A novel harmonic-selection technique is introduced to extend the operating bandwidth with low power consumption. By switching between the fundamental-selected mode, the second-harmonic-selected mode, and the third-harmonic-selected mode, only signals in the desired bands can be preserved, while the unselected mixing components are rejected. A dual-mode multi-band low-noise amplifier (LNA) based on a configurable transformer is adopted to realize broadband operation with minimized power consumption and noise figure (NF). The Hartley architecture is employed to further improve the image rejection performance. A hybrid-type polyphase filter (PPF) with a detector-based high-precision calibration block is utilized in this work to realize the Hartley operation with reduced insertion loss (IL). The proposed phased-array receiver is fabricated in a standard 65-nm bulk CMOS process. With the concerted efforts of all components, the proposed multi-band receiver can support 5G standard-compliant OFDMA-mode modulated signals up to 256QAM with a 400-MHz channel bandwidth from 24 to 71 GHz. Better than 36-dB inter-band blocker rejections can be maintained by this work. With existing of 0-dBc inter-band blockers at worst case frequencies, this receiver shows EVMs of −33.3, −30.9, −31.6, and −28.5 dB at 28, 39, 47.2, and 60.1 GHz, respectively. The power consumptions for a single receiver channel are 36, 32, 51, and 71 mW at 28, 39, 47.2, and 60.1 GHz, respectively.


I. INTRODUCTION
M ILLIMETER-WAVE (mmW) communication is indispensable in the next-generation network to satisfy the exponentially growing data traffic between massive devices. To further improve the data rate and channel capacity, the fifth-generation mobile network new radio (5G NR) bands keep scaling toward frequencies over 100 GHz. The frequency allocations for 5G usage in various countries are shown in Fig. 1 [1]. The frequency resources in 28-, 39-, and 47-GHz bands have already been regulated in 5G standard. The 60-GHz spectrum is also under discussion. To realize global application and cross-standard communication, multi-band compatibility is necessary for user devices in 5G NR networks. As indicated in Fig. 1, the necessary operating frequency range with complete support of 5G NR bands mentioned previously should be at least 24.25-71 GHz. Phased-array architecture is essential in 5G NR communications to improve signal quality at mmW frequencies. 5G NR phased-array systems with competitive receiver performance have been published with narrowband designs recently [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14]. However, multiple chips are necessary to support the multi-band operation, which increases the system size and complexity. To realize compact user devices with low cost, several studies have demonstrated wideband phased-array receivers supporting multiple 5G NR frequency range 2 (FR2) bands with minimized system dimensions in recent years [15], [16], [17], [18], [19], [20], [21], [22]. However, the operating frequency range of these works is still limited and difficult to be scaled to more 5G NR FR2 bands. In addition, multi-band operation also exposes the receiver to more cluttered and rapid-changing electromagnetic (EM) environments. Power-efficient and wideband receiver architecture with enough rejections to inter-band blockers will, hence, be required for such receivers.   [20], [21]. (b) Conventional multi-band configurable Hartley receiver [18]. (c) Proposed multi-band Hartley receiver utilizing the harmonic-selection technique.
This work introduces a CMOS multi-band phased-array receiver covering 24.25-71 GHz. Complete 5G NR FR2 bands can be covered. A harmonic-selection technique is proposed to extend the operating bandwidth with low power consumption. Improved inter-band blocker tolerance can also be maintained by this work. This article, which is an extension of [23], is organized as follows. Section II introduces the system consideration of the proposed multi-band phased-array receiver. The proposed harmonic-selection technique and the detailed circuit implementations are explained in Section III. Section IV presents the measurement results. Finally, the conclusion is drawn in Section V.

II. SYSTEM CONSIDERATION
As mentioned previously, the 24.25-71-GHz operation is necessary to be covered for supporting complete 5G NR FR2 band operation. The frequency plans of conventional and proposed multi-band receivers with 24-71-GHz radio frequency (RF) coverage are shown in Fig. 2. As shown in Fig. 2(a), the conventional multi-band receiver based on the superheterodyne architecture achieves multi-band operation with wideband signal path design [20], [21]. With high intermediate frequency (IF), the images can be completely removed from the passband of the low-noise amplifier (LNA). However, the fractional bandwidth of the local oscillator (LO) path will be much larger when the RF frequency coverage scales to 24-71 GHz. The power consumption of both RF and LO will become incredibly large to guarantee the required conversion gain (CG). Moreover, the image frequency will also be inevitably overlapped with the passband of LNA; even a high IF frequency is used. To tackle with this issue, the Hartley architecture is adopted to provide full-band image rejection in multi-band receivers [17], [18], as shown in Fig. 2(b). Conventional multi-band receiver employs the configurable Hartley architecture to select the desired sideband. Therefore, 24.5-43.5-GHz RF frequency coverage can be realized with a high image rejection ratio (IRR) [18]. A single multi-band LNA is also utilized for providing wideband signal amplifying. However, the noise figure (NF) of such a system will be degraded by around 3 dB since the images are still located in the passband of the LNA. When the RF frequency coverage is extended to 24-71 GHz, the LO frequency range will be also enlarged. Quadrature LO generation will be required to be maintained over an ultra-wide frequency range. Therefore, the bandwidth of such multi-band receiver architecture can hardly be extended with small circuit area and power consumption overheads.
To realize multi-band receiver achieving band selectivity across a wide frequency range with low power consumption and high inter-band blocker rejection, the scalable harmonic-selection technique is introduced in this work. The block diagram of a harmonic-selection receiver is shown in Fig. 2(c). By applying multi-phase LO to a mixer, the desired mixing component can be selected from the harmonics. Assuming that there are totally N mixing paths in the harmonic-selection receiver, and they are driven by N-phase LOs, the resulted mixing components could be represented with the following equation: In the equation, V IFkth represents the mixing component with the kth harmonic of LO. It can be found that only the Nth harmonic mixing component will be enhanced, while the other mixing components will be rejected by applying an N-phase LO with 2π/N phase interval. With this feature, any mixing components generated by kth (k < = N) order harmonic of the LO can be realized by applying an appropriate LO phase assignment to an k-path harmonic-selection mixer. It can be considered that the RF signal is mixed with an equivalent harmonic of the LO with the harmonic-selection mixer. Therefore, the operating frequency range of the receiver can be significantly extended without a wideband LO. The power consumption can be minimized with scalable RF frequency coverage. According to the equation, the harmonic-selection technique also provides rejections against the inter-band blockers generated by the unwanted harmonics. Collaborate with the LNA bandpass filtering and the Hartley receiver architecture; the proposed technique can realize high inter-band blocker rejection with suppressed system NF and minimized power consumption.
To realize the required 24-71-GHz RF coverage, three mixing paths with a tri-phase assignment are required for the proposed harmonic-selected technique, as shown in Fig. 3(a). For an RF amplifier, since the matching loss of the matching network tends to increase proportionally along with its bandwidth, a larger transistor size or more stages are required to compensate for the matching loss, which will significantly increase the power consumption. Therefore, it can be roughly assumed that the power consumption (P dc ) of the LO buffer is proportional to the LO bandwidth for a certain LO budget. An estimated P dc of LO buffer against LO bandwidth is shown in Fig. 3(b) based on the measured and reported P dc of this work and conventional work in Fig. 3(a) [21]. P dc of LO buffer could be up to 40 mW for conventional wideband LO path to support the required 24-71-GHz RF coverage. According to (1), only k mixing paths are required for the harmonic-selection mixer to select the desired kth harmonic mixing component. As shown in Fig. 3(c), theoretically, only one and two mixing paths are activated at fundamental-and second-harmonic-selected modes, separately. Therefore, lower power consumption can be realized on lower operating bands. On the contrary, the power consumption of conventional wideband LO is constant on all operating bands. Since the harmonic-selection technique depends on the nonlinearity of the mixer, the higher order mixing components tend to be weaker than the fundamental mixing component. However, as explained in (1), multi-phase mixing paths in the proposed harmonic-selection technique also result in a k-times CG, which can compensate for the loss of higher order harmonic mixing components effectively.

III. CIRCUIT IMPLEMENTATION
The block diagram of the proposed 24.25-71-GHz multiband phased-array receiver based on the harmonic-selection technique is shown in Fig. 4. Considering the required RF frequency coverage, a tri-phase LO is utilized in this work to drive the mixer. Thanks to the proposed harmonic-selection technique, the required LO frequency range is reduced to 16-26 GHz. The IF frequency is fixed at 8 GHz for better selectivity. Besides, the 8-GHz narrowband design can prevent IF from the influence of LO spurious and leakage. With the improved tolerance to LO leakage, the LO can be generated with a mature sub-6-GHz frequency synthesizer following by the frequency multiplier theoretically [24], [25], [26]. Totally two receiver channels are included in the proposed chip. Each receiver channel consists of a dual-mode multi-band LNA, a harmonic-selection mixer with a tri-phase LO generating circuit, and an LO phase shifter. LO phase shifting architecture is chosen for this work to realize precise beam steering across a wide frequency range [11], [27]. Each channel in this work is designed with 360 • phase-shifting coverage. The dual-mode multi-band LNA in this work can be configured to cover 24-44 or 44-71 GHz. Configurable Hartley receiver architecture is also adopted in the proposed receiver for sideband selection and image rejection. Since the phased array already provides sufficient spatial selectivity, the Hartley architecture in this work is designed for the situation where the desired and undesired signals arrive with the same phase. The quadrature LO is generated by the LO phase shifters in different receiver channels. A hybrid-type polyphase filter (PPF) is inserted into the IF part for summarizing the received signals in quadrature. Based on the system implementation, the detailed frequency plan of the proof-of-concept harmonic-selection receiver is shown in Fig. 5. There are totally four operating modes for the receiver. Frequencies configurations of are assigned to 28-GHz band, 39-GHz band, 47-GHz band, and 60-GHz band operations, respectively. When the receiver is in 28-GHz band operation, the harmonic-selection mixer will be configured in fundamental-selected mode, and the LNA will be configured to cover 24-44 GHz. The upper sideband is selected by the Hartley operation in this mode, while the lower sideband is rejected. In the 39-GHz band and 47-GHz band operations, the harmonic-selection mixer is in the second-harmonic-selected mode. Because the 39-GHz band and 47-GHz band operations are image frequencies with each other, they are distinguished by the sideband-selection function provided by the Hartley architecture. The LNA will be in the 24-44-GHz mode for the 39-GHz band operation and in the 44-71-GHz mode for the 47-GHz operation. Therefore, enough isolation could be provided between these two modes for a maximized IRR and a minimized system NF. In the 60-GHz band operation, the harmonic-selection mixer is in third-harmonic-selected mode, and the LNA is configured with the 44-71-GHz mode. The lower sideband is selected by the Hartley operation. Within the four modes mentioned above, the desired signal could be selected by the proposed receiver, while the unwanted inter-band blockers at harmonic frequencies and image frequencies could be rejected by the proposed harmonic-selection technique, the LNA bandpass filtering, and the Hartley receiver architecture. In actual application, non-ideal mismatches, such as the LO phase error and phase offset between desired and undesired signals, may affect the performance of the Hartley operation or harmonic-selection operation, which will be analyzed in the following part. However, the harmonicselection technique, LNA bandpass filtering and the Hartley operation always cooperate with each other to reject the undesired signals, which guarantees the receiver performance despite various mismatches.

A. Harmonic-Selection Mixer and Tri-Phase LO Generation
The proposed harmonic-selection technique greatly reduces the required LO frequency coverage while still realizing multiband down-conversion. The operation principle of the proposed down-conversion technique in the fundamental-selected mode, the second-harmonic-selected mode, and the thirdharmonic-selected mode is explained in Fig. 6. The proposed harmonic-selection mixer is driven by the configurable tri-phase LO generation circuits. It consists of three differential mixing paths. Each mixing path is independently driven by an LO signal with proper phase assignment according to the desired mixing component. By applying LOs with different phase assignments to the mixer, the resulted mixing components in each mixing path behave constructively for the desired component and destructively for the undesired harmonics. A differential-/common-mode selector based on the transformer is also implemented at the mixer output side. Additional signal filtering and better matching can be, therefore, provided.
In the fundamental-selected mode, only two mixing paths are activated. The LO path to the closed mixing path is also turned down for saving power. The differential-mode output is selected in this mode, and the proposed mixer now behaves as a conventional double-balanced mixer. The CG of the fundamental mixing component is enhanced by the double-balanced topology, while the unwanted second-and third-harmonic mixing components are rejected. The secondharmonic-selected mode keeps the same LO phase assignment as the fundamental-selected mode. Nonetheless, the mixer output is switched to a common-mode connection in this mode. Therefore, only the second-harmonic mixing component is retained. The differential fundamental-and third-harmonic mixing components are canceled. The balanced topology of  fundamental-and second-harmonic-selected modes can eliminate the LO leakage effectively. In the third-harmonic-selected mode, three mixing paths are fully activated and driven by tri-phase LOs with 120 • phase difference. The fundamentaland second-harmonic mixing components are canceled by the 120 • interval tri-phase LO, as analyzed in Section II. The output connection of the mixer is switched to differential mode to further reject the common-mode second-harmonic mixing component. Therefore, the third-harmonic mixing component is, finally, preserved at the output. In an actual circuit, the tri-phase LO may deviate from the desired phase due to the imperfect frequency characteristic of tri-phase LO generation and coupling between mixing paths. For fundamentaland second-harmonic-selected modes, mixing paths on two sides are selected to avoid coupling and keep the circuit symmetrical. The phase error will only slightly degrade CG with a balanced mixer topology. This issue could be more obvious in the third-harmonic-selected mode, as shown in Fig. 7(a). Nonetheless, the simulation result in a worst case in Fig. 7(b) shows that the harmonic-selection technique has a high tolerance to the phase error.
In this work, the compact tri-phase LO generation is designed with low power consumption. The detailed circuit schematic of the LO is shown in Fig. 9. After the LO phase shifter for beamforming, the LO signal is divided into three paths by a compact 1-to-3 Wilkinson divider, which ensures isolation between each path. The bulky λ/4 wavelength transmission lines in the Wilkinson divider are replaced by areaefficient CLC networks to significantly reduce the effective footprint [28], [29]. After that, a tri-phase phase shifter is employed in each path to realize the corresponding LO phase assignment for each harmonic-selection mode. As shown in Fig. 9(b), the proposed tri-phase phase shifter consists of a −60 • phase shifting path, a 60 • phase shifting path, and a 0 • through the path. The −60 • and 60 • phase shiftings are realized by a phase-lagging low-pass network and a phase-leading high-pass network, respectively, for a compact circuit area. A differential LO buffer with 180 • phase-flipping function, as shown in Fig. 9(c), is inserted after the tri-phase phase shifter [30], [31]. Together with the tri-phase phase shifter, the phase assignment for all the operating modes could be generated with a minimized circuit overhead, as shown in Fig. 6. Transformer matching with capacitors is utilized in the LO buffers for broadening the operating bandwidth. Since the harmonic mixing is realized by the non-linearity of the mixer rather than the harmonic distortion of the LO buffer, the LO buffer consumes the same power on all operating modes, which is only around 7 mW.
The measured CG and harmonic rejections of the proposed harmonic-selection mixer along with the tri-phase LO are presented in Fig. 8. The IF frequency is fixed at 8 GHz in this measurement. As shown in the figure, the flat CG characteristic is obtained in all the harmonic-selection modes. More than 20-dB rejections to the undesired harmonic components are also achieved in each operating band by the proposed mixer. The CG offset between each operating mode is less than 5 dB, which can be compensated by variable gain without causing an NF degradation. It should be noted that the rejections could be further improved by the LNA bandpass filtering and the Hartley receiver architecture.  are designed with bridged-T architecture, which realizes stable and precise phase shifting with small gain variation [32], [33], [34]. Nonetheless, the phase error is difficult to be eliminated in a wide LO frequency range. The simulated relative phase response of the STPS is shown in Fig. 10(a). The remaining phase error may cause LO I/Q mismatch and degrade the performance of the Hartley receiver operation. Therefore, the 22.5 • stage with CLC topology shown in Fig. 9(b) also plays the role of the fine-tuning stage by employing varactors [35]. As shown in Fig. 10(b), the fine-tuning realizes at least 22.5 • coverage, which is sufficient to compensate for the LO phase error.

B. Dual-Mode Multi-Band LNA
In recent years, although many attractive blocker rejection methods have been proposed, LNA is still the front line to undertake the impact of blockers. In conventional multiband receivers, a single LNA is designed with a wideband frequency response to cover all the desired bands. The power consumption of the LNA will scale against the bandwidth for maintaining enough gain and linearity. The inter-band blocker rejection of such a method is also limited due to the lack of bandpass filtering. In order to improve the power efficiency and inter-band blocker tolerance, a dual-mode multi-band LNA is proposed in this work, as shown in Fig. 11. The proposed LNA consists of two LNA elements, which are the lower band LNA covering 24-44 GHz and the upper band LNA covering 44-71 GHz. The frequency coverage of the LNA elements is selected considering the system image rejection and the LNA circuit performance. With the help of the configurable matching network shared between two operating mode, the proposed dual-mode multi-band LNA structure takes a good balance between chip area and circuit performance. The bandpass filtering of the LNA also leads to high isolation between the fundamental-and third-harmonic mixing components of the harmonic-selection mixer. The detailed compositions of the two LNA elements are also demonstrated in Fig. 11. The lower band LNA employs four cascode stages to achieve high gain while maintaining a low NF [36]. The input stage is source degenerated with an inductor coupled and integrated with the input series inductor [37]. A compact footprint is realized with improved matching and linearity. The upper band LNA introduces seven common-source (CS) stages to ensure enough power gain. Transmission-line-based interstage matching is chosen to improve the area efficiency.
Typically, the required passive values for the matching are inversely proportional to the operating frequency. Based on this characteristic, a reconfigurable transformer is employed at the input to combine the two LNA elements. As shown in Fig. 12, the upper band LNA is connected to the center tap of the primary coil. When the lower band LNA is operating, the input transformer forms a high-order wideband matching network with C gs from SW2 to cover 24-44 GHz. During the operation of the upper band LNA, the secondary transformer coil will be grounded. The upper band LNA will, hence, be matched with the approximate half-inductance value of the primary transformer coil. At the output side, the two

C. Hartley Receiver and Hybrid-Type PPF
The IRR performance of multi-band receivers is essential due to their wide frequency coverage. The proposed receiver utilizes the Hartley receiver architecture to improve image rejections. A 90 • -shifted LO is used at the adjacent channel, and −90 • is again applied in IF PPF to realize the Hartley operation. The insertion loss (IL) of passive multistage PPFs increases significantly with more stages, which degrades the system CG and NF. Therefore, a single-stage PPF is utilized in this work. Generally, the PPF topology can be classified into two types, as shown in Fig. 14(a) [38]. For Type-I PPF, the I and Q signals are orthogonal at all frequencies. However,  the amplitude of I and Q signals will be the same only at the pole frequency f C = 1/2πRC of the PPF. On the contrary, the amplitude of I and Q signals in Type-II PPF is identical at all frequencies but will be orthogonal only at the pole frequency f C . Typically, Type-II PPF is preferred in conventional designs since its IL is 3 dB theoretically better than Type-I topology. However, regarding the IRR degradation caused by PVT variations, Type-II PPF generally requires complicated and bulky phase calibration [16], [39], [40]. The Fig. 16.
Schematic of (a) proposed differential voltage detector for hybrid PPF calibration and (b) high-dynamic detector for IF power level detection.  corresponding calibration accuracy is usually limited, and the power consumption is usually high. On the contrary, the IRR of Type-I PPF can be easily calibrated by simple and high-accuracy magnitude detections. Therefore, this work introduces a hybrid-type PPF to achieve both accurate

IRR calibration and low IL
(2) As explained in (2) [38], [41], Type-I and Type-II PPFs have identical IRR with peak frequency located at f C = 1/2πRC when R and C values are the same. The hybrid-type PPF can be reconfigured between Type-I and Type-II topologies while maintaining the same R and C values. The operation principle of the hybrid-type PPF is detailedly explained in Fig. 14. The hybrid-type PPF will be first configured in Type-I mode for IRR calibration. An 8-GHz test-tone signal is an input from the IF output node, while the I and Q ports of the hybrid-type PPF are connected to a magnitude detector. The R value is tuned to calibrate the I/Q magnitude imbalance depending on the readout value of the detector. Since Type-I and Type-II PPFs share the same IRR peak frequency f C , the proposed PPF will keep the calibrated R value and directly switches to Type-II mode. Lower IL during normal operation could be, therefore, achieved, as shown in Fig. 14(c). f C of the PPF is steered by tuning R on of a triode-region transistor. With the help of analog-to-digital converter (ADC), RDAC, and serial peripheral interface (SPI) integrated into the digital block, the hybrid PPF calibration can operate automatically. The measured IRRs of the proposed PPF in both Type-I mode and Type-II mode are shown in Fig. 15(a) after calibration in Type-I mode. As demonstrated in the figure, the IRRs in Type-I and Type-II modes match with each other very well. As expected, Fig. 15(b) shows that the measured CG achieves a 2-dB improvement with the proposed hybrid-type PPF operating in Type-II mode.
The proposed hybrid-type PPF is calibrated with an on-chip differential detector, as shown in Fig. 16(a). The I/Q ports of the PPF share one magnitude detector to avoid mismatch. The differential detector senses the input voltage by an input transconductance stage followed by a current rectifier. The rectified current is then amplified and filtered to generate a dc voltage VOUT dc [42]. Another detector is applied at the IF output node to indicate the output power of the receiver, which is shown in Fig. 16(b). To extend the input dynamic range, multiple transconductance stages with bypass switches are introduced. Larger than 20-mV/dBm sensitivity can be achieved across a 40-dB signal power range in the simulation.
An IF VGA is inserted between before PPF and mixer to provide variable gain and isolation. The detailed circuit of the proposed phase-invariant IF VGA is shown in Fig. 17(a). The IF VGA is designed based on the current-steering topology with 3-bit coarse tuning and 10-bit fine-tuning [43], [44]. The IF selectivity can be improved by IF VGA with a fixed IF frequency at 8 GHz. A source degeneration inductor L s is coupled and integrated with the input series inductor L g , as shown in Fig. 17(a), to realize improved matching with compact area [37]. A transformer with capacitors at a center tap is utilized at the output of the VGA for providing matching with an improved common-mode rejection ratio (CMRR). Fig. 17(b) demonstrates the measured normalized variable gain of the proposed receiver in four operating modes. The IF frequency is fixed at 8 GHz in measurement. During the measurement, the proposed VGA realized a 9-dB gain tuning range with 5G standard compatible bandwidth.

IV. MEASUREMENT RESULTS
The proposed two-channel multi-band phased-array receiver is fabricated with a 65-nm CMOS process. Fig. 18 shows the micrograph of the proposed chip. The chip size is 3.2 mm × 1.4 mm, including the two-channel receiver element. Each element occupies 1.2-mm 2 core area while covering almost 50-GHz bandwidth. The single-path receiver characteristic is first on-wafer measured. Fig. 19(b) demonstrates the  As mentioned previously, the multi-band receiver suffers from inter-band blockers. This work utilizes the harmonicselection technique, LNA bandpass filtering, and the Hartley receiver architecture to improve the rejections to inter-band blockers. In this work, the worst blocker case happens when the blocker frequencies locate at the harmonic or image frequencies of the desired signals. In these conditions, the down-converted IF will be at the exactly same frequency as the desired signal, which cannot be removed by the IF bandpass filtering. In this work, the inter-band blockers are analyzed with four cases, which are at 28, 39, 47.2, and 60.1 GHz. The rejections to harmonics and images in the abovementioned four cases are first measured and shown in Table III(a). This work achieves better than 36-dB rejections against the blockers located at the harmonic and image frequencies. The constellations and EVMs are also measured with inter-band blockers. The measurement setup for each operating mode is explained in Fig. 20. The Keysight VXG signal generator M9384B is utilized to generate the OFDMA-mode desired and blocker signals in 256QAM and 16QAM, respectively. For signals higher than 44 GHz, an additional mixer is employed. The worst case blocker frequency settings mentioned previously are applied in each case for convincing results. The measured EVMs and constellations are shown in Table III(b). Without the blockers, the proposed receiver demonstrates EVMs of −33.5, −31.1, −31.8, and −29.3 dB at 28, 39, 47.2, and 60.1 GHz, respectively. With blockers on the same power level against desired signals, the measured EVMs are only slightly degraded to −33.3 dB at 28 GHz, −30.9 dB at 39 GHz, −31.6 dB at 47.2 GHz, and −28.5 dB at 60.1 GHz. The wideband modulated 256QAM signal is still supported with enough margin to meet the 5G NR standard. Table IV compares this work with other state-of-the-art multi-band receivers designed for 5G NR FR2 [17], [18], [20], [22]. Thanks to the proposed harmonic-selection technique, this work supports the 24.25-71-GHz operation while maintaining over 36-dB inter-band blocker rejection. Each channel of the proposed receiver only consumes 36, 32, 51, and 75 mW when operating at 28, 39, 47.2, and 60.1 GHz, respectively. The proposed receiver can support ultra-wideband operation with minimized power consumption and improved inter-band blocker rejections.

V. CONCLUSION
In this work, a two-channel multi-band phased-array receiver with a proposed harmonic-selection technique is introduced. The frequency coverage of 24.25-71 GHz makes the receiver compatible with all existing 5G NR FR2 bands and the potential 60-GHz band. Cooperating with the dualmode multi-band LNA and Hartley architecture, this work realizes rejections to inter-band blockers better than 57, 56, 50, and 36 dB at 28, 39, 47.2, and 60.1 GHz, respectively. As a result, the proposed receiver can support 400-MHz standard-compliant 5G NR modulated signals in 256QAM even regarding 0-dBc worst case inter-band blockers. The power consumptions per channel are only 36, 32, 51, and 75 mW at 28, 39, 47.2, and 60.1 GHz, respectively. The low-cost and energy-efficient multi-band phased-array receiver adapting to the evolving 5G NR standard with enhanced inter-band blocker rejections can be realized.