Subranging BJT-Based CMOS Temperature Sensor With a ±0.45 °C Inaccuracy (3σ) From −50 °C to 180 °C and a Resolution-FoM of 7.2 pJ·K² at 150 °C

This article presents a BJT-based CMOS temperature sensor with a wide sensing range from −50 °C to 180 °C. To effectively relax the sensor resolution requirement and conversion time over the entire temperature range to improve energy efficiency, we introduce a nonlinear subranging readout scheme together with double sampling to achieve dynamic reconfiguration of the sensor readout according to the ambient temperature. We further reduce the sensor power at high temperature by devoting the <inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-cancellation circuit only for BJT biasing while applying a temperature-independent bias current for the other sensor building blocks. Implemented in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS with four-wire connections and switch-leakage compensation based on small BJTs, the proposed sensor chip prototype achieves a high resolution-FoM of 7.2 pJ<inline-formula> <tex-math notation="LaTeX">$\cdot \text{K}^{{2}}$ </tex-math></inline-formula> at 150 °C, while featuring a small sensing error of ±0.45 °C under a 1.5-V supply.

superior sub-pJ·K 2 resolution-FoM [5] as well as high accuracy after one-point trim with polynomial curve fitting [6]. The recent self-calibration approach assisted by a thermal-diffusivity sensor further reduces the calibration cost [7]. However, resistor-based temperature sensors are highly dependent on the temperature dependency of on-chip resistors and may not be favorable in processes with only small TC resistors [8]. In contrast, owing to the stable thermal characteristics and good reproducibility of BJTs [9], BJT-based temperature sensors can satisfy the above design constraints and achieve good performance at high temperature (high-T) with one-point trim, simple digital processing, and good process scalability [10], [11], [12], [13].
For BJT-based sensors designed in bulk CMOS, the device nonlinearity and leakage can be the major performance killers at high-T and are traditionally addressed by using a larger bias current [10], or employing leakage reduction techniques [14], [15]. However, prior designs primarily focused on the sensor performance at room temperature (RT) [16]. Yet, their power consumption could increase rapidly to compensate for the increased noise and leakage current at high-T. This can severely degrade the overall energy efficiency and hinder their deployment in practical harsh environment scenarios [2].
This article presents a BJT-based temperature sensor targeting for a wide sensing range from −50 • C to 180 • C (expanded from [17]). The proposed subranging double-sampled readout scheme reconfigures the sensor dynamically according to the ambient temperature. This can reduce both the required sensor readout resolution and temperature conversion time, thus improving the sensor energy efficiency. Meanwhile, this design only devotes the β-cancellation circuit for BJT biasing while employing a reference current to bias the other sensor building blocks. Such an arrangement, together with clock-gated digital circuits using high-V th devices, can avoid sharp sensor power increase at high-T. The leakage-compensated sampling switches can also ensure accurate sensing at high-T without increasing the frontend power consumption.
This article is organized as follows. Section II presents the system-level sensor optimization. The sensor implementation and operation are presented in Section III. Section IV elaborates on the experimental results. Section V concludes. This

A. BJT and BJT Biasing
Identifying and minimizing error sources from BJTs are essential to ensure good sensing accuracy over a wide operating range. Fig. 1 shows the sensor core for generating the temperature-dependent signals V BE (i.e., V BE0 ) and V BE (i.e., V BE0 − V BE1 ) [9]. For low-power operation, the two pnp BJTs, Q 0 and Q 1 , carry the same emitter bias I e , while having an emitter area ratio of 1 : p. Therefore, and where V T is the thermal voltage, η is the BJT's nonideality factor, I s is its saturation current, β is its nominal forward current gain, and r q is its terminal resistance referred to the base. In (2), we assumed both Q 0 and Q 1 exhibit the same β through selecting an appropriate I e [18]. The temperature sensitivities of V BE and V BE are near-constant if I e I s holds [10]. However, this condition weakens at high-T due to the exponential increase of I s , leading to substantial nonlinearities in V BE and V BE . As indicated by (1) and (2), except for ensuring I e I s , adopting a pnp BJT with a small I s , a large β, and a small p can help to minimize the nonlinearity terms. Based on the simulation results in Fig. 2(a), this work employs a pnp BJT with a small emitter area of 2 μm × 2 μm, which enjoys a relatively larger β under the same bias current densities at high-T. An emitter bias current density from 1 to 200 nA/μm 2 can result in a negligible current dependence in β. Meanwhile, we adopted p = 8 considering the tradeoff between the temperature sensitivity and linearity of V BE . Under these design constraints, the sensing error introduced by r q , which is around 100 as specified in the device model, becomes negligible. As shown in Fig. 2(b), the overall sensing error of the adopted BJT due to signal nonlinearity is about 0.05 • C from −50 • C to 180 • C after a first-order fit.

B. Sensor Readout Selection
There are different methods to combine V BE and V BE to produce a digital representation of temperature, as depicted in Fig. 3(a). The classical way is to digitize the ratio [19]. This scheme is not flexible since the gain α, as determined by the process model, is typically built-in within the sensor readout. It also amplifies the noise power in V BE by α 2 during sampling. Another popular scheme is to digitize the ratio Y T = V BE /V BE with a two-step zoom ADC [20], whose output is a nonlinear function of temperature but can be handily linearized in the digital backend. However, this scheme should sample V BE in every clock cycle. Since V BE is small and often amplified during readout, its noise contribution is usually dominant. However, the noise contribution of V BE may be significant in low-power designs, as discussed below.
As shown in Fig. 1, the noise v nb associated with the BJT core bias V b (also see Fig. 10) appears in V BE0,1 as a common mode noise, which can be suppressed during V BE sampling but not when sampling V BE . Depending on the bias generator design, the noise added to V BE via V b could be significant as indicated in Fig. 4, which shows the simulated noise profile of V BE and V BE of the designed sensor frontend at RT (details in Section III-B). Although the noise contribution from V BE and V BE to the digitized output also depends on the readout configuration, especially the V BE gain (e.g., α in [19]), it is still beneficial if we can minimize the number of V BE sampling in one temperature conversion to reduce the total noise sampled from the sensor frontend, especially for lowpower high-resolution sensors. With this consideration, this work digitizes the ratio Z T = k · V BE /V BE as it does not sample V BE in every clock cycle, with k being a gain factor to accommodate for the readout dynamic range [11], [21]. k (set to be 3 or 6 in this work) is smaller than α (=16) in [19] or V BE /V BE max (=28) in the zoom ADC readout [20].
Considering from another perspective, these readouts have different requirements to achieve the same sensing resolution. As shown in Fig. 3(b), to achieve a target resolution of 15 m • C over a wide temperature range, compared to other schemes, digitizing Z T offers a gradually relaxed readout resolution requirement 1 at high-T when the system becomes noisier. This feature is preferred in our design, which aims to optimize the sensor performance at high-T. After conversion, we can linearize Z T by With a first-order fit of μ T , the digital representation (in • C) of the measured temperature is where A ≈ 600 and B ≈ -273 are constants, with their exact values derived via batch calibration. A higher-order fit of μ T can be applied when systematic nonlinearity exists [16].

C. Subranging Scheme
The main issue for digitizing Z T is its high readout resolution requirement at low temperatures (low-T) as observed in Fig. 3(b). By designing the sensor for the worst case, that is, 16-bit at −50 • C referenced V BE , the sensor can waste an excessively large power at high-T as only 13.5-bit is necessary for resolving the target temperature resolution at 180 • C. In this work, we employ a subranging scheme to achieve a high energy efficiency over the entire temperature range. As illustrated in Fig. 5(a), for temperatures below the transition temperature T r ∼ 100 • C, that is, the low-T subrange, we set the signal gain for V BE to 6 (i.e., k 1 ) to relax the system resolution requirement by 1 bit. For temperatures above T r , that is, the high-T subrange, the corresponding gain for V BE is set to 3 (i.e., k 2 ) to avoid overloading the readout. As observed in Fig. 5(b), this can relax the total ADC inputreferred 2 noise power requirement by 4× and 2.5× for the two subranges, respectively. Note that changing the gain k does not affect the temperature reading after linearization. Fig. 5(c) shows the simulated magnitude of Z T and μ T . With the selected k 1, 2 and T r , we can maintain Z T to be less than 0.8 for ensuring the stability of a second-order incremental ADC [23].
As presented in Fig. 5(d), the subrange control is achieved by checking the polarity of (8V BE −V BE ) before each conversion. For temperatures near the transition temperature, either k 1 or k 2 can be employed, thus noise and process induced variations of T r are highly tolerable. Applying more subranges is possible at the cost of increased control complexity.

D. Faster Conversion
For a low-power BJT-based temperature sensor, irrespective of the readout details, its frontend power is often determined by the bias generator's settling requirement (e.g., for dynamic error correction) and its BJT core biasing (e.g., usually larger than the current required for settling during V BE0,1 sampling) [9]. Therefore, for a given readout sampling frequency f s (e.g., 40 kHz in this design), energy consumed by the sensor frontend E frontend scales linearly with the number of clock cycles N in one temperature conversion, as illustrated in Fig. 6(a). In contrast, to achieve a target thermal-noise-limited resolution (e.g., 15-bit), energy consumed by the readout E A/D is nearly constant irrespective of N. This is because if N increases, the modulator's sampling capacitance, thus its power consumption will decrease proportionally (thermal noise averaging cycle ∝ N) [23].
Depending on the design choices, the power consumed by the sensor frontend can take up 30% [21], 57% [11], or even more than 70% [18] of the sensor's total power. Therefore, for a given f s and resolution target, it is beneficial if N can be minimized. In addition, the sensor's digital power could be significant at high-T (e.g., consuming 36% of the sensor's total power at 180 • C in our design); a smaller N can also reduce its energy consumed per temperature conversion.
In this work, we employ double-sampling to achieve a faster conversion. By sampling the input and feedback signals in both φ 1 and φ 2 , and with the quantizer evaluating twice per clock cycle, the number of clock cycles required for one temperature conversion can be halved without burning extra power or sacrificing the effective thermal noise averaging cycle [24], [25]. Meanwhile, we adopt a second-order modulator with a sinc 3 instead of the often adopted sinc 2 filter for output decimation [26]. It can reduce the required conversion cycle by ∼2×, thus halving the energy consumed by the sensor frontend and digital controller. Because the sinc 3 filter has a higher thermal noise penalty (∼1.6 compared with ∼1.3 of sinc 2 [27]) and N is halved, compared to that of using a sinc 2 , the readout sampling capacitance should be increased correspondingly (e.g., by ∼2.4× in this work). Yet, the energy savings from the sensor frontend and digital controller due to a ∼2× faster conversion can lead to a significant overall energy reduction (e.g., about 30 nJ per temperature conversion using sinc 3 in this work, compared to 48 nJ using sinc 2 ). This is especially true for low-power designs where the frontend and digital controller contribute to a significant portion of the overall sensor power consumption (e.g., [18]).
As shown in Fig. 5(a), the required system resolution is 15-bit after employing subranging. With the above readout arrangement, running the modulator for 160 clock cycles can handily suppress its quantization noise power to a negligible level (i.e., 102 dB SQNR, 10× below the target noise level), as depicted in Fig. 6(b). It is one-fourth of the cycles required by a typical modulator that only samples the input/feedback signal and operates the quantizer once per clock cycle.

E. One-Point Calibration
For BJT-based designs, one-point trim is typically necessary to correct the spread of V BE [9], and the trimmed output can be expressed as where is the actual sensor output to be calibrated, with σ k representing the spread of k. α is the sensor's trimming coefficient such that its trimmed output equals to the desired μ T 0 at the calibration temperature T 0 (e.g., RT, use k 1 ), with Unlike the V BE spread, σ k cannot be corrected by α.
To resolve this issue, [11] employed only one sampling capacitor with multiple integration cycles to achieve an accurate gain, but at the cost of reduced energy efficiency. To limit the sensing error caused by σ k to be below 0.1 • C, σ k should be within 0.05%. In our design, this gain accuracy is achievable with the adopted large sampling capacitor size (a few pF), together with local capacitance averaging and common-centroid layout. When needed, we can perform a second RT trim by applying known input voltages to the readout for deriving the actual gain On the other hand, if k 1 /k 2 deviates from the designed ratio (i.e., 2 in this work), applying the ideal k 1 and k 2 (i.e., 6 and 3) to (5) for the low-T and high-T subrange calibration, respectively, would cause a discontinuity in μ T _cal between the two subranges at T r . In other words, it will introduce a step temperature change at T r (e.g., about 0.15 • C with a 0.1% k 1 /k 2 ratio error). To address this issue, we perform one extra correction step by converting the same temperature (i.e., RT) twice with different gain settings (k 1,2 ). We can then extract the actual gain ratio k 1 /k 2 = Z T 0_k1 /Z T 0_k2 to be applied for the high-T subrange calibration, expressed as Therefore, even with subranging, we can still perform sensor calibration at RT with a comparable calibration cost to the existing BJT-based designs.

III. IMPLEMENTATION
The proposed sensor is shown in Fig. 7, which consists of a sensor frontend, a switched capacitor (SC) -ADC readout, a current reference generator, and a controller. We introduce the design considerations of the main building blocks as follows.

A. Sensor Current Reduction at High-T
In this design, instead of using a proportional-to-absolutetemperature (PTAT) current that can double the sensor's power consumption from −50 • C to 180 • C, we only use PTAT biasing for the BJT core, while employing a temperature-compensated reference current I REF in Fig. 8 to bias the rest of the building blocks. Similar to [28], we utilize the TC of resistor (TCR) to minimize the temperature dependency of I REF (∼86 nA at RT). The resistor R 1 of 65 k is implemented using p-poly resistor with an averaged negative TCR of −780 ppm/ • C, and R 2 of 220 k being an n-well resistor with an averaged positive TCR of 3860 ppm/ • C.
In addition, we implement all digital circuits with high-V th transistors to minimize the channel leakage current at high-T. As illustrated in Fig. 9, at 180 • C, the static leakage of an inverter and a C 2 MOS DFF [29] using high-V th devices are 18 and 7 times less than that of using standard-V th devices with the same transistor sizes, respectively. An even larger leakage can be observed for static DFFs in standard-V th devices (i.e., around 50 nA at 180 • C). Therefore, besides clock-gating, digital design with a high-V th device as performed in this design is crucial to reduce the sensor current at high-T.   cascode PMOS in the current mirror can ensure low-voltage operation, but at the expense of a degraded negative supply rail rejection at high frequency. The 94-dB dc-gain folded-cascode error amplifier A E consumes 0.45 μA, with its low-frequency noise being upmodulated by chopping. Mismatch of the current mirrors and BJT pair are mitigated by dynamic element matching (DEM) [13]. Four-wire connections at the BJT outputs can prevent accuracy degradation in V BE0,1 due to the varying voltage drop across the DEM switches.

B. Sensor Frontend
To reduce the noise bandwidth and power consumption of the β-cancellation bias circuit, its closed-loop −3 dB bandwidth is designed to be 58 kHz at RT. As the readout samples V BE0,1 at f s = 40 kHz, the settling of V b , thus V BE0,1 , are slightly incomplete after each switch operation in the bias. In this design, we apply a relatively slow f cp = f s /36, which is above the simulated flicker noise corner frequency of the bias circuit over the target temperature range. Therefore, the settling error in V b appears once every 18 clock cycles and becomes negligible after averaging. For example, the sensing  Fig. 10. Chopping and DEM are performed within the nonoverlapping region of the two sampling clock phases to maintain the fidelity of V BE0,1 during sampling. Note that the intermodulation between the chopping and DEM residues with the bitstream via the feedback DAC can cause quantization noise folding, thus degrading the sensor resolution [19]. In this design, since we employed a slow chopping and DEM with minimized V BE0,1 transient spikes, a simple fixed frequency chopping and DEM scheme is adopted.

C. Switch Body-Leakage Compensation
Regarding the switches employed for dynamic error corrections in the frontend, their maximum input and output voltage difference is V BE , which is less than 100 mV. Therefore, their OFF-state channel leakages are negligible, and simple transmission gates (TGs) are sufficient [14]. However, the body leakage of a transistor increases exponentially with temperature, effectively introducing nonlinearity to V BE0,1 at high-T. As depicted in Fig. 11, the body-leakage current of NMOS and PMOS flow in the opposite direction in a TG. Based on the adopted process model, the diffusion area of PMOS is designed to be 3.6 times that of the NMOS to achieve a first-order body-leakage compensation.
For the extensively employed analog multiplexer for DEM in Fig. 12(a), the transistor source/drain diffusions are shared to further reduce the leakage current I leak at the output node. Based on the measurement results in Fig. 12(b), I leak is a few pA at 120 • C, reaches 630 pA at 180 • C, and can be reduced to 180 pA with body-leakage compensation. This can suppress the switch leakage-induced nonlinearity error in the frontend to be less than 0.1 • C. We can expect an even lower leakage by further fine-tuning (slightly increasing) the PMOS diffusion area. The effectiveness of this compensation scheme varies with the diffusion doping concentrations, which typically exhibits a process spread of ±15% in modern processes [9].   its good tradeoff between quantization noise suppression, input range, and design complexity [23]. Fig. 13(a) shows its topology during temperature conversion. The gain for V BE is selected by sel − k at the beginning of each conversion. With a supply of 1.5 V, the first integrator gain α 1 is designed to be 1/3. Therefore, the maximum outputs of the two integrators are about ±0.35·V BE , which can be satisfied by the designed current-reuse opamp. As the ADC input-referred noise from the integrator is ∝ (1 + 1/α 1 ) 2 , it is not helpful to further reduce α 1 . Effectively, the integrators and the quantizer operate at 2· f s , producing two bs output bits per clock cycle.  Fig. 13(b) shows the ADC configuration during subrange decision. With the second integrator disabled, V BE is double-sampled with a gain of 4, and V BE is sampled once per clock cycle. After running the ADC for n sub clock cycles, the first integrator output is n sub ·(8V BE −V BE ), whose polarity is checked by the comparator to generate sel − k [see Fig. 5(d)]. In this work, we set n sub = 6 to effectively suppress the variation of T r induced by circuit noise and comparator offset.
2) Implementation and Operation: Fig. 14 presents the ADC schematic and its simplified timing diagram. It consists of two sampling paths C s1.1 and C s1.2 , but with only one fully-floating feedback DAC C fb to avoid quantization noise folding caused by DAC mismatch [25]. To implement k 1, 2 and α 1 , we configure C s1.1,s1.2 /C fb /C I1 to be 6C u /1C u /3C u in the low-T subrange, and to be 12C u /4C u /12C u in the high-T subrange, respectively. As shown in Fig. 5(b), the worst-case design targets are at −50 • C and 100 • C for the two subranges, respectively. In this work, the unit capacitance C u is 260 fF to keep the total ADC input-referred noise from the frontend and readout below the target levels [30], [31].
Mismatch between C s1.1,s1.2 and C fb directly affects the accuracy of k 1,2 . Applying the conventional DEM approach can result in a total of 336 switches for the 56 unit capacitors. As the k 1 /k 2 ratio can be derived at RT, this design just performs a local averaging at the low-T subrange by involving all the unit capacitors of C s1.1,s1.2,fb within one temperature conversion. For example, as shown in Fig. 14(a), only 6C u is used for V BE sampling at low-T. The other unused 6C u is connected to V ad+ (to V ad-for the other capacitor in the C s1.1 pair) to reduce the frontend noise bandwidth. Their roles are exchanged periodically during conversion (i.e., at f s /36). The same applies to C s1.2 . This can increase the effective capacitor area for matching, thus minimizing the spread of k 1 and the layout-dependent k 1 /k 2 ratio error.
The local averaging of C fb is bs-controlled to ensure its unit capacitors are equally involved for feedback. Specifically, the positions of the four unit capacitors in the DAC are shifted once for every eight ones in bs. That is, its switching frequency depends on the density of "ones" in bs, which is temperaturedependent. As a result, this can introduce a frequency-varying noise tone to the output after intermodulation, especially with the chopping residue at f s /36.
The first integrator consists of two ∼80-dB dc-gain chopped current-reuse opamp slices A 1.1,1.2 , as shown in Fig. 14(c), with only one enabled in each subrange. A 1.1,1.2 have different transistor sizing to maximize their respective output swing for the two subranges, while consuming 0.8 μA and 1.65 μA, respectively. Despite the reduced settling requirement, A 1.2 designed for the high-T subrange burns more power due to the 2× larger C s1.1,s1.2 and degraded transistor g m /I d efficiency at high-T. The second integrator and summer, with much-relaxed gain, noise, and driving requirements, draw 170 nA each.
To avoid affecting the floating input V i1+, i1-of the first integrator (i.e., equal to the common-mode voltage V DD /2 after reset), the varying common-mode voltages of V BE and V BE are canceled by shorting the respective sampling plates of C s1.1/s1.2/fb during charge redistribution. Switches employed in the readout are analog T-switches with body leakage compensation to minimize both their channel and body leakages, thus minimizing their influence on V BE0, 1 during sampling [11], [14]. The use of low-leakage switches is also essential to minimize the drift of V i1+,i1-at high-T. Fig. 15(a) depicts how a single DAC can achieve feedback at a speed of 2· f s . After reset, it stays at state-A. When bs = 1, it switches to state-B, thus sampling −V BE for feedback. Next, if bs = 0, the DAC will stay at state-B, or switch back to state-A for feedback otherwise. The DAC control signals S fbp/n,cm,a,b are triggered by one of the falling edges of φ 1d,1dd,2d,2dd depending on the current DAC state and clock  phase, as detailed in Fig. 15(b). For example, if the DAC is currently in state-B with the clock in φ 1 , we can achieve feedback by turning off S b,cm at the falling edge of φ 1d , and then turning on S a,fbp at the falling edge of φ 1dd . Note that the DAC does not perform a "sampling" operation on V BE when it switches from state-B to state-A. In this case, the noise in V BE is not sampled by the first integrator, meaning that half of the feedback operations are free from the noise in V BE . This is another advantage of employing a fully floating DAC in a double-sampled ADC.
In this design, one temperature conversion takes 333 clock cycles in total. System-level chopping, once per conversion via f sys , can suppress the residual offset and 1/ f noise by inverting the input polarity and averaging the decimated output.

IV. EXPERIMENTAL RESULTS
Fabricated in a standard 0.18-μm CMOS process, the sensor prototype occupies an area of 0.42 mm 2 . Fig. 16 shows the chip micrograph. The sinc 3 filter is implemented in FPGA for testing flexibility. However, it can be handily integrated on-chip. With a 1.5-V supply, the simulated average current of our customized sinc 3 filter is 55 nA running at the data rate of 80 kHz at RT. Clocked at 40 kHz, the sensor draws 2.5 μA at RT (230 nA from the digital controller), and 3.8 μA at 150 • C with a 1.5-V supply. As observed in Fig. 17, the sensor current further increases to 5.7 μA at 180 • C, with 2.08 μA consumed by the digital controller even after employing clock-gating and high-V th devices. From 1.5 to 2 V, the measured dc supply sensitivity is 0.44 • C/V and 0.15 • C/V at RT and 180 • C, respectively, as limited by the reduced gain of the designed error amplifier in the frontend when supply voltage increases.     18 shows the measured power spectrum of the output bitstream at RT. Periodic noise tones caused by the dynamic error correction techniques are noticeable and can be suppressed by the digital filter. The noise tone introduced by the local capacitance averaging (active only in the low-T subrange) of C fb is also visible, with its amplitude staying almost constant across temperature (frequency varies with temperature). The 1/ f noise corner is suppressed to <150 mHz.
As shown in Fig. 19, with dynamic error correction enabled, the achieved kT/C-limited resolution is 17.6 m • C rms under a conversion time of 8.325 ms at RT, corresponding to a resolution-FoM of 9.7 pJ·K 2 . The measured resolution at  150 • C and 180 • C is 12.3 m • C and 13.5 m • C, respectively. As a result, by exploiting a nonlinear readout with subranging, double sampling, and constant current biasing techniques, this work demonstrates a state-of-the-art resolution-FoM of 7.2 pJ·K 2 at 150 • C. The sensor resolution degrades to ∼25 m • C at T r mainly due to the residual step change after k 1 /k 2 ratio error correction (see Fig. 22). Using a separate comparator with hysteresis for subrange decision can avoid this resolution loss, while at the cost of hardware and control overhead.
To investigate the subranging operation, we performed a slow temperature ramp test near T r . Fig. 20 shows the measured responses from 25 untrimmed samples. The transition between k 1 ↔ k 2 is quite smooth. The transition temperatures, which lie between 96 • C and 105 • C (3σ ), are also consistent during ramp up and ramp down.
We measure the k 1 /k 2 ratio error for a batch of 25 samples at RT to perform gain calibration for the two subranges. As shown in Fig. 21, this error is 0.103% and 0.06% without and with local capacitance averaging, respectively. This gain accuracy is a result of using a relatively large capacitor, dedicated layout matching, and the application of the local averaging technique. Fig. 22 shows the measured discontinuity between the two subranges due to k 1 /k 2 ratio error, which can be alleviated using k 1 /k 2 ratio correction at RT (Section II-E).
To evaluate the sensor accuracy, we characterize these 25 samples from −50 • C to 180 • C in a climate chamber. After batch calibration, the constants required in (3) and (4) are derived to be α = 11.455, A = 650.23, and B = −286.63.  As observed in Fig. 23, the untrimmed inaccuracy is ±1.8 • C (3σ ), which could be larger if more samples from different wafers are measured. With one-point trim at RT, the sensor inaccuracy is ±0.5 • C (3σ ) as shown in Fig. 23 (middle). After the k 1 /k 2 ratio correction, the achieved inaccuracy further improves to ±0.45 • C (3σ ), ultimately limited by the absolute precision of k 1 and the residual spread of V BE .
The designed sensor can operate at a measured temperature of up to ∼205 • C, mainly limited by the maximum stable input range of the second-order modulator. Considering the lifetime and robustness of bulk CMOS, we only characterize the sensor up to 180 • C. Table I benchmarks this work with state-of-the-art energy-efficient temperature sensors. This work achieves the lowest power consumption with a similar resolution at RT compared to [10], [11], and [20]. Among the designs with an extended sensing range, this work in bulk CMOS achieves a 6-to-10× higher energy efficiency than prior works [10], [11] with a comparable sensing range, resolution, and trimming effort (except for the resistor-based one [5]).

V. CONCLUSION
This article presents a low-power (3.8 μW at RT) BJTbased temperature sensor optimized for a wide sensing range from −50 • C to 180 • C. This sensor can achieve high full-range energy efficiency by exploiting subranging, doublesampling, constant current biasing, and nonlinear readout techniques, especially at high-T. Measurement results show a state-of-the-art resolution-FoM of 9.7 pJ·K 2 at RT and 7.2 pJ·K 2 at 150 • C. The switch body-leakage compensation scheme can maximally maintain the signal linearity at high-T, which enables a process-spread-limited sensing inaccuracy of ±0.45 • C (3σ ) with 25 measured samples.