A Single-Source Switched-Capacitor-Based Step-Up Multilevel Inverter With Reduced Components

—Switched-capacitor-based multilevel inverters (SC MLIs) have received a great deal of interest that reduces the dc

in generating a sinusoidallike output using the combination of switches and dc sources. Diodes and capacitors are the additional components used in the MLI to strengthen structural flexibility. MLIs are used in different applications that include photovoltaic (PV) systems, electric vehicles, STATCOM, traction drives, high-frequency power distribution, etc. [5]- [7] to enhance the power quality, efficiency, and reliability. Popular MLI topologies are the neutral-point clamped (NMLI), flying-capacitor MLI (FMLI), and cascaded H-bridge MLI (CMLI). Both the NMLI and FMLI are subjected to voltage balancing problems and collapsing of the whole module due to the series connection of switches [6], [8]. CMLI, on the other hand omits the requirement of additional clamping diodes/capacitors. However, the requirement of large number of semiconductor devices remains a concern in these MLIs for generating higher voltage levels at the output. Based on the requirement and application, CMLI can be operated using equal (symmetrical), unequal (asymmetrical), and varying dc sources [9], [10]. Symmetrical MLIs have simpler control while the asymmetrical structures can increase the voltage levels using less number of dc sources. The CMLI structure in [5] is equipped with capacitors in one of the modules to reduce the number of dc sources. Even though this circuit creates five levels at the output, the boosting factor (ratio of the output voltage to input voltage) is still one. The voltage boosting is elemental in PV systems to match the output voltage with the grid/load requirement. Several structural modifications have been done in recent years to reduce the number of switches, dc sources, and control complexity [7], [11]. These structures can be broadly classified into two types, i.e., reduced source switched-capacitor (SC)based boost type topologies and multi-dc nonboosting MLIs. The switched-source and switched-diode MLIs without the inherent boosting feature are esteemed as the nonboosting type MLIs. Toward an attempt to reduce the number of dc sources, structures are developed in [12] and [13]. The input voltage is equally distributed among the capacitors, which appear across the load and consequently lack the ability to boost the output. The circuit proposed in [14]- [16] for the renewable energy application uses series diodes in the conduction path. Thus, their operation in highly inductive loads is unfeasible. However, the voltage level enhancement integrating a floating capacitor is an additional advantage of the circuit proposed in [14]. An additional switch in [15] can eliminate the voltage spike appearing due to the inductive loads only in the first voltage step. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ The MLI presented in [17] is suitable for PV systems. However, the circuit requires multiple input sources identical to the conventional CMLI. The above-discussed structures embody a back-end H-bridge for generating the negative levels. Excluding the full bridge, potential nonboosting structures are disclosed in [18]- [20], which reduce the voltage stress significantly.
Apart from this, significant research interest is growing in recent years to develop SC MLIs with inherent boosting ability. Voltage balancing of SCs without auxiliary sensors and voltage boosting without additional inductor/transformers makes the SC MLIs suitable for the PV applications and high-frequency ac power distribution [8], [21]- [23]. The MLI topologies presented in [24]- [26] use the same basic unit to generate high output voltage levels using reduced number of components. The basic unit consisting of one dc source and a capacitor can create a two-step twofold boosted output. The charging of the capacitor in parallel and discharging in series with the source enables self-voltage balancing. Single-phase extension of these circuits requires more number of dc sources. On the other hand, this offers an opportunity to increase the voltage levels (17-level, 25level, 49-level, 81-level) by operating the MLI in symmetrical as well as asymmetrical modes. A novel basic module proposed in [27] synthesizes nine-level twofold boost output using a single dc source. However, the extended version of this structure requires multiple dc sources. SC MLI introduced in [28] requires a number of series-connected dc sources to obtain the desired output. The basic module of the disclosed structure in [29] can produce threefold three-step output. However, the switch count and the number of dc sources increase when high-quality voltage is intended to be produced at the output.
Most recent research also involves the design of SC MLIs with single input even in the extended forms. Charging spike in SCs is addressed in [23] by developing such MLI with a quasi-resonant front-end structure integrated with a back-end full bridge. All the capacitors are equally charged and the input voltage is divided among the capacitors. Consequently, this topology lacks in boosting the voltage. The MLI circuits proposed in [30] and [31] reduce the voltage stress satisfyingly at the cost of a large number of circuit components. Research effort is also made in [32] to develop a single-dc hybrid NMLI-based structure to reduce the stress on the switches while generating 7-level, 9-level, and 11-level output. However, the voltage gain in 11-level inverter is limited to 2.5 times the input voltage. Recently configured MLIs in [22], [33], and [34] attain high voltage gain (six times, four times, and three times) using lower number of components. Conventional H-bridge is not required in these circuits to generate the ac voltage output. Including further extension to the nine-level circuit proposed in [22] toward voltage quality improvement using a lower number of components, an improved SC MLI is proposed in this work with the following prominent features.
1) Single dc source is required to generate a 17-level output.
2) Only 12 switches and three capacitors are used in the circuit.
3) The capacitor voltages are self-balanced without auxiliary sensors/closed-loop controller. 4) Four times boosting ability of the circuit (V o = 4V in ). 5) More than 50% of switches operate at a low frequency; as a result, switching loss is reduced. 6) The proposed circuit can adequately operate under any loading power factor (PF). The next section introduces the proposed topology as well as the capacitor sizing and self-balancing mechanism. The power loss analysis is discussed thoroughly in Section III. A comparison with the recent-art MLIs in Section IV confirms the structural advancement. Followed by a detailed discussion on the modulation scheme in Section V, Sections VI and VII present extensive simulation and experimental investigation, respectively, to validate the workability of the 17-level SC MLI. Concluding remarks are provided in Section VII.

II. SC MLI TOPOLOGY AND ITS OPERATIONAL PRINCIPLES
The proposed 17-level SC MLI circuit is shown in Fig. 1. The proposed circuit consists of 12 switches (S 1 -S 12 ), three capacitors (C 1 -C 3 ), two diodes (D 1 and D 2 ), and a single dc power supply (V in ). All the switches have an antiparallel diode connected across it. The circuit produces a 17-level quadruple boost output (0, ±0.5V in , ±1V in , ±1.5V in , …, ±4V in ) without using an H-bridge for changing the polarity. The switch pairs S 1 − S 2 and S 11 − S 12 are complementary, thus reduces the control complexity. The switches S 5 -S 10 operate in fundamental frequency and switch pair S 3 − S 4 operates at lower frequency, which results in low switching losses. In addition, the voltage stress across each switch in Fig. 1 implies that only three switches S 8 -S 10 withstand peak load voltage stress. The ratio of voltage across the capacitors C 1 , C 2 , and C 3 (V C1 :V C2 :V C3 ) is naturally maintained at 1:2:0.5 in the steady state. To verify the inherent balancing of the capacitors, the operation of the 17-level SC MLI is analyzed hereafter.
In the positive half-cycle of the output voltage, the first voltage step (+0.5V in ) is produced by discharging only the capacitor C 3 . The second voltage step (+V in ) is produced by including the source voltage in the load current path and bypassing the capacitor C 3 . During this, the diode D 1 is in forward conduction and the voltage across the capacitor C 1 is clamped to V in by turning ON the switch S 1 . By additionally turning ON the switch S 11 , the capacitor C 3 voltage is again added with the input voltage and thus, +1.5V in is obtained at the load. In the next level (+2V in ), the capacitor C 1 discharges to the load in series with V in by turning ON switch S 2 and C 2 is charged during this instant by triggering the switch S 4 . The diode D 2 is connected  to avoid unwanted discharging of the capacitor C 2 . The voltage steps +2.5V in and +3.5V in are obtained by discharging the capacitor C 3 as mentioned earlier. Discharging of C 2 in series with the source produces +3V in at the output and the load voltage becomes +4V in when both the capacitors (C 1 and C 2 ) discharge in series with the source. In the negative half-cycle, the voltage steps −V in , −2V in , −3V in , and −4V in are produced similarly by turning ON the switches (S 8 , S 10 , S 12 ) instead of the switches (S 7 , S 9 , S 11 ). The capacitor C 3 is charged during the intermediate voltage levels −0.5V in , −1.5V in , −2.5V in , and −3.5V in . It is also worth noting that there always exists a path for the reverse flow of current, which facilitates successful operation of the proposed circuit under different load PF. Table I presents the switching states to synthesize the 17-level output with any loading PF and the output waveform of the proposed SC MLI with capacitor charging-discharging pattern is shown in Fig. 2(a). Fig. 2(b) shows that the capacitor C 1 charges in parallel with the dc source to V in and discharges in series with the source. The capacitor C 2 is charged in parallel with V in + V C1 and discharges in series the accumulated energy (2V in ) to the load, as depicted in Fig. 2(c). The capacitor C 3 is discharged in the whole positive half-cycle and charged symmetrically in the negative half-cycle, thus maintaining 0.5V in voltage across it.

A. Steady-State SC Analysis
Fig. 2(a) implies that the overall charging time of the capacitors is significantly lower than the total output voltage duration, attesting quick recovery of the capacitor voltages after the discharging period. The low parasitic resistance path and adequate charging instant further warrant retaining the desired capacitor voltage. To select the suitable capacitance, different factors, i.e., the largest discharging period (LDP) duration of the capacitors (C 1 and C 2 ), total discharging time in the whole positive half cycle (C 3 ), nominal frequency, lower voltage ripple, and type of loading, are considered. Assuming equal duration for all the voltage steps, the discharging amount of the capacitors C 1 -C 3 can be expressed as in (1)-(3) in the following, considering ϕ as the lagging angle between the load current (I o ) and fundamental voltage where the peak fundamental load current is I omax : Further, based on the fundamental frequency switching output voltage shown in Fig. 2(a), one half-cycle (T/2) can be divided into 16 time steps (t 1t 16 ) and therewith, t 1 , t 2 , t 5 , and t 7 (in s) are expressed in (5) using (4) as follows [29]: where N s is the number of voltage steps and N l is the number of levels in the output.
The corresponding voltage ripple (ΔV rC ) is expressed in (6) and capacitance is given in (7), as follows, considering k% voltage ripple in the capacitors: . (7) Applying (1), (2), (3), and (5), the capacitance is finally expressed as Using the series-parallel charge balancing principle and with the selected values given in (8) and (9) considering k% of voltage ripple, the capacitors C 1 and C 2 naturally maintain the voltage in a 1:2 ratio. However, capacitor C 3 symmetrically discharges and charges in the positive and negative half-cycles, respectively. Thereby, the self-balancing nature of C 3 can also be verified considering any intermediate voltage steps. For instance, consider the equivalent circuit shown in Fig. 3 for the synthesis of ±2.5V in output voltage. The net charge (ΔQ C3 ) is zero, which can be expressed as follows: where I C3 is the current flowing through the capacitor C 3 . Assuming the net impedance Z, the following expressions are derived from the equivalent circuit: Using (12) and (13), T and hence, V C3 = 0.5V in at the steady state.
The above deduction demonstrates the inherent voltage balancing and selection process of suitable capacitance in the proposed SC MLI. Considering about 5%-7% of voltage ripple, the proposed circuit is developed and examined further.

III. POWER LOSS EVALUATION FOR THE PROPOSED CIRCUIT
Switching loss (P sl ), ripple loss (P rl ), and conduction loss (P cl ) are the three major losses associated with the SC boost type MLIs [23], [29], [31]. These losses are evaluated in the following sections for the proposed 17-level MLI.

A. Switching Loss
The time delay between the transitions of a switching state produces switching power loss (P sl ). The blocking voltage (V B ) across a semiconductor switch during its OFF-state charges the built-in parasitic capacitor (C p ) linearly. Further, C p discharges from the magnitude V B to zero during the ON-state of the switch. Therefore, the energy loss (E sl ) by a semiconductor switch for one transition state can be evaluated using (14). Thereby the switching power loss during the switching actions can be calculated using (15), as follows: As can be noted from Fig. 1, the switches S 5 -S 10 block sum-total voltage stress of 18V in and operate in a fundamental frequency (considering purely resistive loading). Thus, considering f s and f o as the switching and fundamental frequencies,  (15) can be further simplified as follows:

B. Ripple Loss
Internal resistances of the capacitor and semiconductor devices that are in the charging path of capacitors (C) generate ripple loss in the SC MLI. The voltage difference (ΔV c ) between the actual and desired voltage of the capacitor is the key influencing parameter of the ripple energy loss (E rl ) that is evaluated in terms of the charging time (t c ) and charging current (I c ) From (17) and (18), the ripple power loss (P rl ) can be calculated by (19). It can be observed that the larger value of the capacitance can minimize P rl . However, a tradeoff is vital between the sizing and the ripple loss due to capacitors

C. Conduction Loss
The loss incorporated by the parasitic elements of the conducting devices in the load current path results in the conduction loss (P cl ). Fig. 4 shows the generalized equivalent circuit for the proposed MLI for synthesizing any voltage level. Therein, the output current expression (I o ) is given by where m i is the modulation index, which is the ratio of reference voltage (desired value) to the maximum obtainable fundamental voltage and Z l is the load impedance. The conduction loss can be evaluated by considering the duration of each voltage level. For instance, the time duration (t 1 -t 2 ) in Fig. 2(a) represents the voltage level 0.5V in . Consequently, the energy loss is expressed in (21), considering the ON-state switch resistance (R s ), the internal resistance of the capacitor (R c ), and forward voltage drop of the diode (V D ) The diode voltage drop is not included in (21) as it is in reverse bias during 0.5V in . Consequently, the total conduction loss of the proposed MLI considering all the voltage levels is Taking into account the losses derived in (16), (19), and (22), the power losses and overall efficiency of the proposed MLI are evaluated in Section VI using η = output power output power + P sl + P rl + P cl .

IV. COMPARATIVE EVALUATION
To assess the advantages of the proposed SC MLI, a comparison is carried out in Table II with recently developed 17-level MLI topologies based on different parameters and taking into account symmetrical configurations. As stated earlier, the compared topologies are categorized into two broad categories. The switched-dc or switched-diode-based circuits basically consist of multiple dc sources and do not possess the boosting ability. The SC-based topologies reduce the source count and feature the boosting ability. A number of capacitors and switches are used in such circuits to produce a high-quality output voltage. However, the proposed circuit aims at reducing the number of components to produce a 17-level output.
Except the MLI proposed in [23], the required number of dc sources (N dc ) in all the nonboosting structures is more than one. Most of the SC MLIs also require multiple input sources when extended to create 17-level output, unlike the proposed MLI. In view of the least number of switches (N sw ) and drivers (N dr ), the proposed circuit ranks first among other SC MLIs. The MLI disclosed in [14] involves fewer switches and drivers but at the cost of large number of dc sources. The single-dc SC MLIs [30] and [31] do not require discrete diodes (N dd ), but involve a large number of switches. On the contrary, the proposed 17-level topology uses only two diodes. Although the use of capacitors supports voltage boosting, the inrush current increases with increase in number of capacitors. Lower number of capacitors (N cap ) in the proposed circuit limits the inrush current and increases the reliability. More number of switches in the conducting path increases the power loss. The proposed MLI is also superior among all the MLI topologies on account of maximum number of switches in the conduction (N ms ) for 17-level operation.
Total standing voltage (TSV) and maximum standing voltage (MSV) are further evaluated for MLI topologies. TSV is calculated taking into account voltage stress across all the switches. The proposed MLI reduces the TSV to a great extent as the conventional full bridge is avoided for producing ac output.  The MLIs proposed in [14] and [31] have the minimum TSV. However, the former requires almost double the number of switches than the proposed MLI and the latter is a multi-dc topology that lacks the boosting ability. Proposed MLI has a quadruple boosting gain using minimum number of switches. Besides, cost factor (C f ) is chosen as a parameter to establish the design superiority, which is defined as (24) C f is evaluated considering different values of the weightage coefficient δ (low for more weightage to the number of components and high for more weightage to the TSV). The proposed MLI has the least C f among the other MLIs under both the conditions (δ = 0.5 and 1.5). Hence, the proposed MLI is a suitable alternative to the recently developed MLIs for obtaining high-quality output using least switch count.

V. MODULATION SCHEME
Fundamental switching control and high-frequency switching control are the two main categories of pulsewidth modulation (PWM) control schemes generally employed to verify the MLI working. Selective harmonic elimination switching control (SSC) is one of the former category of control schemes which aggressively eliminates the targeted lower order dominant harmonics and thereby maintains the highest quality of output waveforms [9], [11], [14], [16]. The fundamental component of staircase output voltage waveform in terms of Fourier series equations can be expressed as follows, which is valid for any single-phase MLI: Here, α p (proportional to t i ), n, and V d are the symbolic representation of switching angles, order of harmonics, and nominal value of the dc voltage, respectively. Further, p is directly associated with the number of voltage levels (N l ) as For any voltage level, the switching angle values can be determined within the modulation index (m i ) range of [0, 1] to eliminate the targeted lower order harmonics from the system, and thus, it can be regarded as the key control parameter. The expression of m i in terms of the fundamental and nominal dc voltage is given as follows: The proposed MLI is designed to output a 17-level staircase voltage waveform. Considering the expressions (25) and (27), the associated nonlinear equations for the MLI are given in (28) with the target to eliminate the 3rd to 15th order harmonics. To extract the optimal solutions (α p ), particle swarm optimization algorithm (PSO) is employed, taking into account the angle constraint in (29) and fitness function given in [16] ⎧ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎩ cos α 1 + · · · + cos α 8 = 8m i cos 3α 1 + · · · + cos 3α 8 = 0 . . . cos 15α 1 + · · · + cos 15α 8 = 0 Moreover, the performance of the optimization process for the proposed MLI can be verified from Fig. 5. Corresponding to the minimum value of the fitness function (i.e., in the range 0.9-0.94), switching angles are selected to verify the operation of the proposed circuit. The figure also implies that the total harmonic distortion (THD) level decreases with the increase in m i and also the fundamental value is retained at the desired level even under a lower m i value. This is one of the dominant features of the SSC technique and thus, the number of levels in the output voltage and current does not reduce with the decrease in m i although an increase in THD can be expected in such a scenario. Besides the optimum values of the switching angles chosen corresponding to the minimum fitness function value, a lower m i value of 0.3 is taken as reference to verify the SSC principle in the next section.
The fundamental frequency SSC scheme maintains the required fundamental value of the output and thus cannot regulate the ac output (or the voltage gain), which is generally required in different applications of an MLI. In such a case, the phasedisposition PWM control (PPC) scheme [14], [19], [33] may be employed. In the PPC scheme, multiple carrier signals are compared with the reference sinusoidal signal to generate the PWM signals through the pulse logic decoder, as shown in Fig. 6. In the decoder circuit, the switching logic presented in Table I is synthesized through the appropriate combination of logic gates. The PPC scheme does not involve any complex equations to retain the fundamental component, unlike the SSC technique. Nevertheless, the conversion ratio of the proposed circuit can be varied in the range of 0.5V in to 4V in by varying m i .

VI. SIMULATION ANALYSIS
The proposed 17-level MLI consisting of 12 IGBT switches is simulated in MATLAB/Simulink environment. The input dc source is considered 100 V and the inverter is operated with a 50-Hz nominal frequency unless otherwise specified. The capacitance values are accordingly calculated using (8)- (10) and C 1 , C 2 , and C 3 are chosen as 3300, 4700, and 2200 μF,   Fig. 7(c) verifies the working under a change in load PF with the change in loading from 90 Ω-108 mH to 120 Ω-108 mH. The capacitor voltage ripple decreases with an increase in R value for fixed C 1 , C 2 , and C 3 . The capacitor voltages inherently settle to the original value under sudden variation in input from 80 to 100 V, as shown in Fig. 7(d), which verifies the successful performance of the proposed SC MLI. Fig. 7(e) depicts that the voltage ripple decreases considerably and the load current drops due to an increase in frequency from 50 to 150 Hz (switching angles corresponding to 150 Hz are also saved in lookup table) in the presence of inductive loading. Evidently, the proposed MLI can act as a potential high-frequency ac source for different applications. Fig. 7(f) shows that the voltage stress across all the unidirectional switches is in accordance with Fig. 1. It is also apparent that apart from switches S 1 , S 2 , S 11 , and S 12 , all other switches operate at a low frequency, which thus results in low power loss in the circuit.

VII. EXPERIMENTAL VERIFICATION
To verify the suitable real-time operability, a test setup of the proposed 17-level MLI is developed in the laboratory. A programmable dc supply is initially set to 100 V. As the output voltage is boosted to four-times the input, the rms value of the load voltage is about 280 V. IGBT switches 12N60A4D with integrated antiparallel diodes are considered for S 1 -S 12 and two MUR860 are used as D 1 and D 2 . Selected values of the capacitance (C 1 -C 3 ) are the same as in simulation with internal resistances 36, 18, and 54 mΩ, respectively. A DSP controller with Simulink interfacing is used to produce the switching pulses of (0-5) V. An isolated driver circuit built using TLP250 is then used to amplify these pulses (about 20 V) which drive the switches. In addition, the driver circuit also provides adequate isolation between the power circuit and control circuit. A ScopeCoder (DL850E) is used to capture the voltage-current waveforms and the performance parameters are obtained using a WT1800 power analyzer.
Identical to the result shown in Fig. 7(a), experimental outputs are obtained with a change in m i and with fixed resistive loading of 90 Ω in Fig. 8(a). The desired 17-level output is obtained with a change in switching pulse in conjunction with variation in m i from 0.3 to 0.94. Further, tests follow considering higher m i value (0.94). The rms value of load current varies from 2.9 to 3.9 A and the PF varies from 0.93 to 0.85 as the load changes from 90 Ω-108 mH (RL-1) to 60 Ω-120 mH (RL-2) in Fig. 8(b). The output voltage and capacitor voltages are undistorted during the sudden load transient. Self-balancing of the capacitors in both Fig. 8(a) and (b) is obtained due to appropriate charging-discharging. Herein, the capacitor currents and the source current are depicted in Fig. 8(c) with 90 Ω load, which implies symmetrical charging pattern of the capacitors in a full cycle. The current spikes are reduced using a small inductor (0.03 mH) in the charging loop that is not shown in the circuit analysis for the sake of simplification. The captured power analyzer results in Fig. 8(d)-(g) show the change in activereactive power (P, Q), PF (λ), phase angle (Ф), efficiency (η1), voltage THD, and current THD. Fig. 8(d) and (e) is obtained in accordance with Fig. 6(a) at fixed resistive loading and change in m i . The THD varies with the change in m i . Fig. 8(f) and (g) is obtained in accordance with Fig. 8(b) with a change in load from RL-1 to RL-2. A proportional increase in the active power and change in efficiency is witnessed with decrease in the impedance and PF. Fig. 8(h) and (i) further verifies the self-balancing and step-up abilities of the proposed circuit with sudden variation in input voltage (90 to 100 V) and output frequency (150 to 50 Hz), respectively. Similar observation as in Fig. 7(f), the voltage stress on switches is testified in Fig. 8(j).
To verify the adequate operation of the proposed circuit, experimental tests are further performed with PPC technique considering a switching frequency and nominal frequencies of 2 kHz and 50 Hz, respectively. Initially, the proposed inverter produces a 13-level output with 0.6 m i and the desired 17-level output is obtained, as shown in Fig. 9(a), once m i is changed to unity. Fig. 9(b) ascertains a clean sinusoidal load current, undistorted load voltage, and self-balanced capacitor voltages with a change in loading from RL-1 to RL-2 under the PPC scheme. The efficiency of the prototype is further evaluated with the corresponding output power considering pure resistive loading of 90 Ω. It is clear from Fig. 9(c) that the switching power loss, conduction loss, and the ripple losses increase with an increase in the output power.

VIII. CONCLUSION
This work introduced a reduced switch single-source SC MLI with quadruple boosting ability. Using only 12 switches and three capacitors, the proposed MLI is able to synthesize a 17-level output with a reduced number of devices in the conducting path. The capacitors C 1 and C 2 can inherently balance the voltage in 1:2 ratio using the series-parallel charge balancing principle and the capacitor C 3 self-regulates the voltage at 0.5V in due to symmetrical charging-discharging in a full cycle. Thus, the use of auxiliary voltage balancing circuit/sensors is avoided. The operating principles, voltage balancing ability, steady-state analysis of the SCs, and power loss evaluation have been addressed thoroughly. The comparative assessment with recent-art 17-level structures demonstrates the benefits on lower number of components, minimum cost factor, and no requirement of polarity reversal H-bridge. Simulation and experimental investigations of the 17-level MLI under change in m i , sudden change in supply voltage, change in PF, and frequency variation fully testify the structural operability. Moreover, high step-up operation with adequate inherent voltage balancing without additional dc-dc converter makes the proposed MLI suitable for PV applications.

ACKNOWLEDGMENT
The projects funders were not directly involved in the writing of this article.