Optimized 9-Level Switched-Capacitor Inverter for Grid-Connected Photovoltaic Systems

This paper introduces a novel switched-capacitor-based 9-level inverter topology to meet IEEE standards for low total harmonic distortion (THD) in grid-connected inverters. The new design addresses the trade-off between increasing output voltage levels to reduce harmonics and the consequent rise in device count. The proposed topology is streamlined, consisting of 12 switches, 3 capacitors, 2 diodes, and a single DC source. Comparative analysis with similar topologies confirms the advantages of the new design. The experimental results show that the proposed inverter achieves a THD of 13.58% in its output voltage. The topology is validated through its application in a single-stage, three-phase photovoltaic system connected to the grid. Simulations are conducted using MATLAB/Simulink to test the system's performance. Furthermore, hardware-in-the-loop experiments are performed using OPAL-RT 5700 real-time simulators to further substantiate the efficacy of the proposed topology.

Abstract-This paper introduces a novel switched-capacitorbased 9-level inverter topology to meet IEEE standards for low total harmonic distortion (THD) in grid-connected inverters.The new design addresses the trade-off between increasing output voltage levels to reduce harmonics and the consequent rise in device count.The proposed topology is streamlined, consisting of 12 switches, 3 capacitors, 2 diodes, and a single DC source.Comparative analysis with similar topologies confirms the advantages of the new design.The experimental results show that the proposed inverter achieves a THD of 13.58% in its output voltage.The topology is validated through its application in a single-stage, three-phase photovoltaic system connected to the grid.Simulations are conducted using MATLAB/Simulink to test the system's performance.Furthermore, hardware-in-the-loop experiments are performed using OPAL-RT 5700 real-time simulators to further substantiate the efficacy of the proposed topology.

I. INTRODUCTION
S OLAR photovoltaic (PV) energy has become a viable alternative to conventional energy sources today.Power converters play an important role in the transformation of solar energy into electric energy [1], [2].Among these, multilevel inverters (MLIs) are particularly favored for their superior output waveform quality, reduced total harmonic distortion (THD), minimal filtering needs, and lower voltage stress, among other advantages.This allows the use of devices of lower rating, thus reducing both the cost and size of MLIs [3], [4], [5].MLIs are generally classified into neutral-point-clamp (NPC), flying-capacitor (FC), and cascade H-bridge (CHB) types.For MLIs connected to the grid, it is essential that the THD of the output voltage is in accordance with existing IEEE standards.To achieve this, an increase in voltage levels is often required, leading to a corresponding increase in the number of switches and devices.However, this increase in device count adds operational complexity, cost, and losses, particularly when higher voltage levels are targeted [6], [7].
To mitigate the challenges associated with traditional MLIs, the literature features various topologies designed to minimize the number of devices.Transformerless inverters (TI) have gained popularity in PV systems for their cost-effectiveness and compact size.However, they lack galvanic isolation and struggle with leakage current restriction, particularly in HERIC and H-6 configurations, due to switch-junction capacitance [8].Moreover, these topologies are often bulky and expensive, necessitating the use of dual inductors for filtering and resulting in elevated conduction losses.In the case of NPC and FC topologies, a significant challenge lies in maintaining voltage balance across capacitors.The design process for these topologies is inherently cumbersome, and their output voltage levels are generally limited to five.Expanding beyond this five-level configuration for NPC and FC topologies introduces complexity due to increased device count [9].CHB-MLIs typically employ multiple isolated DC sources to achieve elevated voltage levels [10], [11].In PV systems, this often involves the use of several PV arrays, which introduces problems such as partial shading, array mismatches, and synchronization difficulties in Maximum Power Point Tracking (MPPT) algorithms.As a result, MLIs operating on a single DC source are generally preferred for PV applications [12], [13].
Switched-Capacitor Multilevel Inverters (SCMLIs) have shown promise for photovoltaic applications because of their ability to produce higher voltage levels while using minimal switch count and a single isolated DC source.In SCMLIs, capacitors are connected either in series or parallel during charging and discharging modes, and are specifically arranged in series during the discharging phase to achieve higher output voltage levels.Despite these advantages, SC-based Transformerless Inverters (TIs) designed for five-level output still suffer from high levels of harmonics in their output voltage [14].As a result, these inverters require high-volume filters to effectively attenuate the harmonics.Further research into SC-based 7-level inverter topologies reveals challenges such as high voltage stress across switches [15], [16].Additionally, some of these 7-level topologies have issues related to capacitor balancing [17].In the context of PV-grid integration, a specific 7-level topology has been introduced that minimizes the number of switches and reduces the voltage stress [18].Despite this, this design produces a THD of 16.66 % in its output voltage, making it necessary to employ larger filters to meet the IEEE 519-2022 standards for the 8 % THD below 1 kV bus voltage at PCC.
To achieve a balance between minimizing switch count and reducing the THD in the output voltage, a number of 9-level (9 L) inverters have been explored in the literature.Various inverter topologies designed to produce the 9 L output voltage are discussed in [19], [20], [21], [22].However, these designs subject the switches to high voltage stress.Conventional methods to create a 9 L inverter, such as using cascade H-bridge units, require a minimum of four units with 12 switches and four isolated DC sources, making the system costly, bulky, and complex [23].In PV applications, the use of multiple isolated DC sources introduces complications such as partial shading and mismatch of PV modules.Alternative 9 L topologies that utilize 13 and 12 switches are presented in [24], [25].These designs, although effective, increase the overall cost due to the high number of switches.In [26], a packed e-cell topology is proposed for 9 L output, but it also relies on two isolated DC sources.Similarly, a t-type packed u-cell topology is described in [27], which also employs two isolated DC sources.Further developments in 9 L inverters that focus on the use of a larger number of switches and DC sources are presented in [10], [28], [29].This contrasts with the existing 13-level inverter design, which features 1.5 times voltage boosting and is based on two K-type units and 14 switches, including clamping transistors [30].The primary objectives of this manuscript are as follows.r To implement a three-phase, single-stage solar PV system using the proposed 9 L topology and integrate it with the grid.Compared to the conference version [1], which proposed a 9 L inverter using optimal devices, the manuscript further elaborates on and advances the work by: r A pre-existing 7-level MLI [18] was successfully extended to a 9-level topology with reduced THD, utilizing only twelve switches and a single DC input source.r A novel switching table was developed, achieving not only a 9-level output voltage, but also ensuring self-balanced floating capacitor voltages, thus enhancing the system's robustness and efficiency.
r The newly developed 9-level MLI topology was effec- tively implemented in a single-stage, three-phase solar PV system, demonstrating its real-world applicability and relevance to current energy demands.By achieving these additional objectives and contributions, the manuscript provides a more comprehensive and in-depth study, distinguishing itself from the conference version.The construction and working principle of the proposed 9L-SCMLI topology are described in Section II.The theoretical analysis with PV-grid integration using the proposed 9L-SCMLI topology is also presented in Section II.The results and discussion  are explained in Section III.Finally, the conclusion is drawn in Section IV.

A. Topology Description
The topology of the proposed 9L-SCMLI inverter is shown in Fig. 1.It is a single-phase configuration.It comprises nine active IGBT switches (S 1 , S 2 , . . .S 9 ), two DC-link capacitors (C 1 , C 2 ) and two floating capacitors (C 3 , C 4 ).Switches S 7 , S 8 , and S 9 are bidirectional, and the remaining switches are unidirectional.Switches S 3 and S 4 are reverse blocking IGBTs.A half-bridge made of S 1 and S 2 is connected to the output side of the inverter.The midpoint of two floating capacitors (C 3 and C 4 ) and the other midpoint between the switches S 1 and S 2 are joined through a bidirectional switch S 9 .The midpoint of two DC-link capacitors C 1 and C 2 is connected to one end of the bidirectional switches S 7 and S 8 .The proposed inverter is fed from a single DC source with DC-link voltage V dc .The magnitude of the input DC voltage is equally divided between C 1 and C 2 .Therefore, the voltage across each of them is equal to (V dc /2).Each floating capacitor C 3 and C 4 is charged to a voltage magnitude of V dc /2.A load is applied to the output terminal.All switching states to generate the desired voltage levels are listed in Table I.Fig. 2(a).The series connected DC-link capacitors C 1 and C 2 are charged to V dc , so the voltage across each of them becomes equal to V dc /2 and remains constant regardless of operating states.The strings of floating capacitors C 3 and C 4 are charged to V dc /2 through a switch S 3 and S 8 as indicated by a blue dotted line.So, the voltage in both C 3 and C 4 becomes equal to V dc /4.The charges of C 3 and C 4 are evenly distributed throughout the cycle, as shown in Table I

B. Operating Principle
Operating State-2 (v o = 0.25V dc ): During this state, switch S 3 , S 8 , and S 9 are ON.The positive load current flows through the path C 1 -S 3 -C 3 -S 9 -C 1 as indicated by the red line as shown in Fig. 2(b).The string of C 3 and C 4 is charged to V dc /2 through a switch S 3 and S 8 as indicated by the blue dotted line.The output voltage during this state 2 v 2 o can be expressed as Operating State-3 (v o = 0.5V dc ): During state 3, the switch S 1 , S 3 , and S 8 are ON.The positive load current flows through the path C 1 -S 3 -S 1 -C 1 , which is shown by the red line.The charging of C 3 and C 4 takes place through the switch S 3 and S 8 as indicated by the blue dotted line as shown in Fig. 2(c).The output voltage (v 3 o ) during state 3 can be represented as Operating State-4 (v o = 0.75V dc ): During state 4, switch S 5 and S 9 are ON.The positive load current flows through the path C 1 -S 5 -C 4 -S 9 -C 1 as depicted in Fig. 2(d).The load current path is shown by the red line.No charge or discharge of C 3 occurs, although C 4 is discharged through the load.The output voltage during state 4 can be written as For the remaining states, as indicated in Fig. 2(f) to Fig. 2(j).The analysis is the same as described for the above-mentioned states.
As a result, nine different voltage levels are produced in the output voltage, including ±V dc , ±0.75V dc , ±0.5V dc , ±0.25V dc , and ±0.

C. PWM Control for Proposed 9L-SCMLI
The carrier-based sine PWM technique is considered to control the proposed 9L-SCMLI.One sinusoidal reference signal with an inverted negative half-cycle and four triangular carrier signals are used.The advantage of using such an inverted negative half-cycle reference signal is that the number of required carrier signals is half that of the noninverted reference signal.Hence, only four carrier signals instead of 8 are required to control a 9-level inverter.Each of the carrier signals has a 2.5 kHz frequency.The carrier signals are level-shifted one above the other above the x-axis.Therefore, such a PWM is henceforth termed in this paper level-shifted PWM (LS-PWM).In addition to the reduced number of carrier signals, LS-PWM produces fewer harmonics in the output voltage.When the reference signal cuts the carrier signals, the gate pulses for all switches in the proposed 9L-SCMLI are produced according to the logic given in Fig. 3.In which the output of the AND gate ±0 indicates zero voltage levels, ±0.25 indicates ±0.25V dc voltage levels.Similarly, the voltage levels ±0.5V dc , ±0.75V dc , and ±V dc are Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 3. PWM logic circuit for producing switching pulses for switch S 1 to S 9 of the proposed 9L-SCMLI.

TABLE II VOLTAGE STRESS ACROSS THE PROPOSED 9L-SCMLI SWITCHES
represented by the outputs ±0.5, ±0.75, ±1, respectively.The carriers and reference signal arrangement, the gate pulse of each switch, and the 9-level output voltage waveform are illustrated in Fig. 4. The modulation index can be calculated as where m a represents the modulation index, and V ref and V cr are the peak values of the reference signal and each carrier signal respectively.

D. Theoretical Analysis
Voltage and Current Stress on Switching Devices: Analyzing the operating states as demonstrated in Fig. 2, it is revealed that all the switches (S 1 -S 9 ) are clamped across the capacitors during their turned OFF period.Therefore, the voltage across each switch (V S1 -V S9 ) for each output voltage level can be calculated as shown in Table II.From this table, the maximum voltage stress across the switches can be expressed as, It is evident that the highest voltage-stress occurs across switches S 5 and S 6 are 1.5V dc .For the SC-based inverter, some switches carry additional current due to capacitor charging.In the proposed topology, the charge current through the active capacitor (i C ) flows through the switches S 3 , S 4 , S 7 and S 8 only.Therefore, the current stresses across these switches are maximum.Other switches carry only the load current (i L ).The peak amplitude of the charging current passing through the switches is high, but its average value is lower.In the same way, the current stress on all switches can be calculated and tabulated in Table III.The maximum current stress on each switch on the proposed inverter can be mathematically represented as where i S1 , i S1 , . . .i S9 are the maximum current stress across switches S 1 , S 2 , . . .S 9 , respectively.DC-link Capacitance Design: The semiconductor switches are selected considering voltage and current stress.The voltage between switches calculated in ( 7) is considered to decide the voltage rating of the switches.Average current ratings calculated in (8) are considered to determine the switching current rating.The switches S 3 and S 4 carry the capacitor charging current and the load current.Therefore, their current rating is high compared to other switches.The voltage rating of DC-link capacitors C 1 , C 2 and the floating capacitors C 3 , C 4 is determined on the basis of (1).The equivalent DC-link capacitance is calculated as where P o and ΔV dc represents the average power output of the inverter and ripple voltage (5-10% of V dc ) in C 1 and C 2 respectively.As C 1 and C 2 are connected in series.The capacitance of floating capacitors can be calculated as where I L,max is the amplitude of output current and ΔV C is allowable ripple voltage (2-5% of V dc /4 as per (1)) in the floating capacitors.As two floating capacitors C 3 and C 4 are connected in series.
Loss Analysis: The losses that occur in an SC-based power electronics converter are conduction losses, switching losses, and ripple losses in capacitors.In addition to those losses, conduction losses in the diode also occur where the diode is used.For the proposed 9L-SCMLI, a detailed loss analysis is given as follows Conduction losses in switches and diodes: The IGBT with antiparallel diode is used as switches for the construction of the proposed 9L-SCMLI.In addition, two power diodes are also used.The conduction losses (P con ) and the diode losses (P d ) that occur on the switches and diodes, respectively, can be calculated as follows [31].
For the switches, the on-state resistance, and on-state voltage are represented by R T and V T , respectively.Similarly, for the diode, these variables are denoted by R D and V D , respectively.The symbol β is the constant coefficient of the switch.
Switching losses: The switching losses (P sw ) occur in the switch during its transition from the ON state to the OFF state and vice versa.The energy losses during turn-on (E on ) and turn-off (E of ) of each switch can be calculated as follows [31] v on I on t on (13) where v of , I of and t of are the turn-off voltage, current and time respectively of a switch.Similarly, v on , I on and t on are the voltage, current, and time during the switch turn on, respectively.Thus, total switching losses in the inverter can be evaluated as where N sw is a number of switches, f s is the fundamental frequency, and N on and N of are number of turning ON and OFF a switch during a complete cycle.

Ripple losses:
The capacitors in an SC-based converter carry the charging and discharging current.Power losses occur in the capacitors because of their own internal resistance.The magnitude of the power loss (P cap ) depends on the magnitude of its voltage ripple and can be calculated as where f sw is the switching frequency, C is the capacitance of the capacitors {C 1 , C 2 , C 3 , C 4 }, and ΔV c is the ripple voltage across respective capacitor.Therefore, the total losses that occur in the proposed 9L-SCMLI can be calculated as The total losses that take place in the switches, diodes, and capacitors of the proposed 9L-SCMLI are graphically presented in Fig. 5(a).It was calculated for a power output P o = 1000 W. The conduction losses in diodes (P d ) and ripple losses in capacitors (P cap ) together contribute 47% to the total losses.The rest of the losses (53%) take place in the switches (P con , and P sw ).Among switches, S 3 and S 4 have a maximum amount of losses each of 12% as it carries the charging current in addition to the load current.In a practical implementation, these two switches Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE IV COMPARISON AMONG VARIOUS TOPOLOGIES ([P]: PROPOSED)
could be strategically placed at one end of the power PCB near the entrance of the cooling mechanism.This could be forced air cooling or liquid cooling, depending on the specific application requirements.Such an arrangement would facilitate efficient heat dissipation from these switches, mitigating the impact of their higher loss contributions.The percentage of all four types of losses is shown in Fig. 5(b).which shows that the percentages of P con and P d are 44% and 22%, respectively.The contributions of P sw and P cap are 9% and 25%, respectively.

E. Comparative Study
In order to prove the effectiveness of the proposed 9L-SCMLI, a fair comparison with similar typologies is illustrated in Table IV.To make such a comparison, the number of voltage levels (N ), power electronics switches (N sw ), gate drives (N gd ), diodes (N d ), capacitors (N c ), and input DC source (N dc ) is taken into account.Furthermore, the switch-per-level ratio (N sw /N ) and the total standing voltage (T SV pu ) are added to the comparison to make it more reasonable.The term T SV pu is calculated as follows; where V Si is the voltage across ith the switch, and v o,max is the peak value of the output voltage.T SV sw (p.u) is evaluated after normalizing to v o,max .All typologies with voltage gain equal to one are selected to achieve a greater degree of comparison.A five-level inverter is investigated in [32], which has a larger switch-per-level ratio and its T SV pu value is quite high.In [16], a seven-level topology is proposed with 12 switches and 4 capacitors.The switch-perlevel ratio is still high in such a topology.For a conventional Cascade H-Bride 9-level topology, 12 switches and 4 isolated input DC sources are required.The larger number of isolated DC sources is a drawback of the topology.In [23], a 9-level topology with 9 switches is proposed.Though it comprises a reasonable number of switches, it uses 4 isolated input sources.In another literature, a 9-level topology is described with 13 switches [24].It consists of more switches and a higher N sw /N ratio.In [25], a 9-level topology is invented with 12 switches, 3 capacitors, and a DC source.The drawback of such a topology is a higher number of switches.In [26], [27], the 9-level topology is investigated.However, the N sw /N ratio, T SV pu , and the number of switches are reasonable.However, both topologies use two isolated DC sources to achieve 9-level output.Using 12 switches, 12 gate drives, and 2 DC sources, a 9-level inverter is proposed in [10].For such a topology, both the number of switches and the DC source are quite In [28], 17 switches and 4 capacitors are used to achieve a 9-level output.The number of switches is very large relative to the other topologies considered.Also, the value of T SV pu is quite high.In [29], the 9-level output is achieved using 12 switches, 12 gate drives, and 2 DC sources.Such a topology also has the disadvantage of using more than one DC source.In contrast to the above, in this paper, a 9L-SCMLI topology is proposed.It consists of 9 switches, 9 gate drives, 2 diodes, 4 capacitors, and only one DC source to produce 9-level output voltages.On the basis of the above discussion, it can be concluded that the 9L-SCMLI topology proposed in this paper is superior to other topologies taken into account.
The design of [33] comprises just 6 switches and 2 DC sources but requires an additional boost converter to achieve the required voltage boost.Likewise, the work in [34] generates a 7-level output using 12 switches; however, it requires a variable DC source, which is considered a drawback.On the contrary, a 7-level (7 L) topology that achieves a voltage boost of 1.5 times is presented in [18].Using 10 switches, its THD stands at an elevated 16.66%, indicating that there is room for improvement.The conventional 9-level cascaded H-Bridge (CHB) structure is described in [11].While it serves as a foundational structure, it has the downside of requiring a high number of DC sources, rendering it impractical for some applications.A similar 9-level topology equipped with a voltage boost feature is reported in [19].Although it also employs 10 switches, it is compromised by elevated voltage stress across those switches.An innovative 13-level output using 14 switches is demonstrated in [30], highlighting its extensibility through the addition of additional K-type units.Further multilevel inverter topologies for 11, 13, and 23 levels are explored in [35], [36], [37].These designs employ 11, 10, and 12 switches, respectively, but also suffer from high-voltage stress.In summary, each topology has its unique set of challenges, whether it is the number of DC sources, the high THD, the voltage stress or the complexity of the switch arrangements.Future research may focus on mitigating these issues to create more efficient and reliable systems.
The efficiency of an inverter topology is an important factor.It depends on the losses that occur in the topology.In a power electronics converter, three types of losses are mainly observed, such as conduction losses, switching losses, and capacitor ripple losses.The PLECS software is used to develop a thermal model of the inverter to evaluate losses.The efficiency of the inverter is estimated on the basis of the losses.The proposed 9L-SCMLI is correlated with recent MLIs in Table IV.This analogy is based on  the number of switches, diodes, DC sources, capacitors, and gate drivers required for those topologies.It is obvious that among the single source MLI topologies, the proposed 9L-SCMLI needs the minimum number of switches and gate drivers.As a result, the cost and volume of the proposed inverter are significantly reduced.Furthermore, the voltage stress across the switches is lower and the maximum number of series connected switches is two to carry the load current.Therefore, both conduction losses and switching losses are significantly reduced.Fig. 6 shows the efficiency curves of different topologies considered in Table IV.The efficiency of the proposed topology is observed to be higher than that of the others.The other topologies have a comparatively lower efficiency than the proposed one, as a result of the higher number of switches.The maximum efficiency of the proposed topology is 97.25%, which corresponds to 300 W output power.Compared to other topologies, the efficiency of the proposed 9L-SCMLI is still high, 94.08% for 1000 W output power, as shown in Table IV.The proposed 9L-SCMLI produces 13.58% THD, which is less than among the topologies considered for comparison.

F. PV-Grid Integration With Proposed 9L-SCMLI
A single-stage PV-grid integration system is established using the 3 − ϕ configuration of the proposed 9L-SCMLI.The 3 − ϕ configuration of the proposed inverter, as shown in Fig. 7 is made up of three similar inverter legs.The 3 − ϕ inverter is supplied by a single DC source through a common DC-link.The control block diagram of the system is shown in Fig. 8.The PV array is designed according to the specification in Table VI.The SunPower SPR-440NE-WHT-D photovoltaic module is selected in the PA array.The perturbation and observed (P & O) MPPT algorithm is used to extract the maximum power available from the photovoltaic array.The P & O is widely used for its precision and easy implementation.In each sample time, the MPPT calculates the delta change in the PV power and, based on the delta change, produces a reference value of V dc that is termed V * dc .Then it is compared with the measure V dc .The error signal is passed through a simple PI controller to produce a reference value of the current on the d-axis i * d .Three-phase PLL is used to convert the three-phase current (i abc ) and voltage (v abc ) at the point of common coupling (PCC) to the d-and q-axis current (i d, i q ) and voltage (v d, v q ) respectively.Then i * d and i d are compared and passed through the PI controller to produce v * d .Similarly, i * q is externally given compared to i q and passes through the PI controller to produce v * q .Next, v * d , v d and the feedforward term −ωLi q are added together to produce u * d , and v * q , v q and feed-forward term ωLi d are added together to produce u * q .Finally, three-phase reference signals (i * abc ) for PWM are produced from u * d and u * q by converting them into the dq-abc transformation.The gate pulses for the inverter are generated by comparing four triangular carrier signals with the 3 − ϕ sinusoidal reference signals V * abc .The inverter output is connected to a 400 V(rms) three-phase grid at the PCC point through a coupling inductor.

III. RESULTS AND DISCUSSION
In proposed 9L-SCMLI, an Insulated-Gate Bipolar Transistor (IGBT) model was meticulously designed based on the datasheet specifications of the Semikron SKM100GB063D, a widely-used IGBT.This approach was taken to ensure that the simulation results are closely aligned with real-world applications.The initial modeling was performed in the Altair PSIM environment, known for its robust electrical simulation capabilities, and was subsequently accessed through the OPAL-RT 5700 Real-Time Emulator (RTE) feature integrated within the MAT-LAB/Simulink platform.This dual-platform strategy served as Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE V SPECIFICATIONS FOR TESTING PROPOSED 9L-SCMLI
an additional layer of verification, improving the reliability and applicability of the model.
Essential electrical and thermal characteristics were also incorporated to provide a comprehensive and realistic representation of the hardware component.The following assumptions are taken during validation, since real-time computational efficiency is often required for Hardware-In-Loop (HIL) simulations.
r Components like IGBTs are modeled based on ideal char- acteristics using datasheets, ignoring actual non-linear behaviors for computational feasibility.
r Simulation simplifies the complex switching dynamics of real-world components, focusing primarily on switched behaviors rather than intricate transients.
r Parasitic inductances and capacitance are averaged to make the model computationally less intensive.The experimental setup for the HIL test is shown in Fig. 9 and consists of the OPAL-RT 5700 RTE with sampling time of 10 μs, a high performance workstation, and YOKOGAWA-made oscilloscopes (model DLM2024).A 2 μs dead time is provided for each gate pulse to control the proposed inverter through a level-shifted PWM.

A. Single-Phase Open-Loop HIL Validation
To test the single-phase 9L-SCMLI inverter in open-loop conditions, a series of Hardware-in-the-Loop (HIL) experiments are conducted in the laboratory.The inverter parameters utilized for these tests are detailed in Table V.The experiments proceed in the following sequence: Initial Setup: The LS-PWM technique is initially used to generate all the switching pulses required for the inverter operation.The inverter specifications are tabulated in Table V.
Resistive Load Test: A resistive load (R) with Z = 100 Ω is first connected to the inverter output terminal.The resulting waveforms for the voltage across floating capacitors (V C3 , V C4 ), output voltage (v o ) and output current (i L ) are shown in Fig. 10(a).The waveforms of V C3 and V C4 are balanced, each having a magnitude of 0.25V dc or 50 V.The peak of the output voltage (v o ) is 200 V, consisting of 9 equal voltage levels.The output current (i L ) exhibits a staircase waveform with a peak magnitude of 2 A.
Step Change to Higher Resistive Load: The resistive load is then changed from Z = 100 Ω to Z = 200 Ω and the corresponding waveforms are shown in Fig. 10 Voltage Transient Conditions: Initially, V dc is set to zero, leaving all waveform magnitudes zero.Upon application of a 200 V DC input, the inverter starts to operate automatically.This initial condition is shown in Fig. 12(c).
Frequency Change: The inverter output frequency suddenly changes from 50 Hz to 100 Hz, as shown in Fig. 12(d).v o and i L adapt to the new frequency.V C3 and V C4 remain unchanged.
Modulation Index Step Changes: Initial tests alter the modulation index from 1.0 to 0.7, as illustrated in Fig. 12(e) and then   The voltage stress across different switches is measured for a 200 V DC input.From Fig. 13(a), (b), and (c), it is observed that the maximum voltage stress across switches S 1 , S 2 , and S 9 is 100 V, 100 V, and 50 V, respectively.S 5 and S 6 exhibit a maximum voltage stress of 300 V and the remaining switches show a voltage stress of 200 V.The test results demonstrate that the proposed 9L-SCMLI performs smoothly under both steadystate and dynamic conditions.

B. Three-Phase Closed Loop Test Through PV-Grid Integration
1) Initial Experiment on 3-Phase Configuration: A 5 kW, single-stage, proposed 3 − ϕ 9L-SCMLI based PV-grid system is tested in HIL experiment using OPAL-RT 5700 RTE under different load and environmental conditions.First, the experiment on the 3 − ϕ configuration of the proposed 9L-SCMLI is carried out under open loop condition.The 3 − ϕ inverter is supplied by a 400 V DC source and operates with a 2.5 kHz switching frequency.A three-phase load of 5 kW with a 0.8 lag power factor is connected to the inverter output.The line-to-line output inverter voltage waveform (v inv(L−L) ), three-phase inverter currents (i a, i b, i c ), and the harmonic spectrum of i a are shown in Fig. 14.It is observed that v inv(L−L) consists of 17 equal voltage levels and that the three-phase currents are nearly sinusoidal.The %THD in phase-a (i a ) current is only 0.89%.
2) Testing Under Various Power Factor Conditions: The proposed photovoltaic grid system is tested under the conditions of unity, lag, and leading power factor.The respective waveforms are plotted in Fig. 15.Solar irradiance is kept constant at 1000 W/m 2 for all three cases.For the unity power factor, the phase-a voltage of the inverter (v a,inv ), phase-a grid voltage (v ga ), and injected grid current in phase-a (i ga ), and the harmonic spectrum of i ga are shown in Fig. 15(c).The inverter operates at a modulation index of 0.8.It is observed that v a,inv consists of 9 equal voltage levels and the peaks of v ga and i ga reach 325 V and 9.667 A, respectively.v ga and i ga are in phase due to unity PF, and i ga is nearly sinusoidal.The %THD in i ga is 3.27 %, which is consistent with IEEE standards.Then, the PV system is operated under lagging PF, and the respective waveforms of v a,inv , v ga , i ga , and the harmonic spectrum of i ga are plotted in Fig. 15(c).It is observed that i ga is close to sinusoidal and lags v ga by 28.14 • due to a lag PF operation.The peak of i ga reaches 12.44 A and its content is 2.84% THD, which is in accordance with IEEE 519-2022 standards.The PV system is then run with the leading PF, and the corresponding waveforms of v a,inv , v ga , i ga , and the harmonic spectrum of i ga are illustrated in Fig. 15(c).The inverter runs at 0.88 leading PF.The i ga leads to the v ga by the 28.14 • angle, which is the leading PF operation.The peak of i ga reaches 12.32 A. The %THD in i ga is 2. 92%, again complying with the IEEE 519-2022 standards.
3) Experiments Under Varying Irradiance: The experiment is carried out in the PV system under varying irradiance conditions, and the respective waveforms of the PV side under varying irradiance such as PV voltage (v pv ), PV current (i pv ), PV output power (P pv ) and injected real power (P g ) to PCC are shown in Fig. 16(a).A step change in irradiance from 1000 W/m 2 to 500 W/m 2 is applied, and it is reversed after a certain period of time.The power factor of the photovoltaic system was kept in unity during this experiment.The magnitude of v pv is 401.6 V for 1000 W/m 2 irradiances, and it is slightly reduced to 396.1 V during 500 W/m 2 irradiances.It can be said that the magnitude of v pv remains almost constant despite such Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.a variation in irradiance.The magnitude of i pv decreases from 12.1 A to 6.04 A when the irradiance changes from 1000 W/m 2 to 500 W/m 2 .The magnitude of P pv is 4.8 kW and 2.4 kW for irradiance 1000 W/m 2 and 500 W/m 2 , respectively.After achieving system losses, the PV system injects real power (P g ) into the PCC, which is 4.3 kW and 2.14 kW for irradiance 1000 W/m 2 and 500 W/m 2 respectively.The waveforms of the grid side parameters v ga , i ga , and the harmonic spectrum of i ga under such varying irradiance are shown in Fig. 16(b).The peak magnitude of v ga is observed to remain constant at 325 V despite the variation of irradiance.But the variation in the impact of irradiance on the magnitude of i ga .The maximum magnitude of i ga reduced from 9.667 A to 4.833 A when irradiance changed its step from 1000 W/m 2 to 500 W/m 2 .The change in the maximum value of i ga is smooth with the change in irradiance step.The %THD in i ga is 3.27% corresponds to 1000 W/m 2 irradiance.However, the %THD increases to 4.79% during 500 W/m 2 irradiance.Both the value of %THD in i ga comply with IEEE standards.

4) Dynamic Behavior Test:
The dynamic behavior of the PV grid system is tested under a step change of the power factor from Fig. 15.HIL results of the PV-grid system using the proposed 9L-SCMLI under different power factor conditions. lagging to leading.During this dynamic test, the irradiance value is kept constant at 1000 W/m 2 .The PV grid is initially run at 0.76 lag PF, then a command is applied to the control system to change the PF from 0.76 lag to 0.76 leading immediately.In this circumstance, the PV side parameters, such as v pv , i pv , and the real and reactive power P g , Q g injected into the PCC are illustrated in Fig. 17(a).It is evident that the magnitudes of v pv and i pv remain constant at 401.6 V and 12.1 A, respectively, due to constant irradiance.The magnitude of P g is also constant at 4.3 kW.However, the sign of Q g changes from positive (+3.5 kVAR) to negative (−3.5 kVAR) when the PF changes from lagging to leading.The grid side parameters under such a varying PF are plotted in Fig. 17(b).It is noticed that the magnitude of v ga remains constant at 325 V, irrespective of the change in PF.The maximum value of i ga is kept constant at 12.44 A for the lag PF and 12.32 A for leading PF, respectively.However, i ga lags v ga by the 39.11 • angle during the lagging PF operation and advances v ga by the same angle during the leading PF operation.The %THD in i ga are 2.84% and 2.92% for 0.76 lagging PF and leading PF, respectively, which comply with IEEE standards.The angle change of i ga from lagging to leading occurs instantly.Therefore, it is concluded that the Fig. 16.HIL results of the PV-grid system using the proposed 9L-SCMLI under varying irradiance conditions.Fig. 17.HIL results of the PV-grid system using the proposed 9L-SCMLI under step change of power factor from lagging to leading.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
steady-state and dynamic behavior of the proposed photovoltaic grid system is satisfactory.

IV. CONCLUSION
In conclusion, this paper presents a new 9L-SCMLI topology that employs a single DC source while minimizing the switch count.The topology consists of 12 switches, 3 capacitors, and 2 diodes and is capable of generating nine different output voltage levels with unity voltage gain.The output voltage has a low total harmonic distortion (THD) of 13.58%, attesting to its high-performance capability.This design leverages the switched-capacitor technique and has a self-voltage balancing feature.A comprehensive comparison with existing topologies based on criteria such as switch count, voltage stress, and number of conducting switches demonstrates the superior effectiveness of the proposed design.The topology has shown satisfactory steady-state and dynamic performance under various test conditions.A single-stage three-phase photovoltaic (PV) system integrated with the grid has been successfully implemented using the proposed 9L-SCMLI.Experimental results under different conditions confirm the system's reliable performance and compliance with IEEE 512 standards for THD content in the injected grid current.This makes the proposed topology particularly well-suited for PV applications.Future work will explore the feasibility of scaling this topology for higher voltage and power applications.

r
To design a new 9 L topology with reduced device count while achieving self-balanced capacitor voltage.r To strike a balance between the output voltage %THD and the device count, addressing a current research gap.
Operating State-1 (v 0 = 0): During state 1, switch S 2 , S 3 , and S 8 are enabled.The positive load current flows through the path C 1 -S 3 -C 3 -C 4 -S 2 -C 1 as indicated by the red line as shown in

Fig. 2 .
Fig. 2. Different operating states (a)-(j) of the proposed 9L-SCMLI in respect of the output voltage v o .
dc ): During state 5, switch S 1 and S 5 are ON.The positive load current flows through the path C 1 -S 5 -C 4 -C 3 -S 1 -C 1 as indicated by the red line as shown in Fig. 2(d).Both C 3 and C 4 are discharged by load.The output voltage during state 5 can be written as

Fig. 5 .
Fig. 5. (a) Power loss distribution among different devices and (b) Percentage of different types of losses of the proposed 9L-SCMLI.

Fig. 6 .
Fig. 6.HIL verified efficiency curves of different topologies in relation to output power.
(b).Despite the instant load change, the waveforms of V C3 , V C4 , and v o remain constant.The only change is in the magnitude of i L , which decreases to half.Switching to Resistive-Inductive Load: Subsequently, the load is switched from a purely resistive load to a resistive inductive load (RL) characterized by Z = 100 Ω + 80 mH.The updated waveforms are shown in Fig. 10(c).The output voltage (v o ) waveform remains unchanged.V C3 and V C4 are still balanced.The waveform of i L transitions smoothly from a staircase almost sinusoidal.RL Load Connection: Initially, a Resistive-Inductive (RL) load characterized by Z = 100 Ω + 80 mH is to the inverter output terminal.The harmonic content in v o i L is depicted in Fig. 11(a) and (b), respectively.%THD values for v o and i L are 13.58% and 1.21%, respectively.The corresponding observations can also be made from Fig. 12(a).Both V C3 and V C4 have balanced magnitudes of 50 V.The output voltage (v o ) waveform remains unchanged from the previous tests.The output current (i L ) transitions to a nearly sinusoidal waveform.DC Voltage Change: A sudden change in DC voltage is applied from 0.5V dc to V dc and the results are illustrated in Fig. 12(b).The magnitudes of V C3 , V C4 , v o , and i L instantly adjust to the new level V dc .
from 0.7 to 0.45, as illustrated in Fig. 12(f).The observations made from 12(f): V C3 and V C4 remain constant; the magnitude of i L decreases proportionally; v o changes to 9, 7, and 5 voltage levels for m a = 1.0, m a = 0.7, and m a = 0.45, respectively; and further tests reverse the modulation index from 0.2 to 0.45, and then to 0.7.Similarly, observations made in Fig. 12(f): v o and i L adapt to the new modulation index; v o manifests 3, 5, and 7 voltage levels; and i L increases proportionally.

Fig. 13 .
Fig. 13.Voltage stress across switches of the proposed 9L-SCMLI for input DC voltage V dc = 200 V during open-loop HIL test.

TABLE I SWITCHING
STATES OF THE PROPOSED 9L-SCMLI

TABLE III CURRENT
STRESS ON PROPOSED 9L-SCMLI SWITCHES

TABLE VI SPECIFICATIONS
OF THE PV ARRAY