Analysis and Experiment of Nanosecond Pulse Circuit Based on Commercial Si-p-i-n Rectifier Diode

In this article, a nanosecond pulse generation circuit is designed and fabricated based on a commercial Si-p-i-n rectifier diode using the DSRD principle. The circuit is composed of four parallel stacks with a 3-kV pulse output and a rise time of less than 2 ns. Each stack contains four diodes in a series. The working principle and main parameters of the circuit are analyzed by Pspice, and the simulation results are consistent with the experimental results. Switching cutoff speed, reverse voltage, offset voltage, and the topological circuit structure of connecting the rectifier diodes affect the amplitude and rise time of the output pulse.


I. INTRODUCTION
H IGH-VOLTAGE fast switch has a wide range of application values in ultrawideband technology [1], laser drive technology [2], particle accelerator systems [3], [4], automobile engine ignition systems [5], plasma discharge [6], sewage treatment [7], medical treatment [8], and other fields. The gas switch is limited by switch jitter and repetition frequency, the avalanche transistor is limited by voltage amplitude, the photoconductive semiconductor switch (PCSS) is limited by lifetime and complex optical systems, and insulated gate bipolar translator (IGBT) and MOSFET are limited by switch speed; none of them is ideal switches for long-life, low jitter, high repeat frequency, and high-voltage nanosecond pulses generation. In the 1980s, the drift step recovery diode (DSRD) was invented by Russian scientist, Grekhov et al. [9]. The device using inductance as the energy storage element has the capability of cutting off kA current [10] level of nanosecond or sub-nanosecond, kilohertz to megahertz repetition frequency [11], [12], picosecond switching jitter [13], and an almost infinite lifetime. It is an ideal switch to produce a high-voltage fast pulse. DSRD is a dual-terminal device with P + PNN + structure [14]. It requires a relatively low and long forward current flowing to the p-n junction to inject carriers, and the injection time is tens to hundreds of nanoseconds. Then, a higher and faster reverse current is used to extract the carriers stored in the p-n junction, which leads to the space charge area of the p-n junction recovering quickly and the reverse current fast cutoff. DSRD is not a standard commercial device and is only designed and used at a few laboratories. It is expensive and not easily accessible. However, studies found that some commercial Si-PiN rectifying diodes can be in fast cutoff operating mode. In [15], commercial diode 6A10 combined with gas discharge tubes (GDT) is used to generate nanosecond pulses. The 6A10 is used as DSRD and is driven by a periodic bipolar rectangular pulse generated by a bipolar dc supply. The GDT is used as a sharpening switch. The pulse voltage obtained on 47-load is 168 V with 3.5-ns rise time. In [16], the power rectifier diode is driven in the DSRD regime. The drive circuit consists of a primary switch and a transformer. The output pulse on a 50-load is about 1.2 kV with a rise time less than 2 ns. The maximum repetition frequency can reach 65 kHz, with the time jitter being less than 25 ps. These studies show the potential of developing low-cost pulse generation circuits.
The circuit topology of generating nanosecond pulses using DSRD usually includes the following types. The first is a double switch circuit [18]. Two primary switches control two resonant circuits to pump DSRD in the forward direction and extract DSRD in the reverse direction. The opening time of the two switches differs by half a cycle. This circuit requires two sets of relatively complex primary switch drive systems. The second type is a circuit composed of a single primary switch and a saturated core transformer [19]. Its circuit feature is that the transformer's secondary is equivalent to a magnetic switch. When the magnetic core is saturated, the capacitance in the transformer's secondary circuit is discharged and the current flows in reverse through the DSRD. The circuit uses a magnetic switch to replace the second primary switch simplifying the circuit. However, due to the introduction of a magnetic core, the loss increases and the repetition frequency This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ is limited. The third type is the single switch circuit [12], [20] that only needs one primary switch. The forward injection and reverse extraction of DSRD are realized through switch's opening and closing states. This circuit has a simple structure and low loss. By selecting high-speed MOSFET as the primary switch, MHz repetitive operation frequency can be realized.
Unfortunately, much of the literature directly gives the circuit's final parameters for the third kind of circuit, and the parameters in similar circuits are differing. When using a rectifier diode to design a pulse circuit in the DSRD operating mode, circuit parameters' choice is confusing. In addition, the literature often focuses on the pulse's output power and repetition frequency, while the factors affecting pulse output performance are less discussed.
This article designs a high-voltage nanosecond pulse generation circuit based on commercial Si-p-i-n rectifier diodes with only one primary switch. The circuit configuration and main parameters are analyzed in detail, and the factors affecting pulse output are also discussed by the Pspice simulation and experiment. Using the combination of four stacks in parallel, each stack containing four diodes in series, a 3-kV nanosecond pulse is generated with a rise time of about 2 ns. This article's analysis and experiment methods are beneficial for developing a fast high-voltage nanosecond pulses circuit with commercial devices similar to DSRD. This article is arranged as follows. Section II presents the nanosecond pulse generation circuit principle and estimates the circuit parameters. At the same time, the effects of diode cutoff time and load parasitic parameters on output performance are analyzed by simulation. Experimental results are given in Section III, and the factors affecting pulse output are discussed. The conclusion is highlighted in Section IV.

A. Principles of Circuits
The circuit configuration of high-voltage pulse generation is shown in Fig. 1. At the initial time, switch S is opened, and capacitor C 2 is charged through the loop of Fig. 1(a)]. Then, switch S is closed to pump the current of the diode D in the forward direction through the C 2 -S-D-L 2 loop, and V 1 charges L 1 concurrently [see Fig. 1(b)]. Tens of nanoseconds later, switch S is opened again. The current through L 1 changes direction to C 2 -L 2 -D, resulting in diode D pulsing in the reverse direction. Diode D is quickly interrupted when the carrier stored in the p-n junction is extracted completely. The current through diode D is switched to R L through capacitor C 4 , generating a highvoltage pulse on R L [see Fig. 1(c)]. Diode D cutoff speed determines pulse rise time. Setting the value of V 1 -V 2 can be used to adjust the forward pumping current. V 1 can also be used to adjust the reverse current. The time of switch S turning on determines the forward pumping time. C 1 is the power supply regulated capacitance. C 3 can limit the overshoot voltage of switch S when diode D is interrupted. C 4 blocks the direct current. R 1 limits the charging current of V 2 and blocks voltage pulses when diode D is interrupted.

B. Circuit Parameters' Estimation
As shown in Fig. 1, when switch S is closed [see Fig. 1(b)], C 1 , L 1 , S, and the resistance R d (including switch-on resistance and loop distribution resistance) form an oscillation loop. To obtain a large current, the inductor L 1 value should be less than hundreds of nanohenries, while the regulated capacitance C 1 is usually greater than or equal to 1 μF. Thus, the resistance R d is approximately equal to 2(L 1 C 1 ) 1/2 , and the L 1 current is where t is the turn-on time of switch S. When switch S opens again [see Fig. 1(c)], L 1 current will transfer to L 2 , and its energy will transfer to L 2 through C 2 ; consequently, L 1 = L 2 and I L1 = I L2 , where I L2 is the current flowing through L 2 . The reverse current of diode D can be approximately equal to I L2 , that is, I D = I L2 = I L1 .
As diode D turns off, its resistance increases with time, and time dependence resistance is set as R D (t). To obtain a large voltage on R L , C 4 capacitance should meet where ω is the angular frequency. The total impedance of the subsystem composed of diode D, capacitor C 4 , and load R L is During the diode D cutoff, the current I D will decay exponentially with a decay constant of L 2 /R tot . When diode D is completely cut, the maximum load current on is t is the time of diode D completely interrupted. According to (1) and (4), L 1 = L 2 , I D = I L1 , and the maximum load current is According to (5), the maximum current on load is related to L 1 . Taking t as a constant, derivate L 1 for (5) and set (6) to zero When I R L max is maximized, L 1 is equal to When diode D is turned off, In general, the Si-p-i-n rectifier diode with reverse withstand voltage ≥1 kV has an i layer width >120 μm. Since Si's electron saturated drift velocity is around 1 × 10 7 cm/s, the time needed for electron transit through i layer is >1.2 ns. Thus, when sets t = 2 ns, t = 80 ns, R d = 1 , and R L = 50 , L 1 is about 140 nH.
In addition, when switch S is closed [see Fig. 1(b)], C 2 , S, D, L 2 , and distribution resistance also form an oscillation loop that pumps diode D in the forward direction. The pumping time (t) should be less than half of the period of oscillation. Here, we take t < π(L 2 C 2 ) 1/2 for simplicity, so when t = 80 ns and L 2 = 140 nH, C 2 should exceed 4.6 nF.

C. Circuit Simulation
The circuit shown in Fig. 1 is simulated by Pspice software. Switch S is an ideal model with a turn-on time of 80 ns, and the front and rear edges of the switching time are less than 10 ns. The other circuit parameters are set as: C 1 = 1 μF, C 2 = 100 nF, C 3 = 1 nF, C 4 = 1 nF, R 1 = 1 k, and R L = 50 . Diode D adopts the Pspice diode model of 1N4007 [12]. When V 1 is 105 V and V 2 is 55 V, the load output voltage is approximately 1.2 kV, and the rise time is about 2 ns.
The simulated waveform of load voltage and diode current is shown in Fig. 2. The black curve represents the ON state of switch S.
As shown in Fig. 2, the interrupted diode current is about 42 A, which is close to the calculated current, according to (1) (about 45 A), while the current on load is about 24 A. It takes time for the diode to cut off, so the load current is less than the cutoff current. According to (4), the shorter the cutoff time, the  Initially, switch S 1 is open and S 2 is closed. Next, S 1 is closed at time t 1 and Vs charges the inductive L c . After a few tens of nanoseconds, S 2 is open at time t 2 . The current flowing through L c changes its direction to load R 2 .
The load currents with different rise times are obtained by setting different switch S 2 cutoff times, as shown in Fig. 4. The current amplitude decreases with the increase of rise time. When the rise time is about 2 ns, the load current slightly exceeds half of the maximum current.
In generating nanosecond pulses, the load distribution parameters impact output characteristics. The distributed parameters mainly come from the series parasitic inductance and parallel parasitic capacitance the load connection introduces. The capacitive reactance and inductive reactance are Z cs = 1/2π f C and Z Ls = 2π f L, respectively. For pulse voltage with rise time t r , f = 0.35/t r . When t r = 2 ns, calculated, Z cs = 0.9 × 10 −9 /C and Z Ls = 1.1 × 10 9 L. The schematic of parasitic inductance (L s ) and parasitic capacitance (C s ) introduced by the load is shown in Fig. 5.
The load current is reduced when the series parasitic inductance is introduced. Assuming a requirement to reduce the  When parallel parasitic capacitance is introduced, the capacitance will shunt the load current. Assuming that the parasitic capacitance current required is less than 10% of the load current, the capacitive reactance of the parasitic capacitance needs to be met, Z cs > 10R L . Thus, C s < 1.8 pF. The simulation results of load current variation under different parallel parasitic capacitance are shown in [see Fig. 6(b)], When C s is 1 pF, the load current is hardly unchanged. When C s is 10 pF, 100 pF, and 1 nF, the load current decreases and the rise time increases.

III. EXPERIMENTAL RESULTS AND DISCUSSION
According to simulation circuit parameters, a pulse generator was made by a cell rectifier diode (ARS50M by Taiwan  Semiconductor with 1000-V reverse voltage and 50-A forward current), as shown in Fig. 7. Switch S is replaced by a highspeed MOSFET (DE475-102N21A by IXYS), and inductors L 1 and L 2 are wound by a hollow helix. A noninductive resistor of 0.1 is installed between diode D and the reference ground for current measurement, which is tested by a voltage probe with a bandwidth of 500 MHz. The output pulse was measured with a 50-high-voltage, high-frequency attenuator (60 dB) and an oscilloscope with a bandwidth of 1 GHz (LeCroy wave runner 140Xi-A).
Set driving time of MOSFET to 80 ns. When V 1 = 105 V and V 2 = 55 V, the output voltage is about 1.17 kV and the rise time is about 2 ns, as shown in Fig. 8.

A. Influence of V1 and V2 on Output
Keeping V (V 1 -V 2 ) and t unchanged and changing the voltage amplitudes of V 1 and V 2 , the test waveforms are shown in Fig. 9. When V 1 = 105 V and V 2 = 55 V, the maximum cutoff current (about 38 A) and output voltage (about 1.17 kV) are obtained. However, when V 1 and V 2 are above or below 105 and 55 V, respectively, the cutoff current and output voltage decrease, and multiple pulses occur simultaneously. In addition, although V and t were unchanged, the forward injection current is not maintained but decreases with increasing V 1 and V 2 . According to the DSRD operational principle, the forward injected charge should be equal to the extracted charge [17]. If V 1 is too small, the reverse current cannot extract all the forward injected charge when the reverse current reaches the maximum. Only after the reverse current has passed, the maximum can the forward injected charge be extracted completely. At this point, the cutoff current exceeds the maximum value, resulting in a smaller output voltage of the load, as shown in Fig. 9(a) and (b).
If V 1 increases, V 2 will also increase to keep V constant. From the circuit shown in Fig. 1, V 2 adjusts the voltage of capacitor C 2 and is the reverse voltage of diode D. Under the reverse voltage V 2 , the p-n junction depletion layer width is where ε is the relative permittivity of Si, q is the electron charge, and N is the doping concentration in the i layer. Therefore, the capacitance of the p-n junction is where A is the chip area of diode D. When the forward current is injected into diode D, the charge consumed by the depletion layer is Equation (10) indicates that the higher the bias voltage V 2 , the more charge is consumed. Under the same conditions of V and t, the forward injection charge is reduced with V 2 increase, resulting in a decreased forward injection current. When V 1 and V 2 increase to 155 and 105 V, respectively, the forward injection charge is dramatically reduced and quickly extracted completely, as shown in [see Fig. 9(d)], and the cutoff current and load voltage are greatly reduced.
When switch S is reopened [see Fig. 1(c)], L 2 , C 2 , C 3 , and diode D form an oscillation circuit. If V 1 and V 2 are too large or too small, diode D will be interrupted before or after the maximum reverse current is reached. In both cases, energy stored in L 2 cannot be fully transferred to the load. The remaining energy in L 2 will repeatedly inject and extract diode D through the oscillation loop and generate multiple pulse voltages on the load. Only when diode D is interrupted at maximum reverse current, can the energy in inductor L 2 be fully transferred to the load, as shown in [see Fig. 9(c)]. Thus, the best working condition of the pulse generating circuit is that diode D is cut off when the reverse current reaches the maximum.

B. Effect of Diode Parallel or Series Connection on Pulse Output
Keep the circuit parameters unchanged and only change the number of diodes D in parallel. Fig. 10 shows the output pulses with a different number of diodes in parallel. With increase in the number of parallel diodes, the "pedestal" voltage (pedestal voltage refers to the part where the output voltage rises slowly) decreases and the rise time increases.
The "pedestal" voltage mainly is from the voltage on the i layer before the diode D is quickly interrupted. It is determined by the reverse current density J re , the width of the i layer W , and the doping concentration N of the i layer where U ped is the "pedestal" voltage and μ e is the electron mobility. The drift velocity of electrons in the i layer is According to (11) and (12), when diodes are connected in parallel, the total diode area increases, resulting in a decrease in "pedestal" voltage and an increased rise time.
Connect diodes D in series and keep the circuit parameters unchanged. The output pulses with a different number of diodes in series are shown in Fig. 11. With an increase in the number of series diodes, the "pedestal" voltage increases and the maximum voltage amplitude decreases.  According to (11), the "pedestal" voltage is directly proportional to the width of the i layer. With the increase of series diodes, the total i layer width increases, increasing "pedestal" voltage.
In addition, when the series diode increases, diode resistance R D increases. It can be seen from (4) that the load's maximum current decreases with an increase of resistance R D , so the load voltage amplitude also decreases.
Multiple diodes need to be connected in series to prevent breakdown when using diodes to generate higher pulse voltage. When the diodes are connected in series, due to the increase of R D and the increase of i layer width, "pedestal" voltage increases and the load voltage decreases, which is not the desired result. A solution is to use parallel diodes to increase diode area A and reduce R D simultaneously to offset the impact of series diodes.
Although the increase of diode area A will lead to longer rise time, the higher output voltage also means higher reverse current I D . From (12), if I D and A increase simultaneously, the electron drift speed can remain unchanged, so the rise time of load pulse voltage can remain unchanged.
Four stacks of diodes are connected in parallel to generate high-voltage pulses, each stack containing four diodes in series. The MOSFET driving time is set to 80 ns. The diode reverse current is interrupted at the maximum when V 1 = 477 V and V 2 = 177 V. The output pulse reaches 3 kV and the rise time is less than 2 ns. The load pulse waveform is shown in Fig. 12.

IV. CONCLUSION
This article makes a pulse generator circuit with commercial p-i-n rectifier diodes. The output pulse is 3 kV, and the rise time is less than 2 ns. The factors affecting the output voltage, such as diode cutoff speed, reverse extraction voltage, bias voltage, diode series, or parallel connection, are studied. It is found that the faster the diode cutoff speed, the greater the current obtained on the load. If the reverse and bias voltages are too large or too small, the diode will have multiple injections and extraction, resulting in multiple pulses. To obtain the best output voltage, it is necessary to ensure that the reverse extraction current is interrupted when it reaches the maximum. Series connection of multiple diodes accelerates the cutoff speed and increases the "pedestal" voltage. Parallel connection of multiple diodes is beneficial to reducing the "pedestal" voltage but causes rise time increase. In some applications that need to generate nanosecond pulses, p-i-n rectifier diodes are easy to obtain and can replace DSRDs to reduce the cost of pulse generation circuits. However, it should be noted that the commercial p-i-n diode is not specially designed for subnanosecond pulse generation, and it is difficult to generate pulses with a rise time less than 1 ns by using the p-i-n rectifier diode. This article's analytical and experimental methods have reference significance for developing higher nanosecond pulse voltage using a p-i-n diode with the fast cutoff characteristic similar to DSRD. He is currently a Professor at the Graduate School of China Academy of Engineering Physics, Beijing, China. His research interests include subnanosecond pulse-radiating antennas and high-power microwaves.
Hengqing Zhang was born in Xianyang, Shaanxi, China, in 1997. She received the bachelor's degree in electronic science and technology and engineering from the Xi'an University of Technology, Xi'an, China, in 2019, where she is currently pursuing the master's degree with the School of Electronic Science and Engineering.
Her research direction is two-dimensional materials and devices.
Xun Hou is currently a Professor with Xi'an Jiaotong University, Xi'an, China, and an Academician of the Chinese Academy of Sciences, Beijing, China. His main research direction is optoelectronics.