Radiation-Induced Charge Trapping in Shallow Trench Isolations of FinFETs

We provide comprehensive experimental data and technology computer-aided design (TCAD) simulations to clarify total-ionizing-dose mechanisms in 16-nm Si FinFETs. In n-channel FinFETs irradiated to ultrahigh doses, the transconductance evolution rebounds (increase up to 3–10 Mrad followed by a decrease), while the drain-to-source leakage current steadily augments until reaching a plateau at very large doses. These effects result from positive charge trapping deep in the sidewalls of the shallow trench isolation (STI) and negative trapped charge accumulation localized in the upper STI corners. Larger sizes of inter-fin STI enhance the leakage current degradation of transistors with smaller numbers of fins. Hydrogen-induced border- and/or interface-trap generation at the Si/oxide interface at the STI corners leads to increased low-frequency noise (LFN) at doses $>{10}$ Mrad(SiO2). These results show that the quality of oxides and interfaces in the upper region of the STI adjacent to the device channel is crucial for the tolerance to ultrahigh radiation of modern FinFET technologies.

Several recent studies on MOSFET and FinFET technologies have identified the STI as the single most important issue for devices exposed to ionizing radiation, particularly at ultrahigh doses [15], [16], [17], [18], [19], [20], [21], [22].In planar Si CMOS technologies, irradiation induces positive charge buildup in the STI, which is thicker and has higher defect densities than SiO 2 gate oxides [6], [10].Positive charge in the STI increases OFF-state leakage current in n-channel FETs due to the activation of lateral parasitic transistors [9], [19], [20] and induces parametric drifts in n-and p-channel FETs.The worst case degradation is found in narrow-channel transistors due to the radiation-induced narrow-channel effect (RINCE) [6], [9], [10].For example, positive charge trapped in the STI of pFETs can lead to decreased densities of holes in regions of the device channel that are close to the STI, often leading to large shifts in the transconductance g m and threshold voltage V th of narrow pFETs [6], [9], [14], [17].Similar width-dependent effects occur in n-channel MOSFETs: positive charge in STI enhances the number of carriers (electrons) in the regions close to the STI, significantly improving g m of narrow nFETs [6], [9].
negatively charged traps outside the channel region [22], the underlying mechanisms remain unknown.
In this article, we present comprehensive experimental data and technology computer-aided design (TCAD) simulations that clarify the origin of these TID mechanisms in nFinFETs.Ultrahigh dose irradiation is used to magnify the degradation to help understand the underlying causes for the g m rebound and increase in I OFF .We find that these effects result from two mechanisms in different regions of the STI: 1) positive charge trapping in the deep STI sidewalls and 2) negative trapped charge in the upper STI corners.Buildup of negative charge depends strongly on the bias applied during irradiation, in contrast to the trapped positive charge, which is relatively insensitive to the applied bias.Low-frequency noise (LFN) measurements suggest that the negative trapped charge in the upper STI corner is most likely due to acceptor-like interface and/or border traps.TCAD simulations are presented that strongly support this interpretation of the experimental data.

A. Devices
The FinFETs under test were core transistors fabricated in a commercial 16-nm bulk CMOS technology, rated to a nominal V dd of 0.9 V.The devices were part of a custom array composed of several accessible transistors with channel length L = 72 or 240 nm.All tested transistors have the same fin width and fin height, sharing source and bulk contacts with separate drain and gate contacts.
For reference, Fig. 1(a) shows a TEM image of a single fin transistor fabricated from Taiwan Semiconductor Manufacturing Company (TSMC) 16-nm FinFET technology [33].For the devices shown in Fig. 1(a), the channel width (W ) is constant to ∼85 nm, which is calculated as 2 * h fin + w fin , where h fin is the height of the fin (∼39 nm) and w fin is the width of the fin is (∼7 nm).The image highlights two upper sides of the STI, forming two triangular SiO 2 regions, which are distinctive structural characteristics of FinFET devices.These regions will be fundamental for the following discussions and are called "STI corners."Transistors with two, five, or ten fins were tested in this study to investigate the variation of TID-induced effects with fin number (n fin ).As highlighted in Fig. 1(b) for 10-nm Intel FinFETs, the dimensions of the lateral delimiting STI oxides are larger than inter-fin STI, while the STI corners are identical regardless of delimiting or inter-fin STI [34].

B. Exposure Conditions and Measurement Setup
The irradiation was conducted using a Seifert Model RP 149 X-ray irradiator at the University of Padova, Italy, at a dose rate of 4.5 Mrad(SiO 2 )/h [35].All doses are expressed in SiO 2 .The total exposure time was ∼9 days to reach 1 Grad.After the exposure, transistors were annealed at 100 • C for 24 h.Devices were biased in three different conditions during irradiation and annealing: "OFF" (V gs = 0 V and V ds = 0 V), "ON" (V gs = 0.9 V and V ds = 0 V), and "DIODE" (V gs = 0.9 V and V ds = 0.9 V).All other terminals were grounded.
DC static characteristics of transistors were measured at room temperature before exposure, after irradiation, and after high-temperature annealing.The threshold voltage V th is calculated as V gs−int − V ds /2, where V gs−int is extracted in the linear mode of device response (V ds = 50 mV) as the gate-voltage axis intercept for a linear extrapolation of the I d -V gs curve at the point of maximum first derivative [36].LFN was measured in a frequency span between 0.5 Hz and 1 kHz at V ds = 50 mV at several values of V gt = V gs − V th .
The array structure of each tested die contained 12 nFinFET transistors fabricated with different channel lengths and fin numbers.Considering the high sensitivity of transistors to electrostatic discharge and the time required for performing an irradiation test at ultrahigh doses (∼5 days for 500 Mrad or ∼9 days for 1 Grad), at least three dies were tested in each bias condition, for a total of > 36 tested transistors per bias condition.Results in this article are presented for representative channel lengths and fin numbers, with at least two nominally identical devices evaluated for all experimental conditions.Nominally identical devices irradiated and annealed under similar conditions show parameter shifts that typically vary by less than ± 10%; dedicated tests to evaluate device-todevice variability were performed and analyzed in previous work [27].

III. DC MEASUREMENTS A. TID Tolerance at Different Bias Conditions
Fig. 2 shows the dc response for an nFinFET irradiated and annealed for 24 h at 100 • C in the ON-and OFF-bias conditions.The worst case degradation is observed when the devices are irradiated in the ON-condition, as the TID induces significant variation in the slope of the curves, i.e., the transconductance g m .In both cases, the maximum drain current increases until 10 Mrad (blue curve) and then decreases at higher doses due to the g m loss.The leakage current, defined as I d at V gs = 0 V, increases with cumulative dose by ∼100× during irradiation.Annealing at high-temperature induces an almost complete recovery of the leakage current (see the black dotted curve) with negligible effects on the transistor response at V gs > V th .The different behavior of the   3. Degradation of maximum drain current I on-lin as a function of dose for nFinFETs with L = 72 nm.I on-lin is defined as the drain current at V gs = 0.9 V with V ds = 50 mV.Devices were irradiated in different bias conditions: OFF (V gs = 0 V and V ds = 0 V), ON (V gs = 0.9 V and V ds = 0 V), and DIODE (V gs = 0.9 V and V ds = 0.9 V). leakage current and g m suggests that effects originate from two different mechanisms.
The maximum drain current I on-lin is plotted as a function of dose in Fig. 3 for OFF-, ON-, and DIODE-bias conditions.At 500 Mrad, the value I on-lin of ON-biased devices decreases by 18% versus a 5% decrease for the OFF-biased.The curves of the ON-biased (red) and DIODE-biased (green) transistors almost overlap, suggesting an insensitivity of TID effects to the lateral drain-to-source electric field.However, the significant differences between the OFF-biased devices and ON-and DIODE-biased devices show that the results are still strongly influenced by the applied gate bias.
Increases in I on-lin are observed at doses up to 10 Mrad, with a peak observed at ∼3 Mrad.Similar effects are also observed in planar MOSFET technologies [6], [9] exposed at similar dose rates.At doses above 10 Mrad, the ON-current decreases constantly in all conditions in the explored dose range.
To help identify the cause of the I ON degradation, Fig. 4 shows the radiation-induced degradation in terms of (a) maximum transconductance g m-MAX , (b) threshold voltage V th , and (c) subthreshold swing SS.Three significant effects are apparent in Fig. 4.
1) g m Rebound at 10 Mrad: Values of g m clearly increase at doses < 10 Mrad and decrease at doses > 10 Mrad.Considering the worst case, ON-biased nFinFETs g m is +5% at 10 Mrad and decreases to −15% at 500 Mrad.As the g m trend is similar to I on-lin , the dominant effect in the inversion regime is related to the degradation of the transconductance g m .
3) Influence of Irradiation Bias Condition on g m : The ONbiased devices exhibit the highest g m , meaning that the TID mechanism degrading g m is strongly influenced by the intensity of the electric field applied to the oxides.
All these dependences will be important to the discussions of degradation mechanisms in Section IV.

B. Off-Leakage Current
Fig. 5 plots I OFF as a function of accumulated dose, where I OFF is calculated as I d at V gs = 0 V with V ds = 0.9 V.In contrast to g m and I ON , I OFF shows monotonic degradation.The ON-irradiated transistors exhibit similar I OFF degradation compared to OFF-irradiated devices, as both increase monotonically by ∼100× at 500 Mrad.Inspection of all other terminals shows that leakage is flowing from drain to source.At doses > 100 Mrad, I OFF reaches a plateau and settles at about 5 × 10 −10 A, independently of the applied gate bias during irradiation.Annealing devices at 100 • C for 24 h restores I OFF to pre-irradiation values.
I OFF increases indicate positive charge trapping in the STI that activates parasitic leakage paths close to the STI sidewall, similar to effects seen in irradiated planar nMOSFETs [6], [8], [17] and FinFETs [28], [31].The I OFF plateau at doses > 100 Mrad may be induced by the saturation of positive charges in STI sidewalls at ultrahigh doses or by the equilibrium of annealing (detrapping) and trapping occurring during longtime irradiations.More importantly, the insensitivity of I OFF to applied gate bias suggests that the leakage most likely occurs in deeper regions of the STI sidewalls, where the electric field  intensity, and thus charge yield, is not influenced by V g [1], [4], [8], [15], [16], [18].

C. TID Effects Dependence on Fin Number
We evaluated the dependence of the TID response on the number of fins by testing nFinFETs fabricated with different fin numbers and the same channel length (L = 240 nm).The devices were irradiated up to 500 Mrad in the ON-bias, i.e., worst case bias condition.Fig. 6(a) shows the g m degradation of nFinFETs with 2, 5, and 20 fins.The curves nearly overlap, indicating practical insensitivity of g m to the number of fins.At 500 Mrad, values of g m are −12%, −10%, and −11% for 2-, 5-, and 20-fin transistors, respectively.As in Fig. 4(a), all devices exhibit positive g m shifts at doses < 10 Mrad and turnaround at ∼10 Mrad, with g m decreasing at ultrahigh doses.
In contrast, I OFF degradation depends strongly on the fin number of the transistors.Fig. 6(b) shows I OFF normalized by its initial value (I OFF /I off-pre ) for nFinFETs with 2, 5, and 20 fins.Worst case is found for transistors having two fins (blue curve).These show an I OFF increase  annealing induces an almost complete recovery of I OFF , similar to the results in Fig. 5.The dependence of I OFF is most likely induced by the higher volume oxides of lateral STI compared to intra-fin STI [see Fig. 1(b)], similar to the fin dependence found in p-channel FinFETs [21].Enhanced positive charge densities in the lateral STI may induce higher I OFF degradation in the first and last fins in sequences, compared with those in central positions.Consequently, transistors with low numbers of fins have relatively higher I OFF degradation compared to transistors having higher numbers of fins.
The differing g m and I OFF dependences on numbers of fins highlight that significant TID degradation can occur in two different regions of STI.In particular, I OFF is evidently induced by positive charges trapped in deep regions of the STI sidewalls, as suggested by its dependence on fin number and its relative independence of irradiation bias.On the other hand, g m may be induced by negative trapped charge buildup in the upper corners of the STI, as suggested by its independence of fin number and its strong dependence on irradiation bias.
Fig. 7(a) and (b) shows the LFN response of nFinFETs irradiated and annealed in the ON-and OFF-bias conditions, respectively.The FinFETs show 1/ f noise with typical deviceto-device variability [37], [38].In ON-biased devices, the noise is approximately constant after 10 Mrad and increases at 500 Mrad.This LFN increase indicates activation of new traps, as the channel and newly generated defects localized in the near-interfacial gate oxide can exchange charge through tunneling and/or thermally assisted processes, which allows for the capture/emission of electrons by border traps [37], [38], [44].Recent revaluation of LFN also shows a potentially significant role for hydrogen-mediated defect activation and passivation in LFN for some devices, e.g., via the alternating defect activation and passivation of interface traps at the semiconductor/oxide interface [47], [51].As a consequence, increases in LFN noise magnitudes at doses > 10 Mrad indicate the generation of border traps and/or increases in intensity of hydrogen-assisted defect activation and passivation processes at Si/oxide interfaces [37], [47], [51].It is worth noting that the significant increase in magnitude of LFN does not occur until g m begins to drop, after 10 Mrad [see Fig. 4(a)].High-temperature annealing in Fig. 7 (blue curve) slightly increases the LFN, again in agreement with the slight changes in g m after annealing.In contrast, OFF-biased FinFETs show stable LFN response, which is relatively insensitive to cumulative dose.Fig. 8 plots the LFN magnitude at 10 Hz as a function of V gt = V gs − V th for nFinFETs irradiated in the ONbias condition.When the slope |β| of the noise versus V gt curve is approximately equal to 2, the effective density of the traps is uniform in space and energy [37], [39], [40], [42].In pristine and in devices irradiated to 10-Mrad, |β| is ∼2, indicating an approximately uniform spatial and energetic trap distribution.At 500 Mrad, the noise increases significantly and |β| is ∼1.6, indicating that the newly generated traps are less uniform in space and energy than the defects leading to the noise in the as-processed devices.For annealed devices, the S Id -V gt curve shows a slight increase in magnitude at low V gt with |β| of ∼1.6, while |β| is ∼2.1 for high V gt .Hence, there is not only an increase in effective defect density during irradiation and annealing but also a change in spatial and energy distribution [37], [38], [44].
Fig. 9 shows the noise at 10 Hz as a function of dose for transistors of L = 240 nm with different fin numbers.The noise magnitude scales inversely with channel area, i.e., the number of fins, and increases with dose [37], [38], [48].The LFN magnitude of all FinFETs increases substantially after 100 Mrad(SiO 2 ), similar to the g m drop in Fig. 4(a).The increase of LFN is independent of the number of fins, as all FinFETs exhibit a 4× increase in the LFN magnitude.
We conclude that, in ON-biased transistors, the LFN measurements at doses > 10 Mrad and subsequent hightemperature annealing indicate the activation of border and/or interface defects, which are spatially and/or energetically nonuniform, and independent of fin number.These results all suggest that the increase in noise is most likely due to the trap activation processes related to the STI corners [38], [47], [52], [53], [54], which lead to the decrease in g m for similar dose and annealing conditions.

V. MECHANISMS IDENTIFICATION AND DISCUSSION
Based on the above experimental results, we have proposed TID-induced mechanisms that could justify the evolution of g m and I ON at high doses in Figs. 3 and 4. Silvaco TCAD simulations are now presented to illustrate how these basic mechanisms influence the electrical response of the transistors.The results provide strongly supporting evidence for the following sequence.
1) First Mechanism: It is fast generation of positive charge, holes, and H + , in the SiO 2 of STI.This mechanism is responsible for the g m increase at doses < 10 Mrad and for the continuous I OFF increase.
2) Second Mechanism: It is slow activation of donor-like traps, capable of trapping negative charge in the upper corners of the STI [see Fig. 1(a)].This mechanism is responsible for the g m decrease at doses > 10 Mrad and the increase of the LFN magnitude.
Charge trapping in the STI can contribute to the LFN of devices, as reported in [52], [53], and [54].Fig. 10 shows a Silvaco TCAD model developed through the Devedit and Deckbuild tools, including the Atlas and Victory Process.The geometrical structure is based on TEM images shown in Fig. 1 with meshing optimized close to the material interfaces.The gate-stack is formed by ∼2 nm of HfO 2 (brown), ∼6 nm of Al (gray), and a thick layer of Ti (green).Doping profiles in the Si channel have been retrieved from publicly available information and set to 10 16 cm −3 of B in the channel region [26].All the physics for modeling the semiconductor device are set to the default Silvaco parameter values.The color scale in Fig. 10 indicates the electric field intensity E when V gs = 0.9 V.The FinFET layout introduces distinctive regions visible as triangular oxide regions in the upper STI corners, which are characterized by the highest values of electric fields.This agrees well with the strong influence of bias on g m in Fig. 4(a).It is likely that the negative charge formation (mechanism #2) may be related to H + transport and dehydrogenation processes at the Si/SiO 2 interface [12], [13], [55], [56], [57], [58], [59], [60], [61], leading to the accumulation of negatively charged interface traps in the STI corners.Interface-trap formation in the STI corner is enhanced under high electric fields as in the cases of ON-and DIODEbiases, as shown also by LFN measurements.This contrasts with results for OFF-bias, for which electric fields are small in the STI corners.
Fig. 11 shows the proposed TID-induced mechanisms degrading g m .TCAD simulations are performed in nFinFETs at V gs = 0.9 V (channel ON).The color scale indicates the electron density in the Si channel fin.TID effects were simulated by adding fixed charges in specific regions of the STI oxide [15], [16], [18], [62].Positive charge was added as fully ionized donor traps (Q STI ), which are uniformly distributed throughout the STI, in agreement with the relatively small electric field reaching the STI sidewalls.Negative charge, accounting for mechanism #2, was added as fully ionized acceptor traps (Q e− ) uniformly distributed at the Si/STI interface from the top STI corner down to a depth of 15 nm, represented by the red regions of Fig. 10 under the highest electric field.
In the pre-irradiation condition in Fig. 11(a), the channel region is inverted, and the fin is characterized by a high density of electrons.Q STI = 5 × 10 17 cm −3 , in agreement with typical expected charge trapping in the STI [14], [63].Positive charge enhances the effective height (h eff ) of the device channel, which extends a little deeper into the fin substrate.Fig. 11(c) simulates ultrahigh dose effects, considering the contribution of negative trapped charge in the STI corners at Q e− = 7.5 × 10 12 cm −2 , which is in the range of density of interface traps expected at STI corner/semiconductor interfaces [13], [19], [64].This negative charge compensates for the effect of positive charge, depleting the Si channel region near the STI corners and thus reducing h eff .
Variations in h eff that occur as a result of radiation-induced charge trapping in the STI are highlighted in Fig. 11(d), which shows the electron density as a function of fin depth, evaluated at a cutline at 1 nm from the Si/SiO 2 interface.The depth of 0 nm corresponds to the top of the fin, with the increase in value moving down in the fin substrate.Depths with high e − densities [> 5 × 10 18 cm −3 ; see dotted line in Fig. 11(a)] identify h eff , corresponding to inverted Si regions.For example, before irradiation (black curve), h eff is ∼55 nm.The value of h eff increases to ∼59 nm when positive Q STI = 5 × 10 17 cm −3 is added, and the value of h eff decreases to ∼46 nm when negative Q e− = 7.5 × 10 12 cm −2 are added in addition to Q STI .
The initial increase of h eff in Fig. 11(b) and the associated reduction of h eff in Fig. 11(c) agree well with the turnaround of the experimental g m visible in Fig. 4(a), as g m is approximately proportional to the effective channel height h eff .Modulation of h eff may occur due to both positive charges in STI and negative charges in the STI corners.The simulation results in Fig. 12 highlight the h eff modulation effect induced by several densities of Q STI and Q e− .In Fig. 12(a), the electron concentration is plotted for different densities of Q STI .Positive charges in the STI contribute to enhancement of the inversion layer close to the upper corner of the STI, thus increasing h eff .In Fig. 12(b), the effects of electron trapping in the STI corner are studied for different densities of Q e− when positive charges are trapped in the STI (Q STI = 5 × 10 17 cm −3 ).The plot highlights the effects induced by negative charges on the h eff .The black curve refers to only positive trapped charge, representing the condition at 10 Mrad with the highest h eff .By increasing densities of compensating trapped negative charge in the STI corners, h eff decreases with slight changes in electrical response of the main channel, consistent with the constant V th and SS in Fig. 4.
The slight increase of the SS and increase of the LFN at doses > 10 Mrad suggest that the nature of the negative charges of mechanism #2 is most likely interface traps, whose generation is typically slow, electric field driven, and temperature dependent [55], [57], [58], [59], [60], [61].Moreover, the amphoteric nature of interface traps [65], [66] fits with this explanation of both g m and I OFF degradation.As shown by the band diagram of Fig. 13, interface traps located at the STI corners are negatively charged when the channel is in inversion, causing a drop in g m .
In contrast, these interface traps are partially filled when devices are in the subthreshold region, thus affecting much less I OFF , for which the increase relies primarily on positive charges trapped in the STI sidewalls.The interface traps at the STI corners can be partially filled with positive or negative charges, depending on the position of the Fermi energy with respect to the intrinsic level of Si.The mechanism increasing the I OFF current is shown in Fig. 14 through simulations at V gs = 0 V (channel not inverted).The color scale indicates the electron density in the Si channel fin, as in Fig. 11.In Fig. 14(a), the p-substrate region is in accumulation, having an e − density of 10 10 cm −3 .In Fig. 14(b), positive charge (Q STI = 5 × 10 17 cm −3 ) is added in the STI, leading to an increase in e − density in the Si regions close to STI sidewalls.These Si regions with high e − density activate two parasitic leakage paths deep in the STI sidewalls, responsible for the increase of I OFF [8], [15], [16], [18], [26].Fig. 14(c) represents the case, in which the Fermi level is higher than the intrinsic level, thus the case with negative trapped charge.Even at relatively high Q e− = 7.5 × 10 12 cm −2 , the parasitic transistors are still activated, in agreement with the continuous increase of the I OFF of Fig. 5.This effect is highlighted in Fig. 14(d), which shows e − density as a function of fin depth.The peak in e − density is found in the deep Si regions, before and after negative Q e− charge is added in the STI corners.The height of the e − density peak depends mainly on Q STI but can still be slightly influenced by Q e− .In conclusion, in the case of partially filled positive interface traps or in the case of Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
partially filled negative interface traps, the parasitic transistors located in the deep Si regions are still conducting, leading to the I OFF increase visible in Fig. 5.

VI. CONCLUSION
The results of this work clarify the nature of TID mechanisms in n-channel FinFETs, identifying critical TID issues related to charge trapping in the upper corners of STI oxides.The 16-nm Si nFinFETs irradiated up to ultrahigh doses exhibit a turnaround in g m above 3-10 Mrad and a continuous increase in drain leakage current at higher doses.Worst case degradation is found when positive bias is applied to the gate, with V th and SS relatively insensitive to accumulated dose.
Experimental results, combined with TCAD simulations, identify two different dominating TID mechanisms that induce nonuniform charge trapping in the STI oxides.The first mechanism is related to positive charge trapping in the STI sidewalls.Positive charge causes a monotonic increase of the drain-to-source leakage current and improves g m due to an increase in the effective channel height.The larger dimensions of the lateral STI oxides compared with the smaller dimensions of intra-fin STI enhance the relative I OFF degradation of transistors with a smaller number of fins.On the other hand, a second slower mechanism appears at doses > 10 Mrad causing the formation of negative trapped charge in the upper corners of the STI.The negative charge compensates the effect of positive charges and degrades the transistors g m due to the reduction of the effective channel height.The generation of border/interface traps and the activation of hydrogen-assisted processes at Si/oxide interface lead to significant increases in LFN at doses > 10 Mrad.These results resolve several puzzling issues from previous studies of FinFETs at ultrahigh radiation doses, and point to the need to continuously monitor and improve the channel/STI interfaces of advanced MOS technologies.

Fig. 2 .
Fig. 2. Radiation-induced degradation of I d -V gs curves in the linear regime (V ds = 50 mV) for nFinFETs with L = 72 nm.The devices were irradiated and annealed at 100 • C for 24 h in (a) ON-bias and (b) OFF-bias conditions.

Fig.
Fig.3.Degradation of maximum drain current I on-lin as a function of dose for nFinFETs with L = 72 nm.I on-lin is defined as the drain current at V gs = 0.9 V with V ds = 50 mV.Devices were irradiated in different bias conditions: OFF (V gs = 0 V and V ds = 0 V), ON (V gs = 0.9 V and V ds = 0 V), and DIODE (V gs = 0.9 V and V ds = 0.9 V).

Fig. 4 .
Fig. 4. Degradation of (a) maximum transconductance g m-MAX , (b) threshold voltage V th , and (c) subthreshold swing SS, as functions of dose in nFinFETs with L = 72 nm.Transistors were irradiated and then annealed for 24 h at 100 • C in the OFF-and ON-bias conditions.Measurements are carried out at room temperature in the linear regime (V ds = 50 mV).

Fig. 5 .
Fig.5.Increase of drain leakage current I OFF at V ds = 0.9 V as a function of cumulative dose for nFinFETs with L = 72 nm.Transistors were irradiated and then annealed for 24 h at 100 • C in the OFF-and ON-bias conditions.

Fig. 6 .
Fig. 6.Influence of the number of fins on TID-induced effects as a function of dose (a) g m−lin and (b) I off /I off-pre .nFinFETs with L = 240 nm were irradiated up to 500 Mrad(SiO 2 ) and annealed at 100 • C for 24 h in the ON-bias condition.I d -V gs curves of unpassivated GaN-based HEMTs in the saturation regime (V ds = 5 V).The devices were irradiated up to 100 Mrad(SiO 2 ) and then annealed at room temperature for 27 h in (a) "cut-off"-bias and (b) the "on"-bias.of∼10× after 500 Mrad versus ∼2.5× for the 20-fin devices (the increase of 100× reported previously was for the shorter L = 72 nm transistors).In all cases, high-temperature

Fig. 7 .
Fig. 7. LFN response for nFinFETs with L = 240 nm and n fin = 2. Devices were irradiated up to 500 Mrad(SiO 2 ) and annealed at 100 • C for 24 h in (a) ON-and (b) OFF-bias conditions.The noise was measured at V ds = 50 mV and V gt = 0.2 V at room temperature.

Fig. 8 .
Fig. 8. 1/f noise magnitudes at f = 10 Hz versus V gs -V th at V ds = 50 mV for nFinFETs with L = 240 nm.Devices were irradiated up to 500 Mrad(SiO 2 ) and then annealed in the ON-bias condition.

Fig. 9 .
Fig. 9. LFN magnitudes for nFinFETs with L = 240 nm and several fin numbers.Devices were irradiated and annealed in the ON-bias condition with noise measured at V ds = 50 mV and V gt = 0.2 V at room temperature.The out-of-trend increase of LFN of 20-fin device at 100 Mrad is most likely caused by higher-than-normal contact noise during this test.

Fig. 10 .
Fig. 10.TCAD simulation of the nFinFETs for V gs = 0.9 V.The color scale indicates the intensity of the electric field in the STI, while the black arrows show the direction of the electric field.
Fig. 11(b) simulates the condition at 10 Mrad, when positive charges are trapped in STI with

Fig. 11 .
Fig. 11.TCAD simulation of nFinFETs when V gs = 0.9 V (channel ON).The images show TID-induced mechanisms degrading g m−max .The color scale illustrates the electron density in the Si channel fin.(a) Pre-irradiation without trapped charges in the oxides.(b) At high doses with positive trapped charge in STI (Q STI = 5 × 10 17 cm −3 ).(c) At ultrahigh doses with positive and negative trapped charge (Q STI = 5 × 10 17 cm −3 and Q e− = 7.5 × 10 12 cm −2 ).Q STI 's are uniformly distributed in the STI, while Q e− 's are localized at the Si/SiO 2 interface close to the upper corners of the STI.(d) Plot shows the electron density in the Si fin as a function of fin depth [coordinate y in (a)], considering the cutline shown in (a), i.e., at 1 nm from the Si/SiO 2 interface, with Q STI = 5 × 10 17 cm −3 and Q e− = 7.5 × 10 12 cm −2 .

Fig. 12 .
Fig. 12. TCAD simulations of nFinFETs when V gs = 0.9 V (channel ON).The plots show electron density concentrations as functions of fin depth along the cutline in Fig. 11(a), showing the modulation of the effective channel height h eff .(a) Several densities of positive charge Q STI are shown, with Q e− = 0 cm −2 .(b) Several densities of negative charges Q e− are shown, with Q STI = 5 × 10 17 cm −3 .

Fig. 13 .
Fig. 13.Simulated band diagrams as a function of fin depth, considering the cutline shown in Fig. 11(a), i.e., at 1 nm from the Si/SiO 2 interface.The band diagram refers to an nFinFET biased with V gs = 0.9 V. Continuous line refers to the pre-irradiation condition and dotted lines refer to Q STI = 5 × 10 17 cm −3 and Q e− = 7.5 × 10 12 cm −2 .The plot shows that interface traps located in the STI corner are charged negatively, as the Fermi level is above the intrinsic level.

Fig. 14 .
Fig. 14.TCAD simulation of nFinFETs when V gs = 0 V (channel OFF).The images show TID-induced mechanisms increasing the I OFF current.The color scale shows the electron density in the Si channel fin.(a) Pre-irradiation without any trapped charge in the oxides.(b) At high doses with positive trapped charge in STI (Q STI = 5 × 10 17 cm −3 ).(c) At ultrahigh doses with positive and negative trapped charge (Q STI = 5 × 10 17 cm −3 and Q e− = 7.5 × 10 12 cm −2 ).Values of Q STI are uniformly distributed in the STI, while the Q e− values are localized at the Si/SiO 2 interface close to the upper corners of the STI.(d) Electron density in the Si fin as a function of fin height, considering the cutline shown in Fig. 11(a), i.e., at 1 nm from the Si/SiO 2 interface.