Threshold and Characteristic LETs in SRAM SEU Cross Section Curves

Characterizing the sensitivity of a static random access memory (SRAM) to single-event upset (SEU) is an essential task for assuring its soft-error reliability. However, this task often imposes a burden because it usually requires many cycles of accelerator-based irradiation tests. A model recently proposed is a very simple exponential-type equation but has strong potential to reduce the burden because of its capability to predict SEU cross sections in various conditions. The aim of the present study is to revisit the model in terms of threshold parameters called threshold linear energy transfer (LET or $L$ ) and critical charge. Although these threshold parameters are widely used as key parameters that describe whether an SEU occurs or not, they are not seen in the model. This article explores such missing threshold parameters, suggesting that they successfully appear by introducing a factor of five to the original expression.


I. INTRODUCTION
R ADIATION is a famous source of soft errors in staticrandom access memories (SRAMs) [1], [2], [3], [4], [5], [6], [7]. Even a single strike of particle radiation such as alphaand cosmic-rays may induce noise charge that can overwhelm the noise margin of SRAM cell, leading to an undesired flip from a logic "1" or "0" originally kept in the cell to its counterpart. The causal radiation strike and the resultant flip are called single event (SE) and single-event upset (SEU), respectively.
Characterizing SEU sensitivity is of primary concern for assuring SRAM soft-error reliability. This process often involves cross section curves as exemplified in Fig. 1. The curve offers the evolution of SEU cross section (σ ) of SRAM cell as a function of linear energy transfer (LET or L) of impinging radiation (LET expresses the linear charge density generated along the track).
For silicon-on-insulator (SOI) SRAMs, we recently proposed the following model to describe this curve [8]: See Table I for the symbols. This model is similar to others, such as the Weibull [9] and the Edmonds [10]  Cross section curves of an SOI SRAM measured (symbols) and predicted (lines) under two voltage conditions (after [8]). The tested SRAM was fabricated in a 65-nm process, not hardened by design. Once β was determined through a fit with the 1.2-V data, the model successfully predicted the 0.75-V data without any parameter adjustment.
is unique because all the parameters are physically clear and familiar to SRAM SEU researchers. In [8], this model showed its wide applicability to various SOI SRAMs andwith a slight modification from βd SOI to the well-known funnel length-to other bulk-type devices. The aim of this article is to address an issue remained in the previous study. The model was derived on an assumption that the exponential term can be written as e −L T /L (see in Section II for details) where L T represents a threshold LET, which describes the condition for SEU whether impinging radiation produces enough charge or not. In this context, the model should have yielded σ ≈ 0 when L = L T but actually yields 1/e = 0.37 of saturated value, which seems too large to qualify as zero. Rather, together with a characteristic LET (L e ) that accounts for 1/e, the model should be expressed as The threshold L T is no longer seen. This disappearance should be addressed because L T is the most critical parameter in softerror reliability assessments.

II. REVIEW OF THE ORIGINAL DERIVATION
In the previous study [8], the derivation started from our experimental finding shown in Fig. 2. At a given L, as commonly observed in SRAM SEUs, σ exponentially responds to the power supply voltage V DD (i.e., σ ∝ e −kV DD ), where k is a slope parameter dependent on L but not on V DD . Our analysis further suggested that the "straight lines" (on the semilogarithmic chart) are expected to converge on a point P  where V DD = V DR because this point turns the SRAM staticnoise margin to zero [12]. At this point, in theory, the entire region of the cell should be sensitive to any radiation strike, and thus, In this transformation, another finding in an analysis of Fig. 2 was used that k ≈ k 0 /L where k 0 is a coefficient independent of L or V DD . Equation (3) was associated with the following facts. 1) Bark et al. [13] suggest that cross section curves can be normalized by using L/L T . 2) Edmonds [10] proposes, with constants B 1 and B 2 3) Researchers (e.g., [14]) often use a variant of Hazucha and Svensson model [1] σ Here Q C and Q col represent critical and collected charge, respectively. The meaning of the fraction Q C /Q col is essentially the same as L T /L. It expresses the SEU condition whether a node collects charge (Q col ) larger than a critical value for SEU (Q C ). Q C is well known to be proportional to C L V DD . Recently its proportionality constant was found to be determined by the circuit loading effect and constant across technology generations [7]. This finding resulted in where ζ = 2 across generations. For SOI SRAMs, historically, Q col is often given by Starting material of the model derivation [8]. SRAM σ measured under various L and V DD conditions were supposed to converge on the point P where V DD = V DR . Measurement data were taken from heavy-ion tests with the 65-nm SOI SRAM [12], [15]. Therefore, Comparing (3)- (8), we derived the model (1). Note that in the comparison we also assumed that Q C ≈ C L V DD ≈ C L (V DD − V DR ) and adapted A to A/2, taking into account that half of the transistors that make up a cell are OFF and sensitive to SEU.

III. HYPOTHESIS
It is known that the definition of L T varies across papers [16]. Fitting of a Weibull function is one of the most popular ways to extract L T . Another famous approach is to identify L corresponding to σ equal to 1/100 of its saturated value [16]. Following this 1/100-based definition, we propose a hypothesis that which turns the original expression (1) into Note that 4.6 should be used rather than 5 to make 1/100 precisely (∵ e −4. 6 = 0.0101 whereas e −5 = 0.0067). In this study, we have selected 5 for sightly expression. Our survey in the literature could not find strict physical or mathematical reason to use the exact value of 1/100.

IV. EXPERIMENTAL
Numerical device simulation was used to investigate the validity of the hypothesis. Although the previous study [8] showed the good applicability of the original expression to various SRAMs (without the factor of 5), the study relied on literature data. Some of the model parameters were not available explicitly and hence estimated through fits of data and surveys of information about similar SRAMs. To exclude such parametric uncertainty, numerical device simulation was chosen as a main tool for investigation in the present study. Simulations were all conducted in the HyENEXSS technology computer-aided design (TCAD) platform [17].

A. SRAM Cell
A typical six-transistor SRAM cell was investigated (see Fig. 3), which was supported by no radiation hardening by design (RHBD) such as RC hardening [18]. The cell was kept in a retention mode for logic "1" where the access transistors (A 1 and A 2 ) were both OFF while the internal nodes were precharged at V 1 = V DD and V 2 = 0 V. The two bit-lines were fixed at V DD . Thereby, the OFF-state N 1 , P 2 , and A 2 were sensitive to SEU.
The entire cell was modeled as a numerical device, as with [19] and [20]. Fig. 4 illustrates the layout of the cell. Some key dimensions, such as the gate lengths and widths are also presented. The six transistors were placed on a 10-nm-thick SiO 2 film corresponding to a buried oxide (BOX) film. For reduced computational cost, the bottom Si substrate beneath the BOX layer was removed and represented by electrodes (i.e., Dirichlet boundaries) with electron affinities of doped Si (see Fig. 5). A buried-well structure was assumed to make the bottom Si-electrodes. Recent SOI SRAMs often have p-and n-type wells beneath the BOX film for dynamic optimization of power and speed penalties [21], [22], [23], [24].
The SOI SRAM examined in the present study was not a replica of any real existing SRAMs. The dimensions and other parameters such as doping concentrations were values   [21], [22], [23], [24]. Structural simplifications were further applied. For example, the access transistors (A 1 and A 2 ) had the same width as that of the pull-down n-type transistors (N 1 and N 2 ). They are usually different in real SRAMs for proper read and write operations. Using the same width for these transistors helped to reduce the number of mesh and computation time (the simulator relies on orthogonal meshing).
The thickness of all the transistor regions on the BOX film was constant at d SOI of 10 nm. No raised source/drain structure was used. Each transistor had an undoped body region (specifically, channel doping was set at 10 15 cm −3 ). The body region was sandwiched by the source (S) and drain (D) regions with a constant abrupt doping profile of 10 20 cm −3 . The gate-stack consisted of a 1.5-nm-thick SiO 2 film covered by a metal gate. The metal gate was modeled as a Dirchlettype electrode, as with the Si substrate. The work function of each metal gate was adjusted to make the threshold voltage of both p-and n-type transistors ∼0.3 V in magnitude (measured by a constant-current method [25], [26]). Gate spacer regions and lightly-doped drain-source regions were omitted.
All the transistors were virtually interconnected. Metal wires to connect transistors were modeled in the mixed-mode framework.
Only the fundamental equation set that is an ensemble of the Poisson equation and the current-density equations was solved under the assumption of constant mobilities. Other detailed physics were omitted, such as impact ionization, band-gap narrowing, and generation and recombination of carriers.
Resultant parameters for the model (except for β) are summarized in Table II. V DR of 0.05 V is a simulation result of butterfly curves under various V DD (see Fig. 6). The constant factor of two is still used for ζ . The other parameters are straightforward estimations from the structure.

B. Single Event
The SE was assumed to be perpendicular to the top surface of the cell (see Fig. 5). A constant LET was also assumed. It deposited noise charge (electron and hole pairs) along the track constantly. The radial distribution of charge density (ρ) was modeled as where t and r represent the elapsed time and the distance from the strike position, respectively. The delta function δ(t − t 0 ) dipicts the time-dependent distribution of charge.
In the present study, t 0 was fixed at 1 ps. The Gaussian function describes the radial distribution of charge. The characteristic radius (r 0 ) was assumed to be 50 nm [27]. The first fraction is a coefficient to satisfy ∞ 0 ∞ 0 (14) dtdr = L. Scanning the strike position produced an SEU map that visualized where SEU occurred, as exemplified in Fig. 7. Counting the strike position of SEU resulted in σ . A constant 20-nm step was used in the scan. This finite step resulted in the uncertainty of resultant σ . Note that the uncertainty provides no statistical information. It is a spatial discretization error (see Appendix A). The accuracy of the simulation in terms of L was also examined and expected to be within 10% (see Appendix B).

V. RESULTS AND DISCUSSION
A. Validity of the Hypothesis   L increasing, σ monotonically increased and saturated at a certain value. The saturated value was (0.7 ± 0.2) × 10 −9 cm 2 , indicating that L 1/100 = L T ≈ 0.03 fC/nm. Together with other parameters in Table II, the obtained L T straightforwardly yielded β of 1.1 for the hypothesized expression (10). Using this β, the expression (10) successfully traced the simulation results for V DD = 1.0 V (see Fig. 8) and predicted the results for the cases where V DD was scaled down to 0.6 V and further deeply to 0.3 V (see Fig. 9).
Note that the revealed agreements between the model and simulation results do not provide insight into the existence of the factor of 5. This is because the original expression (1) can also trace the simulated cross sections-even without the factor of 5-when β is divided by 5 and adapted to 0.23 (a slight difference from 0.22 or 1.1/5 is a simple round-off error). The following detailed analysis, however, provides support for the existence of the factor of 5, while highlighting the importance of the use of numerical device simulation, i.e., the advantage of device simulation that enables monitoring signals on SRAM internal nodes, which are never accessible in real SRAM measurements. Fig. 10(top) shows the evolution of voltage signals V 1 and V 2 monitored for the case where L = 0.03 fC/nm and V DD = 1.0 V. The strike position was located at the center of N 1 , corresponding to the sole SEU position for this L and V DD condition (see Fig. 7). Note that the position expressed here as "center" is located at x = 0.15 µm and y = 0.47 µm. Due to the 20-nm constant resolution, this position is slightly shifted to the drain side by 0.005 µm from the exact geometrical center of the transistor (x = 0.15 µm and y = 0.475 µm). This slight difference is ignored in this study for merely simplicity of explanation.
The voltage transients indicated a flipping time of t F = 6.8 ps, according to [11], where the second inverter output (V 2 ) exceeded the first inverter threshold voltage (0.50 V). During this flipping process [28], as shown in Fig. 10(bottom), N 1 drain terminal collected 0.41 fC, which provided β = 1.3 (∵ β = Q col /Ld SOI ). This β shows a good agreement with the value extracted from the cross section curve with the factor of 5, as summarized in Table III, justifying the hypothesis.
Since (11)-(13) do not have fabrication process dependent parameters, the hypothesis is expected to be applicable to bulk SRAMs. In fact, the factor of five accounts for the cross section curve of a recent bulk fin field-effect transistor (FinFET) SRAM, as shown in Fig. 11, where our expression (12) is compared with experimental data reported in [29]. For comparison, the authors of the present study converted the original SEU cross sections given in the reference into the event cross sections, taking into account the multicell upset (MCU) multiplicity, which is also given in the article referred to. This is because our model is expected to be suitable to describe the phenomenon that occurs inside the cell [8]. In the model, in fact, σ is limited by the total sensitive transistor area A. Actual SRAMs, however, may suffer from MCUs, exhibiting SEU cross sections larger than the limitation. Deviation is often evident in bulk SRAMs because of charge collection from the outside of the cell through the substrate [30]. The event cross section is a metric for eliminating such an "outer effect," being calculated by the number of events irrespective of multiplicity, i.e., the number of upsets in each single-event [31]. Fig. 11 demonstrates that the resultant event cross section is well explained by (12) in spite of no fit operation. In other words, the maximum event cross section (2 × 10 −10 cm 2 ) revealed in the figure was simply substituted for A/2. L T was estimated to be 0.012 fC/nm (corresponding to the left bottom point) through the 1/100-based definition and directly given to the equation. These two parameters could explain the bulk experimental result thanks to the existence of the factor of 5.

B. Potential for Estimating β From Single-Transistor Testing
In addition to the input and output parameters L and σ , as summarized in Table I, the model relies on seven characteristic  parameters. Six of them are structure and voltage parameters, which can be measured without using radiation. The rest parameter β is the sole parameter that needs an analysis of the result of SRAM radiation test. SRAM radiation testing is often a burden because it requires the exposure of fully functional chip to radiation. It would be helpful if β can be estimated easily from simple parts other than fully functional SRAM chips. In this regard, this section investigates the potential for estimating β from single-transistor measurements.
As mentioned in the previous article [8], similar β are widely extracted from responses of single transistors. A transistor is situated and exposed to SE in the OFF state with its drain terminal biased at V DD . The drain terminal collects Q col(Tr) = ∞ t0 I D dt (15) where I D represents transient drain current, which can be measured with a proper apparatus [32], [33], [34], [35]. The bipolar gain for this transistor is then given by To investigate β Tr , we performed another numerical device simulation (see Fig. 12). In the simulation, the structure of N 1 was exactly copied from the SRAM cell and situated in the OFF state where its drain terminal was constantly biased at V DD while the others grounded. The simulated single-N 1 response exhibited Q col(Tr) of 0.30 fC under the same SE condition as that investigated in Fig. 10. The resultant Q col(Tr) of 0.30 fC corresponds to β Tr = 1.0, which is almost the same as those obtained by integrating the SRAM internal current and extracted by using the factor of 5 (see Table III). As a result of the introduction of the factor of 5, the favorable agreement has appeared, suggesting a possible estimation of β for the SRAM cross section curves from single-transistor drain-current measurements. This possible estimation would be worth a future investigation.

VI. CONCLUSION
The common 1/100-based definition of threshold LET (L T ) for SEU cross section curves suggested a missing factor of 5 in the original expression. This suggestion turned into a hypothesis that L T = L e /5, where L e expresses a characteristic parameter that determines the exponential slope. This hypothesis was supported by the results of the numerical device simulation. A comparison with experimental data also suggested its validity. Therefore, this factor is recommended, and the expression for the model should be revised as follows (see the text for the symbols): The introduction of the factor of 5 also suggested a possible estimation of the bipolar gain β for the SRAM cross section curves from single-transistor drain-current measurements.

APPENDIX A UNCERTAINTY OF σ
Suppose a map shown in Fig. 13(top), which exhibits a cluster of five SEU points in a scan with a constant step of a nm. The number of five straightforwardly yields σ 0 = 5a 2 , as illustrated in the figure (middle and left). We used this value as a representative value of cross section and plotted by a symbol in Figs. 8 and 9. We then estimated the upper bound (σ U ) from the minimum ring of No SEU points that surrounds the SEU points [ Fig. 13(bottom and right)]. On the other hand, the lower bound (σ L ) was estimated from the maximum ring of SEU points (bottom and left).
There might be a statistically better way to estimate the upper and lower bounds. Our method is, however, easy to be implemented in a computer code. The bounds can be identified by scanning a square "S", which is defined by four adjacent SE strike points [ Fig. 13(middle and right)]. Each square "S" has the area of a 2 and is classified with how many of its four corners are SEU points (n). Counting the number of squares with n = 4 provides σ L whereas σ U with 0 < n ≤ 4.

APPENDIX B UNCERTAINTY OF L
We conducted a preliminary simulation experiment using the N 1 transistor. The amounts of charge deposited in N 1 under various SE conditions were then extracted and compared with values theoretically estimated from (14). We confirmed that their differences overall ranged within 10%. Note that in the extraction of deposited charge, a hole counting technique was used [36]. In the present study, counting holes at the drain and source terminals of N 1 provides the amount of charge deposited in it. This is because the number of holes deposited inside the transistor is expected to be preserved, in theory (unless other computational errors occur), thanks to the omission of generation and recombination processes. The holes are then discharged from the transistor region and detected at the source and drain terminals.