Design of a Cost-Efficient Monostatic Radar Sensor With Antenna on Chip and Lens in Package

This work presents a <inline-formula> <tex-math notation="LaTeX">${D}$ </tex-math></inline-formula>-band monostatic radar system operating from 144.6 to 161 GHz, which is placed inside a 3-D-printed low-cost case with a built-in lens to boost the antenna (ANT) directivity. The monolithic microwave integrated circuit (MMIC) is manufactured in a 130-nm BiCMOS process and includes a compact transceiver architecture consisting of an oscillator, a diode-based mixer, and an on-chip antenna. The implemented topology allows to significantly improve the signal-to-noise ratio and features a built-in self-test (BIST) structure with the possibility to provide on-chip antenna characterization using power sensors in combination with a directional coupler. Housed inside the robust printed package, the MMIC has only dc and baseband frequency connections, which offers ease of handling and poses the low-cost potential for a variety of applications. The complete transceiver chip consumes only 84.7 mA from a 3.3-V supply and its size is 1964 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times1448\,\,\mu \text{m}$ </tex-math></inline-formula>. Together with the package the sensor measures a size of 42.2 mm <inline-formula> <tex-math notation="LaTeX">$\times42.2$ </tex-math></inline-formula> mm <inline-formula> <tex-math notation="LaTeX">$\times45.7$ </tex-math></inline-formula> mm.

In terms of area consumption, monostatic transceivers are attractive, as they use only one antenna for transmitting and receiving. Hence, the compact diode-based transceiver topology introduced in [4], which improves the signal-to-noiseratio by omitting a coupler and its associated losses [5], [6], is extended by built-in self-test (BIST) circuits and an on-chip antenna to enable an innovative cost-efficient sensor solution with monitoring options for production test. The integrated BIST circuits provide good test coverage without the need for millimeter-wave probes and test equipment. The output power available from the oscillator, as well as the antenna connections and matching, can be evaluated using the on-chip BIST readings.
As the metal stack in the standard CMOS and BiCMOS technologies has normally a quite small spacing between top metal and substrate, on-chip antenna designs tend to be inefficient. The low resistivity and high dielectric constant of the silicon substrate make it challenging to achieve a good performance. The work presented in [7] addresses this issue by using a thinned-down substrate and placing the chip on a gold-finished opening on a printed circuit board (PCB) that forms the backside reflector of a dipole-antenna. Furthermore, substrate wave cancellation mitigates antenna losses as described in [8]. Other approaches to increase the antenna performance are to use hybrid antennas [9] or artificial dielectric layer superstrates [10]. Despite increasing the performance, all these methods introduce additional steps to the manufacturing process and require further components aside from the chip, adding to cost. Hence, the on-chip antenna in this work is an inset feed patch that solely uses the standard metal stack of the provided technology. As it is crucial to get a good estimate of the power delivered to the antenna to account for the gain and its return loss, timeconsuming electromagnetic (EM)-simulations of connections between the antenna and the circuit, as well as an additional area for antenna test structures are necessary to achieve an optimized antenna design. Here, a simple BIST structure in the transceive path is provided, which allows to measure the matching of the on-chip antenna, and the power delivered to it, directly on the die using power sensors together with a directional coupler. There are several works in the literature that show how to observe the output power of circuits with such sensors and also how to determine the matching [11]- [14]. Here, a power sensor is used to perform a return loss measurement on-chip using a directional coupler. To the best of the authors' knowledge, this is the first time that such This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ Fig. 1. Photograph of the realized monostatic transceiver system. The MMIC is bonded on an adapter board and placed inside the 3-D-printed package, which includes and aligns the lens on top of the die. The WR-06 waveguide horn is placed for scale. a BIST structure is implemented together with an on-chip antenna in this frequency range. Thus, it is possible to monitor the output power and the impact of process variations without using RF probes during the production phase, while taking advantage of the information provided by the structure already in the design phase.
In addition to the on-chip antenna and the BIST structure, a 3-D-printed case for the monolithic microwave integrated circuit (MMIC) is presented that features an integrated lens, which allows to increase the directivity of the antenna and thereby extends its operation in terms of range. As the die possesses only low-frequency connections, it can be bonded onto a low-cost FR4 adapter board that is placed inside the case, leading to the robust and cost-efficient sensor shown in Fig. 1. Possible applications for such a system include, for example, motion sensors or ground speed detection e.g., antilock brake systems [15]- [17].
The article is organized as follows. In Section II, the transceiver MMIC with its different building blocks is explained, while Section III describes the simulation and measurement results of those. Section IV gives an overview of the transceiver implementation into a radar demonstrator and the respective measurement results of the sensor are presented in Section V. Finally, in Section VI, the results are summarized.

II. TRANSCEIVER MMIC
The block diagram of the transceiver chip is shown in Fig. 2 and the circuit is realized in a 130 nm BiCMOS technology [18], which offers HBTs with f t and f max of 250 and 370 GHz. The process features four thin copper layers for routing and two thick copper layers for passives. The topmost metal is aluminum and is usually used for pads or fuses. In this work, the aluminum layer is also used to implement the antennas, as this allows to maximize the distance between radiating patch and ground plane, which is realized in the lowest metal layer. In this monostatic implementation, a transfer mixer connected in series between the signal source and the antenna is used. As the mixer is realized with a single diode, a large fraction of the voltage-controlled oscillator (VCO) signal is coupled via the mixer diode to the antenna. At the same time, the VCO acts as a local oscillator (LO) signal for mixing the received signal from the antenna to the baseband. The fundamental VCO is designed to deliver a high output power, as amplifiers and doublers for high frequencies would lead to a larger power and area consumption. Thus, choosing this VCO leads to low power and compact design. Additionally, a BIST structure consisting of a directional coupler with power sensors is placed between the mixer and the antenna to enable power and return loss measurements. Here, the benefit is that the power delivered to the antenna and its return loss can be measured with the patch as load. Furthermore, a digital interface can be used to control the different blocks.
Compared to state-of-the-art monostatic transceiver implementations, the proposed diode-based mixer topology allows to increase the signal-to-noise ratio (SNR) Here, P T is the transmit power, G the gain which is similar in receive and transmit direction for a monostatic implementation, λ the wavelength, σ the radar cross section, R the range, k the Boltzmann's constant, T 0 the temperature, B the noise bandwidth, and F n the noise figure. The impact on the SNR by the topology is explained in Fig. 3, which shows a conventional monostatic transceiver implementation [19] and the proposed one using a diode-based mixer. The insertion loss introduced by the rat race coupler in the conventional approach decreases the output power at the antenna and also the power that is delivered from the antenna to the mixer. Thus, the insertion loss between port power amplifier (PA) and ANT decreases P T , and the losses occurring from port ANT to RF mix increase F n , leading to a degradation of SNR. In addition, the coupler has limited isolation, which restricts the output power of the system. Otherwise, the transmitter leakage could impair the receiver performance. The innovative diode-based implementation operates without a coupler and can therefore forgo the splitting of the signal into two equal parts, as well as the associated insertion loss. Here, the signal travels through the diode-connected transistor which poses a sufficiently low impedance, so just a small insertion loss occurs. Furthermore, there are no limitations on the output power with this approach. The diode-based implementation also has a simple design and allows to save space, as mixer and coupler area are reduced to a single transistor.
In the following, each component of the realized transceiver is briefly described:

A. Voltage Controlled Oscillator
The fundamental VCO in Fig. 4(a) can be derived from a common-collector Colpitts topology. The base of transistors Q 1 and Q 2 is coupled via a transformer consisting of L 1 and L 2 which also provides the bias voltage. This voltage is created by diode connections to the supply and not shown here to improve readability. The current mirror supplying I bias1 is not shown for the same reason. Transmission line TL 1 serves to isolate the current mirror from the emitter of Q 1 . TL 2 and TL 3 together form the output matching and allow to extract the fundamental frequency. The lines TL 4 and TL 5 are placed to further increase the impedance of the varactors to ground, additionally to R 1 and R 2 . Capacitors C 1 and C 2 are placed as dc blocks.
The two oscillator cores that are formed by the base-coupled cascode stage lock together at a fixed frequency leading to a high output power design. The varactors controlled by V tune1 and V tune2 allow fine respective coarse tuning of the output frequency. The circuit draws 70 mA from 3.3 V voltage supply. Furthermore, the tail current can be controlled by the digital interface allowing power control.

B. Mixer With BB Buffer
In Fig. 4(b) the diode-based mixer is shown together with an BB Buffer. Here, the base-emitter diode of transistor Q 3 is used to mix the LO and RF signal, while enabling the LO signal to pass to the RF port with a small insertion loss. The contact configuration of Q 3 is BEBC to provide a small base resistance and minimize the insertion loss. Furthermore, an additional diode-connected transistor Q 4 is placed in the mixer to adjust the BB common-mode voltage to the input of the buffer. This transistor is similar in size and contact configuration to Q 3 . Transmission line TL 6 transforms the RF short circuit caused by C 2 to an open so that the LO signal For readability only one half of the differential circuit is shown after the VCO. travels ideally only to Q 3 . TL 7 and C 3 decouple the BB signal even more from the transceive path. At the RF port, TL 8 also transforms the short circuit to an open and provides a path to ground for a DC current that is applied by the current source I bias2 to bias the diode. I bias2 is realized with a current mirror, whose reference current can be controlled via serial peripheral interface (SPI), and allows to slightly control the tradeoff between noise figure and conversion gain. Capacitor C 3 is inserted for AC coupling.
The BB signal is fed to the positive input of the buffer stage, which is connected as noninverting operational amplifier. Here, the ratio between resistors R 3 and R 4 allows to set the gain, which can be modified by an external resistor R ext that is connected to a pad. This allows to adjust the circuit after manufacturing and is also necessary as the AC coupling capacitor C ext is too large to be implemented on the chip. The resistor R 5 is inserted to desensitize the output against connected measurement equipment, e.g., capacitances of long cables.

C. BIST Circuit
The BIST circuit is based on the power sensor depicted in Fig. 5. Here, a diode-based detector together with a directional coupler similar to [20] serves to sense the power in the transceiver path. The schematic of the diode detector is shown in Fig. 5(a). The detector uses the nonlinearity of the diode-connected transistor Q 1 which is operated in the squarelaw region, so an output voltage proportional to the power is observed. The signal path is connected to the emitter of the diode, which leads to a higher sensitivity as the influence of large collector parasitics is removed. After the diode, the signal passes an RC low pass filter and is extracted at the emitter follower Q 2 . Resistance R 4 is placed at the base of Q 2 to suppress possible negative resistances for long lines after the emitter follower, which could lead to instability. Transistors Q 1 and Q 2 are biased with current mirrors, which are shown here as current source I bias1 , respectively, I bias2 for readability. Resistors R 2 and R 5 are inserted to decouple the capacitance of the current source, leading to increased sensitivity for the detector and better stability for the emitter follower. The matching network consisting of TL 2 , TL 3 , and R 1 is placed at the input to match the coupler impedance to the capacitive behavior of the detector diode and to adjust the range of operation for the detector. Here, R 1 is a tradeoff between losses in the matching network and bandwidth, while also desensitizing the circuit against process variations. Transmission line TL 1 can be varied to enable flexibility in the positioning of the power detector, while C 1 is inserted as AC coupling. Except for the input matching the same signal path is placed again and provides a reference voltage. Hence, it is necessary to place the elements in close vicinity in the layout to keep the influence of process variation or thermal effects to a minimum. The circuit consumes 0.36 mA from a 3.3 V supply.
The directional coupler depicted in 5(b) is used to acquire the signal traveling to the antenna and the reflected signal. It is realized in a thick top metal of the technology and uses a metal two layers below as reference ground plane. Two detectors are connected to the coupler, where the detector at P IN1 senses the power coming from the RF port and P IN2 the power coming from the ANT port. The detector circuits deliver a voltage proportional to the power in each direction. While the detector diodes work in the square-law region, no correction factor is necessary, because the voltage scales linear with the power as shown in [21]. This allows one to calculate the return loss Here, V rev represents the voltage equivalent to the reflected power and V fwd the accepted power by the antenna. They are the voltage difference between V OUT and V REF acquired at the respective power sensor. Furthermore, the two voltage levels can be used to determine the absolute power that is transmitted, as well as the power that is received by the antenna.  Fig. 6 shows the on-chip antenna which is arranged in a 2 × 1 array formation to increase the antenna gain. Each antenna is fed with one part of the differential signal. At first, only one inset feed patch has been designed and optimized using the 3-D simulator HFSS from Ansys. The top metal of the technology which is aluminum serves as the material for the patch, while the lowest metal which consists of copper is used for the ground plane. As the antenna substrate height is quite small due to the metal stack height, no additional mitigation measures for surface waves were taken. To achieve repeatable antenna performance, fill structures are used to satisfy the density rules for chip fabrication. This leads to small metal rectangles of different sizes in the layers between top and bottom, resulting in an increased effective permittivity. Consequently, the wavelength decreases according to

D. Antenna
Here, λ is the wavelength, c 0 the speed of light, μ r the effective permeability, ε r the effective permittivity, and f the frequency. For the used patch that scales with the wavelength, the size can be reduced as it scales with the antenna area. The associated decrease in the gain can be mitigated by array structures and the smaller form factor of the antenna allows better realization of placement and routing. To account for the change in effective permittivity, the parallel-plate capacitor formula is used, where C is the capacitance, A the area of the antenna and d its distance to the ground plane. After comparing the simulation results of two 100 μm 2 areas, one with filling structures and one without, ε r is extracted. The resulting value from EM-simulation differs with ε r = 7.2 (including fill structures), from the specified one for the technology ε r = 4.2 (without fill structures) [22]. Fig. 7 shows the simulated radiation pattern of the realized antenna array. At 152 GHz it reaches a peak gain of −1.25 dBi with an efficiency of 12.3%.

E. Transceiver
The complete manufactured transceiver die is depicted in Fig. 6. On the left side of the chip the external capacitors to the ground are connected at the pad CAP EXT,p , respectively, CAP EXT,n , with the possibility to insert a series resistance to change the gain of the BB buffer on the chip. The BB frequency can be extracted on the same side at the BB p and BB n pads, where the indices p and n solely denote the left and right path between VCO and antenna. Due to the same phase, those two signals cannot be used differentially. On the bottom side of the chip, the SPI connection pads for enable (ENA), clock (CLK), and slave input (SI) are located, as well as two V CC pads to apply and measure the supply voltage at the same time for on-wafer characterization, while providing a lower resistance when it is supplied in the demonstrator via a low dropout regulator (LDO). On the right side, the forward and reverse voltage of the power detectors for the right half of the circuit can be measured at FWD REF,p and FWD SENSE,p , respectively, REV REF,p and REV SENSE,p . Also the tuning voltage for the VCO is applied at this side via V t1 and V t2 . As the high-frequency signal is transmitted and received by the on-chip antenna, no highfrequency connections are necessary for the pads. To verify the concept of the BIST structure, two transceivers with different  antenna dimensions are implemented. The two antennas will be denoted as ANT1 and ANT2, and are shown in Fig. 15.

III. SIMULATION AND MEASUREMENT RESULTS
The VCO is characterized as a stand-alone chip which allows one to measure the output power that is delivered to the antenna, and is implemented unchanged in the transceiver. All values are measured on-wafer using ground-signal-ground (GSG) Infinity waveguide probes to contact the chip at one differential output while terminating the other with 50 . Fig. 8 shows the tuning characteristic of the VCO for different supply voltages, which is measured using a harmonic mixer from OML together with a Keysight N9010A EXA signal analyzer. The inputs for fine and coarse tuning are connected to each other for this measurement and the voltage is swept from 0 to 7.5 V. This leads to a tuning range of 10.7% ranging from 144.6 to 161 GHz for a 3.3 V supply. The corresponding output power can be seen in Fig. 9 and is acquired using a VDI Erickson PM5 power meter. Its peak is 1.3 dBm for a tuning voltage of 7 V corresponding to a frequency of 160.8 GHz. This corresponds to a total differential output power of 4.3 dBm. For tuning voltages lower than 2 V the output power decreases, due to the decrease in the quality  factor of the varactor. This is uncritical for the determination of the return loss, as the power sensor has a high dynamic range. Fig. 9 shows also the forward voltage of the detector on the transceiver with the second antenna design (ANT2) that relates to the power which is passed to the antenna. As expected the voltage characteristics follow the measured power.
In Fig. 10, the noise figure and the conversion gain of the mixer are shown. The BB frequency of 700 kHz is chosen here due to spurious signals around 1 MHz caused by the measurement environment. Measured noise figure and conversion gain already include the influence of the operational amplifier, which is connected as a noninverting amplifier with a gain of 60 dB and has a 10 μF capacitance off-chip to provide an AC ground for its negative input. The simulated values for the BB buffer can be seen in Fig. 11. Noise figure and conversion gain of the mixer with this BB buffer are determined using the Y-factor method. For the measurement, a version of the chip without antenna is characterized on the wafer using a GSG D-band waveguide probe in combination with a VDI-730 SGX D-band extender and an ELVA-1 ISSN-06 noise source. The BB signal is evaluated using an E5052 signal  source analyzer from Keysight and the necessary external capacitor is connected via a probe tip.
In Fig. 12, the simulated values for directivity, insertion loss, coupling, and isolation of the directional coupler, that is used in the BIST structure, are shown. To evaluate the return loss of the antenna, the VCO of the transceiver is fed with a voltage ranging from 0 to 7.5 V at its tuning ports, that are connected to each other. Then the directional coupler is used to provide the signals for the power sensor. The voltages V rev and V fwd of the sensor are measured using voltmeters. The return loss of the on-chip antennas in Fig. 13 is based on the measured V rev and V fwd of the power sensor and calculated as given in (1). Here, the values of the second antenna design for different reticles on the wafer are shown. The shift between the different plots is due to the process variation and is primarily caused by the fluctuation of the distance between the top aluminum layer and the lowest copper layer, which acts as ground. Additionally, a change in color of the patches on the wafer can be observed under the microscope due to the variation of the passivation thickness, visualizing the process variation.  A return loss comparison of the first (ANT1) and the second (ANT2) antenna design is shown in Fig. 14. The input matching of ANT1 is centered at 158.4 GHz and of ANT2 at 153.2 GHz according to the power sensor. This difference in frequencies aligns with the dimensions given in Fig. 15. As the length of the patch scales with the wavelength, the larger antenna is centered at a lower frequency.

A. System Overview
To demonstrate the operation of the designed monostatic transceiver, a simple demonstrator using a microcontroller (μC) is realized. The block diagram of the demonstrator is shown in Fig. 16. Here, a commercially available development board is used and its LDO provides the power for all blocks. The board also features a USB to universal asynchronous receiver transmitter (UART) converter, which allows to program the microcontroller and at the same time to readback information from it. The μC is used to send the necessary SPI commands to the MMIC and to perform a fast Fourier transform (FFT) on the BB signal, allowing to determine the frequency and thus to evaluate the Doppler effect, giving the velocity of the detected target. The result can then be shown on a display that features a plot of the velocity together with  signal information at the top and the spectrum that is covered by the FFT at the bottom. As the MMIC that delivers the BB signal only has low-frequency connections, it is bonded on an adapter board. Afterward, this adapter board is placed in a 3-D-printed case, that features an integrated lens to focus the transmitted and received power from the on-chip antenna.

B. Case With Lens
An ellipsoid lens is embedded in the package to increase directivity and therefore range. The design is based on [23], where the following equation is used: Here, x and y denote position in a coordinate system, R is the radius around the axis of rotation, and ε r the relative permittivity. The resulting outline of the antenna can be seen in Fig. 17. As the package is fabricated using a 3-D-printer, the filament is characterized regarding its permittivity and loss tangent, because the lens is directly embedded and consequently printed as well. Thus, a sample of the used acrylonitrile butadiene styrene (ABS) is used for various measurements leading to the values given in Table I verify its functionality. The waveguide is used here instead of the on-chip antenna, as it provides a similar antenna pattern, but has a less complicated mesh, leading to reduced simulation times. As the antenna pattern of the waveguide and the antenna are similar, with both having a broad radiation angle, this simplification can be made here. To evaluate the influence of the increased directivity by the package with embedded lens, the open-ended waveguide is excited with a TE 10 mode and its antenna pattern is simulated stand-alone, as well as inside the package, where the chip would be located. The simulated results and the geometries can be seen in Fig. 18 and show that printed case also protects the bondwires and its frame acts as a spacer between PCB and the top, thus ensuring the correct distance to the lens. Furthermore, this setup also allows for low-cost bondwire packages in high volume production.

C. Demonstrator
A photograph of the realized sensor system is shown in Fig. 19 and uses pin headers to combine the different parts. The development board is plugged into the FR4 board, which serves to connect its respective pins with the transceiver in the package and features two operational amplifiers, as well as a multiplexer. Via 5 DIP switches which are also placed on the board, it is possible to control the baseband gain by switch 1 and 2, leading to different feedback resistors for the amplifiers and resulting in four possibilities to increase the BB signal even further by 10, 25, 40, or 56 dB. By switch 3 it is possible to toggle between two bandwidths for observation of the BB signal by setting the sampling frequency to 2048 or 5120 Hz, while switch 4 sets the number of samples to 512 or 1024. Switch 5 allows to choose between the two SAR analog-to-digital converters (ADCs) on the microcontroller from which each is connected to one BB output of the MMIC. This simple architecture allows rapid prototyping of case implementations together with possible lenses and also the quick change of bonded chips.
Furthermore, a display can be plugged in that shows an instantaneous evaluation of the detected signal, as depicted in Fig. 20. In the upper half, on the left side the speed of the detected target, the average power over all signals and the scaling factor used for plotting are shown, while on the right side the FFT bin of the detected signal and the ratio between signal and average power are listed. Below those six values, a plot indicating the change in frequency is shown. In the lower half, an instantaneous spectrum based on the calculated FFT is drawn. The example evaluation displayed here assumes an operating frequency of 157 GHz, as well as a BB frequency that increases repeatedly from 1 Hz up to 1045 kHz, resulting in a sawtooth plot. The respective velocity is determined according to Here, f BB is the baseband frequency given by the mixer, f osc the operating frequency of the VCO and c 0 the speed of light. As 1024 samples and a sampling frequency of 5120 Hz are used, FFT bin 209 corresponds to 1045 Hz, respectively, a velocity of 1 m/s. Combined with the possibility to evaluate the return loss and the power of the antenna with the BIST structure, this demonstrator allows to quickly optimize the whole system.

V. SENSOR EVALUATION
The sensor is evaluated using the measurement setup shown in Fig. 21. Here, a target placed on the plate of a 3-D-printer is moved along the z-direction, while the sensor is placed at the top facing downward and is operated as a Doppler radar with a fixed oscillation frequency of 157 GHz. The programming of the printer is done by G-code, a computerized numerical control (CNC) programming language that allows to set the velocity of the step motors that move the plate. For the measurement depicted in Fig. 22 a value between 1000 and 1700, which denotes the movement speed in mm/min, is passed to the printer. The comparison of  the adjusted and measured velocity shows a small offset in the detected movement. This deviation from the set velocity can be explained by the FFT that is performed on the microcontroller. To detect the slow movements of the plate, the sample frequency is set to 2048 Hz with 1024 samples, which leads to a bin width of 2 Hz. The minimum velocity difference that can be determined therefore is 1.91 mm/s. Thus, the resolution is only limited by the evaluation of the microcontroller. Consequently, the measured velocity is always a multiple of the 1.91 mm/s and therefore evaluates to one of the two adjacent values to the set velocity.

VI. CONCLUSION
This article has presented a compact monostatic radar transceiver that enables low-cost system implementations despite high-frequency operation. The introduced demonstrator shows the ease in handling of the topology and exhibits the possibility to overcome challenges posed by lossy on-chip antennas with a cost-efficient package. Compared to the monostatic transceivers introduced in Table II, this work performs favorably in terms of noise figure, power consumption, and area, due to its innovative architecture. Even with the on-chip antenna that has a gain of −1.25 dBi, the chip transmits sufficient power for close-range operation, which can be extended up to several meters by using the package with an integrated lens. The packaging concept is a simple and appealing alternative, compared to the other low-cost options like surface-mountable packages with flip-chip or embedded wafer level ball grid array packages [26], [27].
As the chip topology scales with the wavelength, the area consumption shrinks with increasing frequency. Thus, also implementations in future processes can benefit from the introduced design, enabling compact transceivers at much higher frequencies.