A Circuit-Inspired Digital Predistortion of Supply Network Effects for Capacitive RF-DACs

This article presents a novel digital predistortion (DPD) approach to compensate for nonlinear dynamic distortions caused by the supply network of capacitive radio frequency digital-to-analog converters (RF-DACs). The developed DPD concept recreates the voltage distortion on the RF-DAC’s supply network and modulates the input signal such that the effects on the output signal of the RF-DAC are canceled. In contrast to conventional DPD approaches such as pruned Volterra series or memory polynomials, the complexity of the proposed concept is reduced to a feasible level, allowing for implementation in integrated circuits. Furthermore, the derived DPD model allows to use linear estimation algorithms for coefficient training. The presented DPD is demonstrated by measurements of two different capacitive RF-DAC designs and compared with conventional DPD approaches. EVM and adjacent channel power ratio (ACPR) can be improved by up to 6 and 7 dB, respectively, outperforming conventional approaches.


I. INTRODUCTION
T HE demand for high data rates, robust transmissions, and power efficiency poses stringent requirements on the design of integrated wireless transceiver systems. Increasing the data rate, while simultaneously providing a reliable and power-efficient transmission, is closely related to the linearity of the communication systems.
In radio frequency (RF) wireless communication transmitters, the key component in terms of linearity and power efficiency is the radio frequency power amplifier (RF-PA) [1]. Circuit implementations tend to nonlinear characteristics when operated in a power-efficient manner. Moreover, high signal bandwidths exceeding 20 MHz emphasize frequency-dependent nonlinear effects, i.e., the so-called memory effects [2], [3].
A way to overcome this limitation is to use digital predistortion (DPD), where the input signal of the PA is modulated by a nonlinear operator such that the overall system's behavior is linear [4]- [6]. The performance achieved by DPD systems heavily depends on the underlying mathematical model of the predistorter. Sophisticated memory-based DPD approaches, such as the Volterra series [7], [8], achieve excellent performance but require large coefficient sets. The so-called pruned Volterra models, such as the memory polynomial (MP) [9], [10] or the generalized MP (GMP) [11], reduce the complexity of the Volterra series by sacrificing some performance and allow the implementation on integrated circuits.
Another approach to increase the system's power efficiency is to utilize the advantages of integrated circuitry based on digital building blocks [12]. One promising concept is the radio frequency digital-to-analog converter (RF-DAC), which shifts the circuit complexity for wireless transmitters further to the digital domain, reducing the number of required active and passive components [13], [14]. RF-DACs combine the functionality of a DAC and an upconversion mixer in a single circuit, allowing an efficient implementation on a monolithic die and leveraging the benefits of scaled CMOS technology with increased usage of fast and programmable digital blocks. RF-DACs have gained an increasing amount of interest in the Wireless Communications Society [14]- [18].
One specific architecture of RF-DACs is the so-called capacitive RF-DAC or switched-capacitor PA (SCPA), which was first published in the literature by Yoo et al. [18]- [20]. The capacitive RF-DAC combines high linearity over a wide frequency range with high power efficiency [18]. Moreover, dedicated architectures can provide enough signal gain to omit an additional conventional RF-PA [21], [22].
Nevertheless, also RF-DACs suffer from internal and external nonidealities, limiting their linearity. Hence, DPD concepts have also been proposed for RF-DAC-based transmitters [23]- [27]. These published DPD systems use conventional black-box approaches to model and hence mitigate the nonlinear effects. DPD concepts targeting specific nonlinear effects of capacitive RF-DACs have been proposed by This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ Markovic et al. [28], [29]. The resulting mathematical models are based on the detailed analysis of the origin and the resulting effects of the nonlinearities of the RF-DAC design, resulting in low complexity, but powerful DPD approaches.
This work follows the methodology of analyzing and modeling dedicated nonideal effects of capacitive RF-DACs. One of the major drawbacks of the capacitive RF-DAC is its low power supply rejection. As a consequence, any distortion or noise affecting the supply is visible at the output, causing undesired spectral regrowth and degraded EVM. The proposed concept introduces a low-complexity memory-based DPD approach. The voltage distortions on the capacitive RF-DAC supply are digitally recreated. This information is used to modulate the input signal such that the effect of supply voltage variations on the output of the RF-DAC is suppressed. The complexity of the proposed DPD is reduced to a feasible level for circuit implementation. Moreover, linear adaptive system identification algorithms can be used for coefficient estimation. The introduced DPD is capable of mitigating static as well as dynamic nonlinear effects and can thus be used for wideband signals exceeding 100 MHz.
The remainder of this article is structured as follows. Section II gives a brief introduction to the capacitive RF-DAC and the origins of its nonidealities. Furthermore, the section introduces the causes and effects of supply voltage distortions of capacitive RF-DACs. In Section III, the novel circuit-inspired DPD method, combating the effects of the supply voltage distortions, is detailed. Measurement results of two capacitive RF-DAC implementations, augmented with the proposed DPD method, are discussed in Section IV. Finally, Section V concludes this article.
The capacitive RF-DAC comprises N cells, each consisting of a capacitor C i , with 1 ≤ i ≤ N, a driving inverter, and an LO gate, as shown in Fig. 1. The digital amplitude information, (d 1 , . . . , d N ), is fed to the LO gates by the digital front end (DFE), determining the number of active switching cells. In this way, upconversion of the digital amplitude with the LO is inherently achieved. Inactive cells are not switching and kept at ground potential. Without loss of generality, all capacitor cells are assumed to be unitary, i.e., C 1 = C 2 = · · · = C N = C u .
The output voltage of the unloaded capacitive RF-DAC, decomposed into a Fourier series, and assuming infinitely steep signal transitions, is given by [33] v o (t) = V DD n(t) N where (n(t)/N) is the ratio of the number of active switching cells to the total number of cells, V DD is the supply voltage, and To restore the sinusoidal from this square wave, an output matching network comprising an inductive element L, as shown in Fig. 1, is part of the capacitive RF-DAC. The inductor L resonates the RF-DAC's capacitance C tot , filters higher order harmonics, and provides impedance matching. C tot with is the total array capacitance seen from the matching network [18], which is independent of the number of active switching cells n(t). Thus, the circuit operates as a single-ended series bandpass filter with the first harmonic given by

A. Nonidealities of Capacitive RF-DACs
Due to manufacturing variations, the driving inverters and especially capacitors in the matched cells slightly deviate from their ideal values, causing a nonlinear relation from the input signal to the output amplitude as the weight of active switching cells is no longer linearly related to the input signal, i.e., (n(t)/N) does not perfectly hold anymore in (3) [34]. Quadrature-based capacitive RF-DAC architectures additionally suffer from mismatches between in-phase and quadrature-related cells, causing an undesired IQ image in the output spectrum of the RF-DAC. The detailed analysis and a cancellation technique have been proposed by Markovic et al. [29]. Polar architectures, on the other hand, suffer from bandwidth expansion of the required magnitude and phase modulation, degrading the ACPR especially for wideband input signals [35].
Additional internal nonidealities arise from misalignment of the sampling instant between data and the respective LO signals or nonideal sign operation, increasing the noise floor and generating unwanted spurs in the output signal [36]. Similar effects are generated by the misalignment of the switching times caused by different lengths of the LO signal distribution into the individual cells. Another origin of nonlinear effects results from the mismatch of the respective pMOS and nMOS ONresistances of the driving inverters in each switching cell. Unequal ON-resistances change the charging and discharging time constant of the cell array, resulting in a code-dependent modulation of the output phase, causing AM-PM distortion [18], [33].
External contributors to the nonideal behavior of the capacitive RF-DAC arise from the LO generation and the supply network. Long-term clock jitter and the corresponding phase noise of the LO contribute directly to the output of the RF-DAC, increasing the out-of-band noise floor [34]. Furthermore, polar and multiphase architectures rely on the dynamic (resolution) of a digital phase-locked loop (DPLL) or a digital-to-time converter (DTC) to achieve the required bandwidth of the modulated digital input signal [14], [37]. Furthermore, the so-called remodulation occurs due to the pulling effect caused by the electromagnetic coupling of the RF-DAC and the used digitally controlled oscillators (DSOs) of the DPLL, generating undesired spurs and thus degrading the EVM and ACPR. Detailed analysis and digital cancellation technique were proposed by Markovic et al. [28].
Nonlinear effects caused by the supply network of the capacitive RF-DAC, which are the focus of the proposed DPD, are addressed in Section II-B.

B. Effects of Supply Voltage Variations
The supply voltage V DD of the capacitive RF-DAC is also its reference voltage. Hence, noise and distortions of the supply voltage are directly modulated with the input signal and the LO. This causes undesired spectral regrowth and degradation of the in-band performance, as briefly shown in Fig. 2.
Apart from thermal noise, supply voltage variations are typically deterministic, including, but not limited to, switching ripples of dc-dc converters [40]. However, the supply current i DD (t) drawn by the capacitive RF-DAC is (input) signal dependent, causing an undesired voltage drop v d (t) over the The drawn supply current i DD (t) depends on the number of active switching cells n(t) as the impedance of the RF-DAC Z DAC seen from the supply changes with n(t). To show this, the RF-DAC is simplified to the model shown in Fig. 3 [41]. All active and inactive cells are combined to two equivalent impedances, respectively. Without loss of generality, C u represents the (assumed) unitary capacitance of every cell and R u is the equivalent ON-resistance of the drivers' pMOS and nMOS [41]. The active cells are assumed to be connected to V DD . With that, the input impedance of the RF-DAC for a given n(t) = n is given by where the number of active switching cells n is determined by the baseband input signal x[k]. The supply current i DD (t) of the RF-DAC and the resulting voltage drop v d (t) over the supply network's impedance Z SN (s) in the Laplace domain are given by assuming an ideal supply voltage V dc and linear behavior of the supply network. The characteristic of the supply network is, apart from design specific circuitry such as low-dropout regulators (LDOs), dominated by parasitics, rendering its prediction with simulation tools with sufficient accuracy impossible. The supply current i DD (t) and, consequently, the voltage drop v d (t) depend nonlinearly on the number of active switching cells n(t) and thus on the baseband input signal x[k], resulting in low-frequency variations on v DD (t). The switching behavior of the capacitive RF-DAC also causes high-frequency distortions on i DD (t) and v d (t) [34], respectively. However, these high-frequency variations are suppressed by the (local) decoupling capacitance of the supply network of the RF-DAC. Thus, their contribution on the output signal of the RF-DAC is practically negligible and, in the following, only the low-frequency variations of the supply current and supply voltage are considered. These low-frequency voltage variations are modulated with the RF-DAC's input signal and upconverted by the LO on the RF-DAC's output, as shown in Fig. 2. However, due to the nonlinear dependence of v d (t) on the input signal x[k], the bandwidth of the distortions on the supply is, in general, larger than the input signal's bandwidth, (5), the supply voltage distortions correspond to the number of active switching cells, where the dependence of n(t) on the baseband input signal x[k] is different for different RF-DAC architectures. In polar architectures, the number of active switching cells n(t) is determined by the magnitude of the input signal. Contrarily, for quadrature capacitive RF-DACs, n(t) depends on the sum of the magnitudes of the in-phase and the quadrature signal. The normalized number of active switching cells for polar and quadrature architectures, respectively, is given by . Hence, the low-frequency distortions on v DD (t) depend either on the magnitude of the input signal or on the sum of the magnitudes of the in-phase and the quadrature components of the input signal. Fig. 4 shows the simulated low-frequency voltage drop of v DD (t) for a polar and a quadrature architecture, respectively. The voltage drop of the polar architecture, for V dc = 1 V, shown in Fig. 4(a), follows the magnitude of the exemplary chosen real-valued input signal, i.e., x[k] ∈ R and, thus, no phase modulation of the LO. In contrast, the voltage drop of the quadrature architecture for V dc = 1.1 V depends on the sum of the magnitudes, as shown in Fig. 4(b). The sudden changes of the supply voltage of the quadrature architecture correspond to the discontinuities of |x I | + |x Q |. In contrast, at the same time instances, the magnitude |x I + j x Q | is smooth. Furthermore, these discontinuities excite the resonance behavior of the RLC supply network and cause the ringing on v DD (t), as shown in Fig. 4(b). Fig. 5 shows the PSDs of a simulated polar capacitive RF-DAC with ideal and nonideal supply network, respectively, using the switched linear state-space modeling approach presented in [34] and [41], which allows to analyze the impact of a nonideal supply network on an (chosen) idealized model of the RF-DAC.
Typically, LDOs are used to regulate and provide a stable supply voltage for capacitive RF-DACs. LDOs with a gain-bandwidth equal or larger than the input signal  PSDs of the downconverted RF-DAC output with ideal and nonideal supply network for a multitone input signal with 10-MHz bandwidth, simulated with switched state-space models [34].
bandwidth are needed to provide the necessary low supply impedance. To also keep track of higher intermodulation distortions (third, fifth, and higher orders), which are caused by the nonlinear signal-dependent voltage drop over the supply network (6b), LDOs with even higher gain-bandwidth are required. Specifically designed LDOs are still feasible to meet the required quality of the power supply for the capacitive RF-DAC for, e.g., 4G communications [17]. However, for future wireless standards, the limits of this remedy will soon be reached due to the necessity of further improvements in power efficiency and reduction in off-chip external components. Moreover, at the same time, larger effective transmission bandwidths, 160 MHz and beyond, higher constellation orders, exceeding 1024-QAM, will impose even more stringent quality requirements on the linearity and the dynamics of the capacitive RF-DAC. Thus, another way of suppressing these effects is required. The proposed DPD approach specifically targets the signal-dependent supply voltage variation of the RF-DAC and offers an efficient way to compensate for these effects by using digital signal processing techniques.

III. SUPPLY NETWORK DPD FOR CAPACITIVE RF-DACS
The DPD concept focuses on the cancellation of the supply network effects discussed in Section II. Fig. 6 shows the principle block diagram of the proposed DPD, which recreates the signal-dependent voltage drop v d (t) over Z SN and modulates the input signal such that the resulting effect of the supply voltage variation on the RF-DAC's output signal is suppressed. The presented DPD approach is thus referred to as supply network DPD (SNDPD).
This section solely focuses on the equivalent (discretetime) baseband signal. Thus, all signals and functions are represented with discrete-time samples, i.e.,

A. Motivation
To achieve suppression of the supply voltage distortion, x[k] is modulated by a signal α[k] such that the predistorted RF-DAC input signal y[k] is given by Inserting (9) into the ideal RF-DAC transfer characteris- Hence, an ideal compensation of v d [k] would be achieved by which leads to the RF-DAC output signal The term represents a systematic error introduced by the DPD (9)  . Hence, the contribution of yields the desired, distortion-free output. The concept (9) with α[k] as proposed in (12) does not represent a perfect inversion of the RF-DAC's nonlinearity. However, the dominating distortions caused by v d [k] can be canceled, as indicated in (14).

B. Concept of the DPD
The details of the proposed DPD are shown in Fig. 7. The algorithm maps the RF-DAC input signal x[k] to the equivalent supply current and uses a digitally implemented supply network model to recreate the voltage distortionα , which is further used as a modulation signal for the input signal as in (9). The concept is valid for polar and quadrature capacitive RF-DAC architectures. The parameterization of the predistorter can be estimated by employing conventional (linear low-complexity) adaptive system identification techniques and a feedback receiver, as will be shown in Section III-D.
The block with O n (x[k]) in Fig. 7 maps the input signal to the normalized number of active switching cells x on [k], depending on the RF-DAC architecture as in (7).
g(x on ) is a static nonlinear function, mapping the equivalent number of active cells x on [k] to the low-frequency input current i DD [k] of the capacitive RF-DAC. This function is comparable to an instantaneous nonlinearity used in the Fig. 7. Concept of supply network predistortion [42]. Wiener and Hammerstein models [5], [43]. For example, g(x on ) can be modeled by a polynomial with order J or by a lookup table, where the respective coefficients are determined either by measurements or by circuit-level simulations. Fig. 8 shows a second-order polynomial, modeling the simulated low-frequency supply current of a polar capacitive RF-DAC for constant input signal magnitudes.
Finally, the operator T {·} models the frequency-dependent supply network impedance, as indicated in (6b). The output α[k] of T {·} is an estimate of the actual voltage drop v d [k] over the supply network, normalized by V dc . The supply network characteristic is dominated by parasitic effects due to wiring and process variation. Therefore, predicting its values with simulation is unreliable for DPD, and hence,α[k] is targeted to be estimated. In contrast to the static nonlinear function g(x on ), the model of the supply network T {·} accounts for frequency-dependent effects of the supply network, including inductive and capacitive effects. Thus, the proposed approach incorporates compensation of static nonlinearities as well as dynamic (memory) effects.
The output of the supply network modelα[k] is first multiplied with x[k] and then subtracted from the input signal x[k]. The resulting mathematical representation of the concept is given by

C. Modified Parallel Hammerstein Model
To be implemented, the static and dynamic nonlinearities in (15c) must be realized with mathematical functions. In this work, g(x on ) is modeled by a polynomial of order J . The operator T {·} is realized by a digital FIR filter of length M, having (J + 1 + M) coefficients. Insertingα[k] in the proposed DPD (9) gives Using (16) to model the voltage distortion is similar to a typically used Hammerstein approach, where a static nonlinear function is followed by one FIR filter. Moving h m inside the inner sum and introducing the coefficients a j m = h m · g j , ∀(m = 0, . . . , M − 1; j = 0, . . . , J ) leads to Considering the a j m as (J + 1) · M independent coefficients leads to an even more general DPD concept, where separate FIR filters are applied for each monomial as shown in the block diagram in Fig. 9. Furthermore, with (18), the output is linear in the parameters a j m and linear estimation algorithms can be used as will be shown next. The derived DPD (18) uses a parallel filter structure similar to the general (parallel) Hammerstein model [9] and the MP. Furthermore, the SNDPD shows similarities to the envelope MP (EMP) model [44], [45]. However, the input to the SNDPD's predistorter depends on the normalized number of switching cells x on [k], changing with the architecture of the RF-DAC as in (7). Although, for polar architectures where x on [k] = |x[k]|, the proposed SNDPD is equivalent to the EMP.

D. Parameter Estimation
The goal is to estimate the parameters a j m through observation of the equivalent baseband output signal v DAC [k] of the RF-DAC, similar to typically used DPD models such as the MP and the GMP. With (8) and using vector notation, the RF-DAC output without DPD can be modeled by and the unknown parameter vector is defined as The term x on [k] T a j m with x on [k] ∈ R ( J +1)·M×1 and a j m ∈ C ( J +1)·M×1 represents the model of the supply voltage distortion as in (12) and Matrices X on [k] and D x [k] in (22) are, respectively, given by and with X on [k] ∈ R K ×( J +1)·M and D x [k] ∈ C K ×K . Each row of (25) consists of the input samples to the parallel filter structure as in (19) Hence, the output of the RF-DAC v DAC [k] is linear in the unknown parameter vector a j m using the model of the supply network distortion, as shown in (18). From (27), one can thus derive a linear estimator such as the linear (complex-valued) least-squares estimator to estimate the unknown coefficient vector [46], [47], i.e., where (·) H is the Hermitian transpose and v DAC [k] are the (measured) equivalent baseband data samples of the capacitive RF-DAC's output. Thus, the proposed SNDPD model in (17) with α[k] (12) allows to use linear estimation algorithms to determine the parameters a j m from the output of the RF-DAC, similar to the typically used DPD solutions. The SNDPD model is based on the modeling of the effects of a varying supply voltage of the capacitive RF-DAC and therefore does not cover all nonidealities of the RF-DAC. However, estimating parameters a j m by minimizing some cost function of the difference between the output signal and the input signal, as proposed above, inherently considers also some other nonlinearities. As will be shown next, the SNDPD outperforms conventionally used models such as the MP and the GMP, validating the presented circuit-inspired DPD and modeling approach.

IV. MEASUREMENT RESULTS OF THE SUPPLY NETWORK DPD
This section presents the measured results achieved with the proposed SNDPD approach. The figures of merit are, as for typical DPD evaluations, the in-band performance in terms of EVM and the out-of-band performance in terms of the adjacent channel power ratio (ACPR). The SNDPD is validated with two quadrature capacitive RF-DAC designs: a capacitive RF-DAC-based digital PA (DPA) [21] and a wideband low-noise quadrature capacitive RF-DAC, similar to [22].
Furthermore, the performance of the SNDPD is compared to the MP [10] and the GMP [11]. In contrast to the MP and the GMP, the SNDPD explicitly uses the equivalent number of active switching cells x on [k] (7) as input to the predistorter, which corresponds to the dependence of the supply voltage distortion on the number of active switching cells, as discussed in Section II-B. Both measured RF-DACs are based on a quadrature architecture, and hence, the input to the SNDPD is x on [k] = |x I [k]| + |x Q [k]|, whereas MP and GMP use the magnitude |x[k]|.

A. Evaluation Setup
The measurement setup, similar for both capacitive RF-DACs, is shown in Fig. 10. The (predistorted) input signal is loaded to an on-chip RAM, which streams the digital code samples to the RF-DAC. A vector signal analyzer (VSA) is connected to the antenna output of the RF-DAC, terminated by a 50-resistor. The VSA also performs the downconversion from the RF to the equivalent baseband signal, similar to a feedback receiver for on-chip implementations. The DPA and the wideband RF-DAC are supplied by an ideal (nonswitching) voltage source. The LO (clock) for both designs is generated by an external clock generator, which is limited in terms of phase noise performance, as will be discussed next.
The evaluated adjacent channel power is integrated over the same bandwidth as the input signal for the upper and lower adjacent channel, respectively. Thus, for a 20-MHz input signal, the upper out-of-band signal power is integrated over where f G is a guard band for the respective bandwidth. The reported numbers in the tables correspond to the lower ACPR of either the upper or the lower adjacent channel.
The predistortion and the estimation of the model coefficients are performed with MATLAB using the downconverted baseband signal v DAC [k] from the VSA. The downconverted output signal is normalized by the expected linear rms gain of the RF-DAC g rms and further time ( t) and phase ( ϕ) synchronized to the input data, as shown in Fig. 10 [4]. The direct and the indirect learning methods have been applied [1] using the complex-valued least-squares algorithm (28) to estimate the coefficients. Coefficient estimation and predistortion are combined in the DPD block in Fig. 10.

B. DPA Measurement Results
The DPA connects four quadrature capacitive RF-DAC cores to a power combiner to increase the output power up to 25 dBm [21]. Even though the supply network was specifically designed to be very low ohmic, the DPD further reduces the spectral regrowth generated by distortions of the supply network.
The VSA for the DPA predistortion evaluation was limited to 40-MHz baseband bandwidth. Thus, DPD performance for spectral regrowth was evaluated using a 15-MHz input signal. The in-band performance, however, was evaluated using a standard-compliant 20-MHz Wi-Fi input signal, using also a 20-MHz signal as a training sequence for the DPD. The coefficients of the models have been estimated by using only one iteration of the indirect learning method.
Here, the SNDPD is compared to the MP using the following implementations: where J defines the highest order of the nonlinearity and M is the filter length. The MP also includes the linear memory terms for j = 0, whereas the SNDPD model for j = 0 becomes x[k] · (1 − m a 0m ), adding only a constant term to y[k]. Thus, the MP inherently includes more degrees of freedom. Fig. 11 and Table I show the PSDs and key parameters of the comparison of the SNDPD and the MP for the out-ofband radiation. The SNDPD achieves similar results compared to the MP although the SNDPD model's complexity is significantly lower.
The achieved improvement of the EVM using the SNDPD and the MP, respectively, is shown in Fig. 12. Both DPD approaches use a coefficient set of J = 3 and M = 4. The input signal is a 20-MHz, 64-QAM modulated orthogonal frequency-division multiplexing (OFDM) signal. The coefficients are estimated once at 14-dbm output power and then used over the whole input signal power range. Here, the SNDPD outperforms the MP by approximately 1 dB over the tested output power range. At 14-dbm output power, the SNDPD improves the EVM by almost 4 dB compared to the measurement without any DPD.

C. Wideband Capacitive RF-DAC Measurement Results
Compared to the DPA, the wideband quadrature capacitive RF-DAC is designed for less output power. However, high linearity and minimized out-of-band noise floor is achieved even without DPD. Its spectral regrowth is significantly lower compared to the DPA. Furthermore, due to increasing EVM requirements for the latest communication standards such as 5G and Wi-Fi 6, also the in-band performance is improved.
Another distinction to the DPA is the supply network. An internal LDO regulator is used to compensate for dc-dc voltage ripple and the signal-dependent current feedback. However, the LDO is not designed to track the applied high-bandwidth signals, and thus, the supply network effects degrade the ACPR.
The bandwidth of the used VSA for these measurements was 600 MHz, which allowed to validate the DPD for signal bandwidths up to 160 MHz.
Contrary to the DPA measurements, the direct and the indirect learning methods were applied, using indirect learning for the initial calibration, followed by three iterations of using direct learning to update the coefficients [48].
Here, the performance of the SNDPD is compared with the MP and the GMP. The implemented realizations are given by The parameters are summarized as follows. 1) J defines the highest order of the nonlinearity.
2) M defines the number of used memory taps for the nonlinear terms.
Thus, if L = 1, the linear memory is included. Depending on the individual definitions in the literature, the MP and the GMP can inherently include linear memory terms. However, the SNDPD model as defined in (18) does not account for these terms. To provide a better comparison, these linear terms are additionally included in the SNDPD. For L = 0, i.e., M lin = 1, the SNDPD in (31) becomes again the proposed approach as in (18). However, as is shown next, including the linear memory terms improves the performance of the SNDPD for the measured RF-DAC. Fig. 13 and Table II show the comparison of the different predistortion approaches for an 80-MHz 802.11ac Wi-Fi signal. The SNDPD approach outperforms the MP and the GMP, which show a higher noise floor in general, as shown in Fig. 13. The increased noise floor of the MP and GMP is most probably caused by estimation errors due to the higher number of coefficients and basis functions used in the DPD, respectively. For the GMP, this even causes small humps as can be seen in the spectrum at ±100 MHz. However, the ACPR can still be improved by almost 5 dB. In contrast, the SNDPD is robust for the same polynomial order J and memory taps M. Furthermore, the SNDPD uses the sum of magnitudes, i.e., x on [k] = |x I [k]| + |x Q [k]|, as input to the   FIG. 14 predistorter, hence achieving better performance although less basis functions are used in the model. As will be shown next, also the performance of the MP can be improved by using Moreover, the SNDPD even achieves comparable performance by only using the second-order nonlinearities in the DPD model, i.e., J = 2. This indicates the relation of the SNDPD model to the actual behavior of the supply current i DD (t), which has a quadratic-like behavior, as shown in Fig. 8. The EVM can be improved by more than 5 dB and the ACPR can be improved by almost 7 dB, as shown in Table II.
The small plot in Fig. 13 depicts the difference between the input signal and the output signals on a larger scale. The achievable noise floor of all measurements is limited by the accuracy of the used measurement equipment, especially by the phase noise of the used LO (clock) generator. All further plots thus only show the zoomed area. Fig. 14 and Table III show the performance of the SNDPD approach for different coefficient sets for a 160-MHz input signal. Adding the linear memory terms in the DPD, i.e., L = 1, improves the ACPR by additional 2 dB. In addition, also the number of filter taps is increased to 14. However, this only shows a minor impact on the DPD performance. Using J = 5, L = 1, and M = 4 improves the EVM and ACPR by 5 dB while still keeping the complexity low. At particular frequency bins, the spectral leakage could be decreased by almost 12 dB.
Another interesting comparison is shown in Fig. 15 and Table IV, where the SNDPD approach is compared with the MP for a 160-MHz 802.11ac Wi-Fi signal. Here, the linear memory terms are now also used in the MP. Furthermore, the I/Q case uses the sum of magnitudes, i.e., x on [k], as input to the nonlinear terms of the MP, equivalent to the SNDPD. Including the linear terms and using the sum of magnitudes     Table V show the results of three iteration steps of the coefficient estimation of the SNDPD with J = 5, L = 1, and M = 4 using a 160-MHz 802.11ac Wi-Fi signal. The DPD already achieves a significant improvement after the first iteration, using indirect learning. Additional iterations only have a minor impact on the ACPR and the EVM, which most probably result from the limited accuracy of the measurement setup. Fig. 17 additionally shows the respective AM-AM and AM-PM plots without DPD and with SNDPD. The performance, especially for the AM-PM, indicates the limits of the phase noise of the external LO generator.
The presented measurement results validate that the SNDPD is an effective method to significantly improve the ACPR and the EVM of capacitive RF-DACs. Due to the circuit-inspired modeling approach of the RF-DAC's nonidealities, the proposed SNDPD allows for a feasible implementation on an integrated circuit while even outperforming conventional DPD models, such as the (generalized) MP.

V. CONCLUSION
This work introduced a novel concept of a circuit-inspired DPD technique to compensate for nonlinear effects generated by nonideal supply networks of capacitive RF-DACs.
The proposed SNDPD digitally recreates the signal-dependent distortions on the supply voltage and utilizes this information to modulate the input signal such that the distortions on the capacitive RF-DAC's output are canceled. The developed underlying mathematical model of the DPD requires a limited set of coefficients, allowing for feasible implementations on integrated circuits. Furthermore, the parameterization of the presented SNDPD can be estimated by employing conventionally linear low-complexity adaptive system identification techniques. The concept accounts for static as well as dynamic (memory) effects and is valid for polar and quadrature capacitive RF-DAC architectures.
The input of the SNDPD depends on the normalized number of active switching cells x on [k] = O n (x[k]), changing with the used RF-DAC architecture. This approach differs compared to the typically used DPD models such as the MP, the GMP, and the EMP that always use the magnitude of the baseband input signal |x[k]|. In general, the SNDPD can be seen as a special case of the GMP (similar to the EMP), which only uses the relevant basis functions corresponding to nonlinear effects caused by the nonideal supply network. This also yields a more robust behavior of the SNDPD model compared to the GMP even when using higher polynomial orders and a larger set of memory taps.
The proposed SNDPD focuses on canceling nonideal supply effects of capacitive RF-DACs. As such, the SNDPD does not include special cancellation techniques for additional architecture-specific nonlinear effects such as LO remodulation, IQ image generation, and PM-PM/PM-AM distortions, which may be implemented additionally to the SNDPD. However, due to the chosen estimation concept, also, nonlinear distortions other than supply network effects are inherently compensated to some extent. Future works may additionally address the mentioned effects by extending the SNDPD model.
The SNDPD has been validated by measurements using two different quadrature-based capacitive RF-DAC architectures. It outperformed state-of-the-art black-box models such as the MP and the GMP while keeping computational complexity at a minimum. The EVM of the tested RF-DACs was improved by up to 6 dB for input signals with bandwidths of up to 160 MHz. Furthermore, the ACPR was decreased by up to 7 dB, whereas for dedicated frequency bins, the spectral emission outside the signal band could even be reduced by 12 dB. Conclusively, the SNDPD considerably increased the linearity of the measured capacitive RF-DACs.