Lumped-Element Wilkinson Power Combiners Using Reactively Compensated Star/Delta Coupled Coils in 28-nm Bulk CMOS

This paper presents four compact lumped-element Wilkinson power combiners (WPC) operating at 5 GHz in 28-nm bulk CMOS. To minimize the chip area, the inductances in the designs are implemented using mutually coupled coils. Two designs use star inverting coupled coils (SICC), while the other two employ delta noninverting coupled coils (DNICC). One of the two SICC-based designs (and similarly for the DNICC-based designs) incorporates a second harmonic (2f0) trap to lower the total harmonic distortion and reduce the required inductances by 25%, further reducing the circuits footprint. A design methodology for effectively exploiting the mutual coupling and nullifying the coupling parasitics is presented. The coupling parasitic in the DNICC-based design is exploited to provide the WPC isolation resistance, resulting in a lumped-element WPC requiring only three components: a coupled coil and two capacitors. The measurement and simulation results are presented to confirm the theory validity. The SICC-based WPC with an area of 0.13 mm2 achieved input return losses (RL) >17.5 dB, output RL > 11.8 dB, isolation >11.2 dB, and insertion losses (IL) <1.5 dB across 3.5–5.4-GHz frequency range. Its variant with a 2f0 trap achieved, from 3.5–5.35 GHz, input RL >18.2 dB, output RL >11.6 dB, isolation >11 dB, IL <1.4 dB, and peak 2f0 rejection of 18 dB at 10.2 GHz in an area of 0.13 mm2.The DNICC-based WPC with an area of 0.11 mm2 achieved input RL and isolation >10 dB, output RL >15.3 dB, and IL <1.2 dB across 4.1–5.45-GHz frequency range. Its variant with a 2f0 trap achieved, from 4.3–5.3 GHz, input RL and isolation >10.1 dB, output RL >14.6, IL <1.2 dB, and peak 2f0 rejection of 23 dB at 10.4 GHz in an area of 0.09 mm2.

due to their extremely small feature size [1]. Smaller feature sizes are being aggressively pursued to meet the demand for faster circuitry and higher levels of integration, but this presents increasing challenges for RF designers. One major challenge in designing the RF transmitter of a CMOS SOC is that the output power of the power amplifier (PA) is constrained by the low transistor oxide breakdown voltages, which limits the usable supply voltages [2], [3]. To prevent oxide damage and achieve the desired output power, multiple PA unit cells can be used together with power combiners such as the Wilkinson power combiner (WPC) [4], quarter-wave transmission lines (QWTL) [5], and transformer-based powercombining structures [6], [7].
The WPC, shown in distributed and lumped-element forms in Fig. 1, is popular due to its simple circuit topology and high performance, e.g., low insertion loss (IL), excellent return losses (RL), and high input isolation [4]. WPCs allow PAs to operate in isolation and ensure that they do not interfere with each other. In the classical distributed WPC, the QWTL match the input ports to the output port and the isolation resistor dissipates antiphase input power. Although QWTLs are too large for use in CMOS integrated circuits (IC) at low microwave frequencies, they can be replaced with lumped-element LC networks as in [8]- [17], as lumped components require much less circuit area than QWTLs.
On a CMOS process, inductors are typically implemented using large, lossy spiral coils, and thus, their size is minimized wherever possible. The high inductor losses on CMOS are due to the thin metal layers and eddy currents caused by the coil electromagnetically (EM) coupling with the conductive silicon substrate [18]. The inductance density can be increased through the appropriate use of mutual coupling between two or more coils. Mutual coupling has been used in [12] This work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/3.0/ and [14]- [17] to create compact lumped-element WPCs, but the reported methodology for correctly using the technique has been insufficient. One critical deficiency in the literature is that the parasitic coupling reactances, which degrade the matching and isolation significantly and hence must be compensated, have not been given sufficient attention. Park and Wang [15] acknowledge the parasitics but state that they were absorbed into the design without giving a thorough explanation of their operation. The WPC design in [17] utilizes four bridged-T coupled coils with each representing a QWTL. Since the bridged-T coil has similar electrical characteristics to QWTLs, the resulting circuit bandwidth is similar to that of the conventional WPC. This paper will provide a thorough and concise methodology for correctly utilizing mutual coupling in order to design compact lumped-element WPCs based on the circuit topology shown in Fig. 1(b). Furthermore, the analysis of mutual coupling will show that the parasitics of coupled coils can be exploited to provide the shunt isolation resistance resulting in a lumped-element WPC requiring only three components: a coupled coil and two capacitors. Two circuits have been designed that use inverting and noninverting coupling, each with a variant containing a second harmonic trap to lower the total harmonic distortion (THD) and the required inductance value in the circuit. The four WPCs were designed at 5 GHz and have been fabricated on TSMC's 28-nm bulk CMOS process.
The key design challenge is to achieve reasonable levels of RL at both input and output ports, IL, isolation, amplitude/phase balance, and operating bandwidth while keeping the overall circuit footprint minimal. The designs in this paper target 5-GHz WLAN (IEEE 802.11ac/n) applications with the ultimate goal being to integrate the power combiners with high-efficiency switched-mode PAs wherein isolation of at least 10 dB is needed to prevent one PA from loading the other.
The remainder of this paper is organized as follows. Section II introduces the star-and delta-equivalent circuit models of the inverting and noninverting coupled coils including reactance compensation techniques, Section III presents the working principles of four WPC variants designed using coupled coils, Section IV covers the implementation of the four circuits on 28-nm bulk CMOS, Section V discusses the circuit measurement results against simulation predictions, and finally, Section VI concludes the paper.

II. STAR-/DELTA-EQUIVALENT CIRCUITS OF COUPLED COILS
The two inductances shown in Fig. 1(b) can be implemented with a single three-port coupled coil comprised of two windings with one side of each connected to a common node. Mutual coupling occurs when the magnetic fields of the two windings interact, which alters the windings net inductances and, thus, can be used to design inductors with higher inductances than the winding self-inductance alone. The windings net inductances are determined by the coupling type and the coupled coil circuit model. The coupling type can be inverting or noninverting and these are respectively caused by antiparallel and parallel current flow in the windings. Coupled coils are commonly represented with dot notation as shown in Fig. 2, where L x is the self-inductance of each winding, M = L x k is the mutual inductance between the windings, and k is the coupling factor, ranging from 0 to 1 which represent no coupling and maximum coupling, respectively. The coupled coil can be modeled as a star or delta network. The star and delta models are derived using the transmission (ABCD) parameters of the inverting/noninverting coupled coils. Alternatively, once one model has been derived, the other can be obtained using a star-delta or delta-star transformation. In the literature, the star model is the most commonly used coupling model, but it will be shown that the delta model can enable the design of an even more compact WPC. Fig. 2 shows that the star inverting coupled coil (SICC) and the delta noninverting coupled coil (DNICC) have larger net inductances than the star noninverting coupled coil (SNICC) and the delta inverting coupled coil (DICC), i.e., L x + M versus L x − M, and, therefore, are favorable for a compact WPC design.
In addition to changing the windings net inductances to L x ± M, mutual coupling results in the creation of parasitic reactances, i.e., ∓M in the star configuration and (L 2 x ∓ M 2 )/M in the delta configuration, which must be removed as they degrade the WPC performance in terms of impedance matching and isolation. The parasitic reactances and their compensation components are shown in Fig. 2. In the SICC, the negative inductance −M can be canceled with an equally sized inductor M. The other three models have positive inductive parasitics which can be resonated out with a capacitor at the fundamental frequency f 0 , with the capacitor values given in the following equation: The detrimental effects of the SICC's and DNICC's parasitics on the performance of the lumped-element WPC shown in Fig. 1(b) are demonstrated in Fig. 3 for two different coupling factor values with circuit values given in Table I and derivations given later in Section III. When k = 0, there would be no coupling and, thus, no parasitics, and compensation would not be needed. As the coupling factor increases, the RL and isolation of the SICC-based circuit are increasingly degraded [ Fig. 3(a) and (c)], and similarly, in the DNICC-based circuit, the input RL and isolation are increasingly degraded, while the output RL is unaffected , giving a tradeoff between the coupling factor and the circuit bandwidth. As k approaches unity, an issue arises with the DNICC-based WPC as the shunt parasitic inductance (L 2 x − M 2 )/M tends to 0 (forming a short-circuit between the inputs) and the compensating capacitance C 2 tends to ∞.
The delta coils have an additional property that is extremely useful for designing compact WPCs. When the winding IL are included in a star-delta conversion, as in Appendix A, the real part of the parasitic impedance (7) increases as the coupling factor is decreased. This relationship means that R in Fig. 1 can be implemented without a discrete resistor by tuning k so that the parasitic resistance equals R. The value of k for a desired parallel parasitic resistance R P A is obtained by solving (10) in Appendix A. The value of the shunt resistance, R P A , given by (9) in Appendix A, is plotted against k and the quality factor Q for L = 1.59 nH in Fig. 4. For a given Q value which is largely dictated by the IC process, k must be tuned to achieve the desired R P A , i.e., if R P A is not sufficiently high, then the coupling factor will have to be reduced. In addition, it can be seen that (d R P A )/(dk) increases with Q, meaning that k does not need to be reduced as much for higher-Q coils. It can be deduced from (4) that the value of k cannot be set as high as possible in order to maximize the mutual inductance and, hence, minimize the circuit size,  since high k values result in small R P A values. This shunt parasitic resistance of the delta model allows the construction of a lumped-element WPC with only three components as will be explained in the following section.

III. NOVEL WILKINSON POWER COMBINERS USING COUPLED COILS
Four lumped-element WPCs using coupled coils, labeled Designs A-D, are shown in Fig. 5, with design equations given in Table II, where Z 0 is the port impedance. The design equations for the WPC shown in Fig. 1(b) are derived using even-odd-mode analysis. In the even mode of Fig. 1(b), L and C Y /2 match port 1 to port 3 (and also port 2 to port 3), whereas in the odd mode, 2C X resonates out L so that all the antiphase input power is dissipated in R. Designs A and B use SICCs to implement the series inductances shown in Fig. 1(b) while C and D use DNICCs. Designs B and D include second-harmonic traps to lower the output THD and reduce the required inductance of the corresponding resonated inductor by 25%, i.e., L B2 = 0.75L A2 and L D2 = 0.75L C2 . Although the DNICC-based circuits require only a single coil, the SICC-based circuits require two coils, i.e., one coupled coil and one compensating coil L A2 , L B2 . The latter provides a good benchmark as they are similar to the traditional lumped-element WPCs, which are typically implemented with two coils, while also demonstrating the effectiveness of the proposed negative inductance compensation technique.
The specifics of the four designs will now be covered. Design A is similar to the WPC circuit shown in Fig. 1(b) with the two inductances L replaced with a compensated SICC. Design B is a variant of A and includes a second-harmonic trap by replacing L A2 with a parallel resonator L B2 C B2 which presents +M at f 0 , with L B2 being 25% smaller than L A2 . Design C requires only three components as R C is provided by the coil parasitics and C C1 is formed from the combination of C X in Fig. 1(b) and compensating capacitor C 2 in Fig. 2.
Finally, Design D is a variant of C and includes a second-harmonic trap by replacing L C2 with a parallel resonator L D2 C D2 which presents L at f 0 , with L D2 being 25% smaller than L C2 .
The use of a second-harmonic trap benefits DNICC-based WPCs more than SICC-based WPCs as will be explained below. SICC-based WPCs employ two coils, the SICC and the compensating coil, whereas DNICC-based WPCs only use one coil (Fig. 5). By incorporating a second-harmonic trap into an SICC-based WPC, the inductance value of the compensating coil is reduced by 25% from L A2 = M to L B2 = 0.75 M (Table II) while the inductance value of the SICC remains the same, i.e., L A1 = L B1 = L. Hence, the 25% reduction in the compensating coil's inductance does not translate into 25% overall circuit size reduction, especially since the size of the compensating coil is smaller than that of the SICC due to M < L. On the other hand, by incorporating a second-harmonic trap into a DNICC-based WPC, the inductance value of the solely employed coil is reduced by 25% from L C2 = L to L D2 = 0.75 L (Table II), and therefore, the overall circuit size reduction will also be close to 25%.

IV. IMPLEMENTATION OF WPCS ON 28-nm CMOS
Designs A-D, designed with port impedances Z 0 = 50 , were fabricated on TSMC's 28-nm bulk CMOS process with the annotated chip layouts and chip micrographs shown in Figs. 6 and 7, respectively. The coils were implemented on the 2.8-μm-thick aluminum redistribution layer to minimize the IL. The coils and interconnects were EM simulated using Keysight's "Momentum RF" solver while TSMC circuit models were used to simulate the metal-oxide-metal capacitors and polysilicon resistors. To reduce the simulation time, the vias were merged using the "merge vias keeping boundaries" option in Momentum. The designs were created in Cadence Virtuoso and simulated with SpectreRF. Keysight's  GoldenGate was used to access Momentum from within Virtuoso. The simulated component values at 5 GHz are given in Table III.
The SICC was implemented with a symmetric center-tapped spiral inductor and the compensating inductor was implemented with a standard spiral inductor. The spacing between the metal traces of the SICC should be as small as possible to maximize the magnetic coupling. The SICC and compensating inductor experience mutual coupling, and thus, there is a tradeoff between the coil separation distance and the interconnect losses. Increasing the coil separation distance lowers the coupling factor (meaning that the SICC and the compensating coil can be designed and optimized individually) but increases the interconnect losses. To minimize the interconnect losses, the SICC and the compensating inductor were placed close together and an iterative approach was used to fully cancel the negative SICC leakage inductance. The design methodology for Design A is as follows.
1) Design the SICC and evaluate by grounding Port 3 ( Fig. 2) and simulating the two-port Z-parameters. 2) Design the +M compensating coil.
3) Connect the two coils and simulate their Z-parameters. 4) Adjust the SICC layout to compensate for the mutual coupling between the SICC and +M coil. 5) Adjust the compensating coil to nullify the new −M. 6) Repeat steps 4 and 5 until the specification is satisfied. 7) Use the design equations in Table II to get values for the remaining components and add to the simulation. 8) Evaluate the combiner using three-port S-parameters. 9) Tune noninductive passives to account for circuit nonidealities.
To lower the IL in Design B, L B2 's inner diameter was increased and its turn count was decreased relative to L A2 resulting in similar areas for L A2 and L B2 despite L B2 = 0.75L A2 . Increasing the inner diameter of a spiral inductor can lower the IL as it reduces the effects of eddy currents which are concentrated in the center of the coil [19]. The EM-simulated SICC inductances of L A1 and L B1 are lower than that givenin Table II (1.48 nH vs. 1.59 nH) as the coils were simulated in isolation with only the ground lines included. When additional circuitry such as routing lines and the compensating inductance are included, the inductances of L A1 and L B1 are much closer to 1.59 nH. R A and R B are ∼20 higher than that given in Table II (100 ) as the simulated isolation was ∼1.5 dB higher at 5 GHz.
The DNICC was implemented with a custom octagonal version of the Shibata coil, which is primarily a single-layer structure, hence enabling both of its windings to be realized on the thick aluminum layer [20]. As the Shibata coil is an edge-coupled structure, it can easily provide the shunt resistance R as the coupling factor can be tuned by varying the spacing between the metal traces. The design methodology for Design C is as follows.
1) Design an initial DNICC and evaluate it by grounding port 3 (Fig. 2) and simulating its two-port Y-parameters. 2) Revise the layout until the specifications are satisfied.
3) Add the resonating capacitance and simulate to confirm that L C1 has been nullified. 4) Obtain the remaining component values from Table II and add them to the simulation. 5) Evaluate the combiner using three-port S-parameters. 6) Tune the capacitances to account for circuit nonidealities. When implementing the L D2 C D2 resonator in Design D, the capacitors were connected directly across the windings to avoid long routing lines from port 1 to port 3 (and port 2 to port 3) while still resonating the majority of the winding inductance.
L C2 and L D2 slightly deviate from their theoretical values in Table II, i.e., 1.7 nH versus 1.59 nH and 1.32 nH versus 1.2 nH, as they were tuned to obtain better overall circuit performance in terms of RL, IL, and isolation.
To increase the layout symmetry, the single-ended capacitor at port 3 (C A2 , C B3 , C C2 , C D3 ) was divided in two and connected between port 3 and the two adjacent ground pads (Fig. 7). All four coil designs achieve good levels of coupling (∼0.7) which show that edge coupling is an effective technique for the design of coupled coils.

V. SIMULATION AND MEASUREMENT RESULTS
The S-parameters measurements were performed using an Agilent E8361C PNA with a 40A-GS-150/40A-SG-150-D-150-N Picoprobe connected to ports 1 and 2, and a 40A-GSG-150-p-n Picoprobe connected to port 3 of each circuit. Three sets of two-port measurements were required to assemble the full three-port S-parameters with the unused port terminated to 50 . A Picoprobe CS-3-150 impedance standard substrate (ISS) was used for each two-port short-open-load-thru (SOLT) calibration. For each two-port calibration, the short, open, and load calibration procedures are illustrated in Fig. 8, where the GSG probe would have one of its two ground pins touch the bare ceramic of the ISS. For Thru #1 (ports 1 and 3) and Thru #2 (ports 2 and 3) shown in Fig. 8, the GSG probe would have both ground pins connected to the ground pad while one half of the GSSG probe would not be included in the calibration. Finally, in Thru #3 (ports 1 and 2), the GSG probe would have all the three pins grounded while the GSSG probe would be connected to the fixture.
The simulation and measurement results of the four circuits, with the bond pads deembedded using EM-simulated S-parameters, are plotted in Figs. 9-12, summarized in Table IV, and compared with [9] and [12]- [14] in Table V. The bandwidths in Table V are defined as the range in which the RL and isolation are ≥ 10 dB. The upper bounds of Designs A-D's bandwidths have been set to keep the IL to acceptable levels. All four designs have an excellent agreement between the measurements and simulations. The results will now be compared and discussed.
1) All Designs: The difference in measured and simulated IL can be attributed to a number of factors. The high-density dummy metal fill, used to meet metal density requirements, was not included in the simulations and is found to decrease the quality factor and self-resonant frequency of integrated inductors due to eddy current flow and increased capacitive coupling, respectively [21]- [24]. A low-density dummy metal fill was available for inductors but was restricted to ≤ 5% of the layout area and so could not be used. Furthermore, the TSMC MOM capacitor models used in the simulations may be inaccurate. Via merging was used in Momentum to speed up the EM simulations and reduce the memory requirements. This could have resulted in an underestimate of the via resistances.
2) A and B: The SICC-based designs have high fractional bandwidths of 42%-43% with the lower and upper bounds constrained by the isolation and IL, respectively. The wider bandwidths compared with C and D are aligned with the simulation predictions in Fig. 3, wherein unlike the DNICC-based WPC, the bandwidth of the SICC-based WPC is shown to be unaffected by the level of coupling factor.
A and B have the best input RL with a minimum value of 17.5 and 18.2 dB across a 3.5-5.4 GHz and 3.5-5.35 GHz bandwidth, respectively. The isolation is excellent with peak values of 28.3 and 27.6 dB, respectively. As can be seen from Figs. 9 and 10, there is a variance in the frequency of the peak RL and isolation, with the peak input RL occurred at frequencies below 5 GHz, while the peak output RL and isolation occurred at frequencies above 5 GHz. This variance was inevitable as tuning the capacitances to optimize one parameter to have a peak value at 5 GHz would diminish the other parameters.
The amplitude error, |S 13 − S 23 |, is relatively constant over the bandwidth and the variation can be partly attributed to measurement noise. Part of the amplitude and phase error, | S 13 − S 23 |, may be attributed to the asymmetric magnetic  coupling between the SICC and the asymmetric compensating coil. The amplitude and phase error could be reduced by using a more symmetric compensating coil or moving the two coils further apart to reduce the coupling factor. To confirm   . These simulation results support the idea that the coupling between the SICC and the compensating coil has a nonnegligible influence on the amplitude and phase errors.

3) C and D:
The single-coil design of C and D resulted in the smallest circuit areas and the simplest layouts with C requiring only three components. The reactive compensation resulted in a negligible size increase when compared with the uncompensated DNICC as the compensation capacitances were absorbed into C X [ Fig. 1(b)]. The benefit of the resonator L D2 C D2 in D is apparent as D is 18% smaller than C.
C and D had good levels of bandwidth with the upper and lower bounds set by limiting the IL to <1.2 dB and isolation to >10 dB. The higher isolation of C enabled a 7% wider fractional bandwidth than D. The difference in isolation could be due to the differing shunt resistances of the DNICCs (Table III).
The IL was much lower than A and B due to the absence of the series compensating coil L A2 , L B2 , with C and D having a maximum IL 0.3 dB lower than A. The excellent isolation centered at 5 GHz with a peak of 18 dB in C validates the technique of using coupling parasitics to provide the isolation resistance and thus removing the need for a discrete resistor.
The amplitude error has been attributed to the physical location of C C1 and C D1 , i.e., across ports 1 and 2 (Fig. 6), which causes an unbalanced resonance current to flow through the coil, altering the L C2 and L D2 inductances. The simulated inductances of the compensated DNICC in Design C are shown in Fig. 13. The simulation results show an inductance imbalance of ∼250 pH between L 13 and L 23 at 5 GHz, with L 23 ∼16% greater than L 13 , which results in |S 23 | < |S 13 | as shown in Fig. 11. This inductance imbalance can be alleviated by using a more symmetric coupled coil than the Shibata coil shown in Fig. 7 and by placing the resonating capacitor C 2 (Fig. 2) in the center of the coil as shown in Fig. 14. The improved DNICC layout shown in Fig. 14 uses an octagonal version of the Frlan coil from [20] with the resonating capacitor placed below the center of the coil. A Frlan coil, including C 2 from Fig. 2, was EM simulated and the results are plotted in Fig. 13. At 5 GHz, the windings  net inductances are L 23 = 1.615 nH and L 13 = 1.605 nH, with L 23 only 0.6% larger than L 13 , and this could be further optimized. The Frlan coil shown in Fig. 14 is also shown in Fig. 13 to have a much higher self-resonant frequency (17.8 GHz) than the Shibata coil shown in Fig. 6 (10.3 GHz).
Simulation results of the unoptimized Frlan-based version of Design C in Fig. 14 are shown in Figs. 15 and 16 with Z 0 = 50 . The design process used the methodology for Design C described in Section. IV. The layout, excluding the capacitors, shown in Fig. 14 was EM-simulated in Momentum with ports connected to the bond-pads and the ends of the capacitor routing lines. The EM-simulated S-parameters in conjunction with TSMC capacitor models were then simulated in SpectreRF. The simulated amplitude error now peaks at 0.1 dB across a 3.5 to 6.5-GHz frequency range, compared to 0.55 dB in the original simulated Design C, with the phase error increased slightly within an acceptable range. At close  to dc, both the amplitude and phase errors are close to zero, implying that internal coupling results in an increasing error as frequency increases. The error is thought to be due to unbalanced current crowding caused by the rotation of the currents through the coil as shown in the inset of Fig. 14. 4) B and D: Designs B and D exhibit good levels of second-harmonic rejection of 18 and 23 dB, respectively. The peak harmonic rejection of D is higher than B since the resonating inductance L D2 is greater than L B2 (see Appendix B for the explanation).
The second minima of S 11 and S 22 (which also occur in Designs A and C at around 15 GHz in simulations) are caused by parasitic capacitances in the design. To demonstrate this, three identical parasitic capacitances (C par ) are added to the WPC shown in Fig. 1(b), where they are connected between ports 1-3 and ground. As shown in Fig. 17, in the absence of  (a) Even mode representation of the WPC in Fig. 1(b) and (b) resulting circuits when measuring Z 11 and Z 22 , and (c) Z 33 , in the presence of capacitive parasitics.
C par (i.e., C par = 0), there is only one dip in the responses of S 11 , S 22 , and S 33 , i.e., at 5 GHz. By introducing C par (i.e., C par = 0), a second dip appears in the S 11 and S 22 responses, but not in the S 33 response. This can be explained through the WPC's even-mode equivalent circuit [ Fig. 18(a)], where it has one capacitor connected to port 3 (i.e., C Y /2) but no capacitor connected to port 1 or 2. As a result, the presence of C par at ports 1 and 2 increases the number of poles of Z 11 and Z 22 (input impedances seen from ports 1 and 2) by one [ Fig. 18(b)], hence producing a second dip in the S 11 and S 22 responses. On the other hand, the presence of C par at port 3 increases the net capacitance at port 3 from C Y /2 to C Y /2 + C par [ Fig. 18(c)], but does not increase the number of poles of Z 33 (input impedance seen from port 3), hence no second minima produced. Furthermore, as shown in Fig. 17, the frequency and the magnitude of the second minima were strongly influenced by the value of C par . 5) Comparison With the Literature: Designs A-D are compared with [9] and [12]- [14] in Table V. While there are no publications of lumped-element WPCs that use a 28-nmbulk CMOS process, the designs in [9] and [14] use 130-nm bulk CMOS processes and the designs in [12] and [13] operate at frequencies close to those used by Designs A-D.
The electrical areas of Designs A-D are considerably smaller than the other designs in Table V. While the larger size of [14] can be attributed to the four-way design, Designs A-D are still very competitive with the largest design, B, being only 40% of the circuit in [14]. It should be noted that the output port of [14] is in the center of the transformer, which is impractical to connect to in a more complex system and the additional routing lines required to connect the combiner to other parts of the system would substantially increase the area and IL.
With regards to the IL, the four designs achieve good levels of performance when considering that [9] used a 4-μm aluminum metal layer, 43% thicker than that used in this paper, and that [12] and [13] benefited from a high-resistivity SiGe BiCMOS substrate which would experience much lower losses due to substrate coupling than CMOS circuits [25].
The most suitable design for comparison is [14], which also used a bulk CMOS process and a similar operating frequency. When compared to [14], it can be seen that the A-D have good levels of performance while operating on a much more advanced CMOS process with much higher integration density that is attractive for SOC applications. The other CMOS design [9] operates at a much higher frequency and has the largest electrical area of the designs in Table V.
Designs B and D have a much greater second harmonic suppression than the designs in [12] and [13]. The design in [14] achieved 14 dB of second-harmonic suppression, which was 4 dB lower than B and 9 dB lower than D.

VI. CONCLUSION
The theory, design, and measurements of four lumped-element two-way WPCs employing star inverting and DNICC in a 28-nm bulk CMOS process, including a design methodology for effectively exploiting mutual coupling and nullifying the coupling parasitics have been presented. The DNICC-based designs exploit the coupling parasitics to provide the isolation resistance, removing the need for a discrete resistor. The fabricated circuits achieved good levels of performance and size when compared with other pertinent designs in the literature as summarized in Table V, with the measurement results having excellent agreement with the simulation results. The concept presented can be extended for n-way WPC design and applied directly to other circuits employing inductors as discussed in Appendix C.
When compared with the SICC-based circuits, the DNICCbased circuits have the best overall performance as they have lower IL, smaller areas, and better output RL with similar input RL and isolation. However, the SICC-based circuits have wider bandwidths since, unlike the DNICC-based circuits, their bandwidths are relatively unaffected by the coupling factor k.
The ability to integrate a second harmonic trap into the DNICC enables a large decrease in circuit area and this is a key advantage over the SICC as there is no access to the internal node of the SICC so the L x + M inductances cannot be resonated. The compensating inductance in the SICC WPC can be resonated but it results in lower harmonic suppression than the resonated DNICC WPC and has little effect on the circuit area. The conversion of a star model of a noninverting coupled coil to a delta model, shown in Fig. 19, will be presented. The three impedances of the star network, P S , Q S , and R S , are converted to the delta network impedances A D , B D , and C D using (2) and (3) The three star impedances are defined in (4) and (5) where L x is the windings' self-inductance, M is the mutual inductance, R x is the parasitic resistance, and quality factor is The three delta impedances are thus calculated in (6) and (7). It can be seen that the real part of A D is a function of the coupling factor For a desired parallel resistance R P A , (7) can be rearranged to find the required value of k. First, express A D as the admittance Y A Equate the parallel resistance 1/Real(Y A ) to the desired parallel resistance R P A Defining the total inductance of B D and C D as L T = L x (1 + k), rearrange (9) in terms of k to get (10) which can be solved with numerical tools such as MATLAB APPENDIX B CMOS RESONATOR IMPEDANCE This appendix will explain why the harmonic rejection of Design D is greater than B due to the larger resonating inductance L D2 compared to L B2 .
We begin with the lossy parallel LC resonator shown in Fig. 20(a) with capacitance C res and its resistance R C,res , and inductance L res and its resistance R L ,res . The two resistances can be combined to form R res as shown in Fig. 20(b). At resonance, C res and L res will cancel out leaving only R res , and thus, to maximize the resonator's impedance during resonance, we must maximize R C,res and R L ,res .
The parallel resistance of a series RL or RC component is defined in terms of its series resistance R series and its series reactance X series as shown in (11). Substituting the quality factor Q series = X series /R series into (11) gives (12) which shows that R parallel is a function of both X series and Q series R parallel = R 2 series + X 2 series R series (11) = X series + X series Q 2 series Q series .
Thus, to increase the impedance of the resonator, Q series and X series must be increased. This can be done by using small capacitances and large inductances to maximize their reactances.
Using small inductances to maximize the inductor quality factor, and thus R parallel , in CMOS circuits is not an effective strategy as it would require larger capacitances with lower reactances and quality factors, and the detrimental effect of the smaller inductor reactance on R parallel would almost certainly be greater than the positive effect from the increase in quality factor. Thus, to design resonators with a high impedance on a standard CMOS process, large inductors and small capacitors must be used and this explains why Design D had better harmonic rejection than B as L D2 > L B2

APPENDIX C ADDITIONAL COUPLED COIL APPLICATIONS
The inductance compensation techniques presented here can be applied to many other circuits that utilize inductors. Two   situations will be presented: an n-way power divider and PAs in a phased-array.
An n-way version of the lumped-element combiner from Fig. 1(b), along with SICC and DNICC-based variants, is shown in Fig. 21 with design equations in Table VI. Each pair of input branches can utilize an SICC or a DNICC to reduce the required circuit area in the same manner as Designs A and C. S-parameters simulations of the three combiners in a four-way configuration are plotted in Fig. 22, where Z 0 = 50 and k = 0.8.
Phased arrays, and other circuits that use arrays of identical PAs, expend a significant amount of circuit area on the dc feed inductances for each PA. The number of dc feed inductances can be halved by replacing each pair of dc feed inductances with a DNICC as in Design ψ in Fig. 21. Design equations are given in (13) and (14) with simulated S-parameters of an ideal circuit plotted in Fig. 22 where Z ψ1 = 10 , Z ψ2 = 50 , and k = 0.6 ACKNOWLEDGMENT U.K. Priority Patent Application No. 1814756.1 "Improvements in and relating to Power Divider/Combiner Circuits" filed 11/09/2018.