Monolithically Integrated C-Band Low-Noise Amplifiers for Use in Cryogenic Large-Scale RF Systems

This article reports on the design of <inline-formula> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula>-band (4–8 GHz) monolithically integrated low-noise amplifiers (LNAs) in a 50-nm metamorphic high-electron-mobility transistor (mHEMT) technology with low-dc-power consumption dedicated to cryogenic operation in large receiver arrays. Two LNA monolithic microwave-integrated circuits (MMICs) are investigated: one two-stage design (LNA1) targeting the <inline-formula> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula>-band, which has been designed as a stand-alone and as a four-channel MMIC to demonstrate the ability to achieve higher integration levels. The second amplifier (LNA2) is a three-stage design focusing on 6–9 GHz, but it can also be used from 4–9 GHz with only minor performance degradation. LNA1 achieves an average in-band noise temperature of 2.7 K with 31 dB of gain when operated at 10 K with optimal noise bias (7.78-mW dc-power consumption). The power consumption of LNA1 can be reduced to 0.77 mW with an average noise of 3.8 K and 23.7 dB of gain. LNA2 provides 44.5 dB of small-signal gain and 3.3-K average noise temperature between 4 and 9 GHz (2.9 K between 6 and 9 GHz) at 10 K and optimal noise bias (5.57 mW). When the dc-power consumption of LNA2 is reduced to 1.34 mW, 35.4 dB of small-signal gain and 4.4 K of average noise temperature are preserved. To the best of the authors’ knowledge, LNA1 demonstrates both the lowest noise temperature and dc-power consumption among monolithically integrated <inline-formula> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula>-band LNAs at cryogenic temperatures.

Monolithically Integrated C-Band Low-Noise Amplifiers for Use in Cryogenic Large-Scale RF Systems Felix Heinz , Fabian Thome , and Arnulf Leuther Abstract-This article reports on the design of C-band (4-8 GHz) monolithically integrated low-noise amplifiers (LNAs) in a 50-nm metamorphic high-electron-mobility transistor (mHEMT) technology with low-dc-power consumption dedicated to cryogenic operation in large receiver arrays.Two LNA monolithic microwave-integrated circuits (MMICs) are investigated: one two-stage design (LNA 1) targeting the C-band, which has been designed as a stand-alone and as a four-channel MMIC to demonstrate the ability to achieve higher integration levels.The second amplifier (LNA 2) is a three-stage design focusing on 6-9 GHz, but it can also be used from 4-9 GHz with only minor performance degradation.LNA 1 achieves an average in-band noise temperature of 2.7 K with 31 dB of gain when operated at 10 K with optimal noise bias (7.78-mW dc-power consumption).The power consumption of LNA 1 can be reduced to 0.77 mW with an average noise of 3.8 K and 23.7 dB of gain.LNA 2 provides 44.5 dB of small-signal gain and 3.3-K average noise temperature between 4 and 9 GHz (2.9 K between 6 and 9 GHz) at 10 K and optimal noise bias (5.57mW).When the dc-power consumption of LNA 2 is reduced to 1.34 mW, 35.4 dB of small-signal gain and 4.4 K of average noise temperature are preserved.To the best of the authors' knowledge, LNA 1 demonstrates both the lowest noise temperature and dc-power consumption among monolithically integrated C-band LNAs at cryogenic temperatures.

I. INTRODUCTION
N OISE caused in electronic receivers inherently limits the system sensitivity, which is why most receivers use a low-noise amplifier (LNA) at an early stage of the receiver in order to keep the degradation of the signal-to-noise ratio as low as possible.When ultraweak electromagnetic signals, such as radio-astronomical signals in C-band (4-8 GHz) or the readout signal of a quantum bit (qubit), need to be The authors are with the Fraunhofer Institute for Applied Solid State Physics (IAF), 79108 Freiburg im Breisgau, Germany (e-mail: felix.heinz@iaf.fraunhofer.de).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TMTT.2023.3340519.
Digital Object Identifier 10.1109/TMTT.2023.3340519processed, conventional systems at room temperature typically have noise levels that are not acceptable.In order to meet the requirements of such applications, the LNAs are cooled to cryogenic temperatures to reduce the noise in the electronics.Lowest cryogenic noise temperatures (T e ) of semiconductor-based systems are achieved by high-electronmobility transistors (HEMTs) based on an InGaAs channel [1], [2].The HEMT structure can be grown directly lattice matched on InP or using a metamorphic buffer to adapt the lattice constant to the GaAs value.Therefore, the later ones are called metamorphic HEMTs (mHEMTs).
Future cryogenic systems, such as radio astronomical phased arrays or superconducting quantum computers, will need to scale the number of channels and, consequently, the number of cryogenic amplifiers for performance enhancement.Especially for quantum computing, it is expected that the number of physical qubits will need to be scaled to approximately one million in order to achieve a useful fault-tolerant quantum computer ("quantum supremacy") [3], [4], [5].Even with frequency-domain multiplexing, the number of readout HEMT amplifiers will need to scale proportional to the number of qubits.
Currently, transmon qubits are read out in C-band [4], where the state of the art is set by HEMT LNAs realized as hybrid assemblies, which use discrete HEMT chips connected to special low-loss substrates with wire bonds [1].However, hybrids are quite bulky, which makes scaling the number of LNAs to several thousand extremely challenging.
Monolithic microwave-integrated circuits (MMICs) might be an alternative to hybrid amplifiers, since they inherently offer a much smaller footprint, which would help to overcome the size limitations of hybrids.In addition, multichannel or multifunctional chips could be realized for a very high integration level on the 4-K stage.However, current monolithic LNAs do not achieve the same noise and dc-power (P dc ) levels as hybrid LNAs [6], [7], [8], [9].This might be due to several reasons: on-chip matching networks need to be realized using much narrower connections compared with off-chip networks leading to higher losses and, consequently, higher noise.However, LNA MMICs presented in the literature have not necessarily been designed on the basis of an advanced scalable cryogenic active device model [7].Fine-tuning the circuit parameters is critical in a fully monolithic design, where adjustments can only be realized with significant costs and in long-time periods.Therefore, the circuits might not achieve the best performance that can be reached by an MMIC.Furthermore, most MMICs published in the literature do not use transistor technologies that are used for state-ofthe-art hybrid LNAs.Consequently, this suboptimal choice of the transistor technology might also be limiting the noise performance of MMIC LNAs published in the literature.
This article deals with the design and characterization of LNA MMICs dedicated to cryogenic ultralow-noise operation.An advanced 50-nm mHEMT technology optimized for cryogenic low-noise performance [10] is used for best noise.An accurate transistor small-signal and noise model working down to cryogenic temperatures is available [11] and allows to set up precise circuit simulations at cryogenic temperatures, which is used to fine-tune circuit parameters for cryogenic operation.Two LNA MMICs are presented: a two-stage design targeting C-band (4-8 GHz) (LNA 1), which has been realized as a four-channel LNA to demonstrate that high integration levels at cryogenic operation can be achieved with the used 50-nm mHEMT technology.A stand-alone (one channel) version is provided as well for comparison.The second design (LNA 2) uses three stages and extends the C-band from 4-9 GHz, with a focus on 6-9 GHz, which is the band addressed by a dedicated superconducting qubit chip that shall be read.Furthermore, higher frequencies would help to further minimize the size of the readout resonators of the qubits.This LNA is used to investigate how the additional design freedom of a third stage can be leveraged for best performance.A third stage might help to improve input and output matching, gain (especially at low-power consumption), or amplifier bandwidth.
This article is structured as follows: The 50-nm mHEMT technology is briefly presented in Section II.In Section III, design strategies dedicated to monolithic ultralow-noise amplifier design with low-power consumption at cryogenic temperatures are discussed.The actual LNA MMICs and their design are presented in Section IV.Room temperature and cryogenic measurement results are provided in Section V.The presented LNAs are compared with the state of the art in Section VI.Section VII concludes this article.

II. 50-NM MHEMT TECHNOLOGY
In this section, the 50-nm mHEMT technology used for MMIC design is briefly recapped [12].The technology has been optimized for cryogenic ultralow-noise operation [10].The epitaxial layer stack of the active devices is grown on 100-mm semi-insulating GaAs wafers starting with a linearly graded InAlGaAs metamorphic buffer layer to adapt the lattice constant from the GaAs to the InP value.The 2-D electron gas (2DEG) is confined in an In 0.8 Ga 0.2 As channel enclosed by In 0.52 Al 0.48 As barrier layers.The upper barrier layer is silicon delta-doped close to the barrier-to-channel edge.The epitaxial layer sequence is finalized by a saturation-doped In 0.53 Ga 0.47 As cap layer ensuring ohmic contacts with low resistance, which is important for low HEMT noise.
Wet-chemical recess etching with a succinic-based solution opens the cap layer.The gate is formed by electron beam lithography using a four-layer polymethylmethacrylat (PMMA) resist.The 50-nm gate is structured using electron beam evaporation of a PtTiPtAu sequence.The gate head of the T-gate is 170-nm long, and the entire gate is encapsulated in benzocyclobuten (BCB), which reduces parasitic capacitances compared with a classical SiN passivation.A second gate head consisting of the first metallization layer of the process is placed on top of the first gate head.The second gate head has a width of approximately 450 nm, which reduces the gate-line resistance significantly without a noteworthy increase in parasitic capacitance due to the increased distance to the semiconductor surface.A low gate resistance is a key to achieve low-noise transistors.Device isolation is achieved by mesa etching.
The process features two gold metallization layers, where the upper one is a thick plated layer that can be used to realize airbridges.Metal-insulator-metal (MIM) capacitors are formed by a 250-nm-thick SiN layer.NiCr thin-film resistors (TFRs) with an approximately temperature-independent sheet resistance of 50 /sqr down to cryogenic temperatures are available.The wafers are thinned to 50 µm in order to suppress parasitic substrate modes.Through-substrate vias are dry etched, and a gold-plated backside layer is attached.Fig. 1 shows a simplified cross section of the backend of line.

III. DESIGN CONSIDERATIONS FOR CRYOGENIC LOW-POWER LNA MMICS
Cryogenic LNA MMICs for large scale systems require lowest noise temperature, high gain, and low-dc-power consumption with sufficient input and output matching.Some of these requirements demand for a trade-off especially in an MMIC implementation.An investigation on how these demands can be fulfilled in an MMIC is given in the following.
It is well known that the first LNA stage mainly determines its noise performance, given that it provides sufficient gain [13].Therefore, the design of the input stage is the key to achieve best noise performance.The lowest achievable noise temperature is given by the first-stage HEMT.Three noise parameters fully specify the noise of a device [14], [15], [16]: its optimal noise temperature (T min ) specifies the best noise performance, which is achieved when the optimal source-reflection coefficient ( opt ) is provided.The third noise parameter (R n ) specifies how the noise temperature degrades when another source-reflection coefficient is provided.The noise parameters describe the noise temperature as a function of the source-reflection coefficient.This function forms a paraboloid over the source-reflection plane, which can be represented in 2-D by circles of constant noise figure in the Smith chart [17].
opt of the whole circuit needs to be transformed to 50 in order to achieve best noise performance.However, in reality, this cannot be done lossless, and therefore, T min degrades dependent on the matching network chosen.A simulationbased investigation of different matching approaches at the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.mid-frequency of the C-band (6 GHz) at an ambient temperature (T a ) of 10 K is given in Fig. 2 and is discussed in the following.The analysis is provided narrowband at a single frequency in order to demonstrate the circuit design principles in a well-shaped manner.The actual LNA design needs to be matched over a broad bandwidth, and the design scheme needs to be applied at each in-band frequency point.
In general, on-chip networks on thin substrates are more lossy compared with thicker off-chip substrates, which can use wider lines to realize the same line impedance.Therefore, the input matching network needs to be designed as lean as possible in order to keep the losses low.An elegant way of transforming opt to 50 would be by a single shunt inductance in combination with an HEMT that has its opt turning to the 50-admittance circle in the Smith chart, which has been sketched for the ideal case of a lossless shunt inductance in Fig. 2 by the gray long-dashed lines.Fig. 2(a) investigates the absolute gate width (W g ) needed for such a network.
It is found that matching with just a stub is only possible for devices with very large gate width.This implies several drawbacks: devices with larger unit gate width (W F ) have higher T min .However, the most important drawback is the fact that the drain current needed to operate the device with a certain maximum stable gain (MSG) is proportional to the gate width resulting in higher dc-power consumption for large gate width devices.In the worst case, self-heating of the device might even degrade the cryogenic noise performance beyond the model prediction, since the model does currently not account for self-heating.At 6 GHz and 10 K, the simulated MSG is approximately 20.5 dB for the device sizes considered (MSG should be approximately independent on the gate width under lossless transformation) when biased at V d = 0.3 V and I d = 50 mA/mm at 10 K. Therefore, sufficient gain can be reached when properly matched for all the gate geometries considered.
Choosing smaller gate width devices helps to limit the dc-power consumption and to use low T min .However, one needs an additional impedance transformation step in order to apply the aforementioned shunt matching principle, which adds additional losses and degrades the circuit T min .The transformation could be achieved by adding a transmission line in series.Fig. 2(b) shows the noise paraboloid of W g = 4 × 60 µm 50-nm mHEMT when a 50-cryogenic groundedcoplanar-waveguide (GCPW) transmission line is connected to the gate in series.An existing room temperature line model [18] has been extended for cryogenic use by extracting the losses with a dedicated resonator test structure at 10 K.The transformation needs a very long (approximately 3000 µm) transmission line for a moderate HEMT gate width.This would be longer than typical MMIC lengths, but could still be implemented by meander structures.However, it adds significant losses, which degrades the noise performance.R n is only weakly influenced by the transmission line, and consequently, the quality of the matching needs to be quite high for best noise performance, which complicates broadband designs.
Another possibility to transform opt is the use of a series inductor.Fig. 2(c) shows the noise paraboloids of 50-nm mHEMTs with W g = 4 × 60 µm with ideal lumped inductors connected (for comparison) and [Fig.2(d)] with actual cryogenic on-chip spiral inductors connected.A dedicated cryogenic model of the on-chip spiral inductors is extracted using a 3-D electromagnetic field solver (CST Microwave Studio).This cryogenic model is obtained by adapting material properties, such as the conductivity of the metals and the loss tangents of the dielectric materials to cryogenic values.These material properties have been extracted using dc measurements and cryogenic on-chip measurements of several spiral inductor structures.The inductance values have been extracted from the simulation results using a simple equivalent circuit model to be able to compare the ideal and real inductances (a more sophisticated equivalent circuit model might be necessary for highly accurate inductance values).
The use of a series inductor has several advantages: it decreases R n , which can be seen by the bigger radius of the circles of constant noise in Fig. 2(c) for higher inductor values.This eases broadband noise matching.Ideal lumped inductors cannot, of course, be realized.Spiral inductors in airbridge technology offer low loss on a low chip area, which can be seen by the lower T min values of the noise paraboloids in Fig. 2(d) compared with Fig. 2(b).The parasitic parallel capacitance of the real inductors moves the circuit opt slightly closer to the Smith chart center, which even further eases noise matching, since the shunt inductance, which will preferably be Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.also realized as a spiral inductor, can be of lower size.Spiral inductors also have the advantage that they only occupy a small chip area, e.g., the 2400-pH inductor in Fig. 2 would only use an area of approximately 350 × 250 µm 2 .
Following conclusions for circuit design can be drawn from the given input-stage investigation: the size of the HEMTs mainly determines the chips dc-power consumption, and low gate width devices are preferred in terms of dc power.However, especially in the first stage, the choice of W g is a key to achieve optimal noise performance.Higher unit gate width devices have higher T min , but need less passive elements adding losses for matching.Lower unit gate width devices offer lower T min , but especially for very small devices, the values are not usable, since the matching networks needed for noise matching degrade the performance significantly.Based on the given investigation, spiral inductors are the best choice to optimize an on-chip input matching network of an MMIC for low noise and low-dc-power consumption.Simultaneously optimizing the HEMT gate width and the matching network is the key for low-dc-power consumption with low noise temperature.
The investigation gives an insight into the circuit design process at a single frequency.However, besides noise matching also other related parameters need to be considered over a large bandwidth.Input matching needs to be achieved, which is typically done using inductive source degeneration.In the frequency band of interest, adding inductances at the source does only weakly influence opt and R n , which allows to do the matching in two steps: noise matching first and afterward input power matching.Therefore, the aforementioned analysis holds true also in this case.Any losses added by real elements in the source path degrade the T min values of the common-source HEMTs shown in Fig. 2. Real HEMTs do not behave unilateral, and therefore, also, the interstage matching network and other circuit parts have an influence on the performance.Therefore, it is mandatory to set up an accurate cryogenic circuit simulation in order to optimize the MMIC performance.
IV. CRYOGENIC LNA MMICS Two 50-nm mHEMT LNA MMIC are designed and investigated: LNA 1 targets the C-band (4-8 GHz) and is realized as a stand-alone and as a four-channel MMIC to demonstrate that high integration levels can be achieved at cryogenic temperatures.A four-channel MMIC would offer several advantages: lowest footprint, since it reduces the number of additional bulky components, such as blocking capacitors and lines or wires to split up the biasing voltages.In large systems that need a high number of LNAs, less chips need to be handled, and the overall assembly effort is reduced.LNA 2 is a three-stage design that focuses on 6-9 GHz, but shall also be able to cover the full C-band if possible.Both designs target low-dc-power consumption and lowest noise temperature.Furthermore, feasible broadband input and output matching needs to be realized.High gain over a broad bandwidth shall be achieved.The multichannel version of LNA 1 aims for low channel-to-channel difference in performance.
Both designs use inductors in airbridge technology for matching, which means the inductor turns formed of the thick plated metal layer are placed above the semiconductor surface in the air and are only attached to the wafer at selected points by small gold pillars.The thick plated metal layer ensures low resistance for low losses.Airbridge inductors have the advantage that the parasitic capacitance per inductor turn area is reduced compared with an inductor directly placed on the GaAs substrate due to the low ϵ of air.This allows for additional freedom when designing the inductors: the self-resonance frequency of the inductors decreases for higher parasitic parallel capacitances [19].The parasitic parallel capacitance scales with the inductor turn area.Using airbridge spiral inductors, lowest parasitic sheet capacity is achieved.This has the advantage that self-resonances can be kept out of the band more easily even for large inductors while using wider inductor turns for lower losses.Interconnections are formed by GCPWs with a ground-to-ground spacing of 50 µm.The HEMTs in both designs use in-transistor airbridge patterns according to the principle presented in [20] to ensure active device stability at cryogenic operation.
LNA 1 uses only two stages in order to save the dc power of a third stage.This comes at the cost of lower gain.However, at least 30 dB of small-signal gain should be achievable with two stages.The design uses inductive source degeneration in both stages for simultaneous broadband input and noise matching.The inductances are realized as spiral airbridge inductors as well, in order to keep the added resistance at the HEMT source low for good noise performance.The first stage uses a W g,1 = 4 × 55 µm HEMT, and the second stage is realized with W g,2 = 4 × 45 µm.
The four-channel version parallelizes four LNAs on a single MMIC.The dc-bias connections are routed on the output side of the LNAs.This is important, since the dc wiring needs to cross the RF lines, which can then only be realized using the first metallization layer with higher losses.At the output, the influence on the noise performance should be negligible.The dc lines distributing the drain current need to be built in the gold-plated layer in order to keep the voltage drop as low as possible, which is important to ensure that the HEMTs are operated in the same bias point in order to achieve the same performance for all channels.Based on the sheet resistance of the metal layers used, a worst-case estimation of the difference in the drain voltage provided to the different channels has been estimated.When the circuit is operated with 50 mA/mm, the maximal channel difference in the drain bias voltage should be less than 13.5 mV.This is low enough to not expect large performance differences between the channels [10], [11].The authors see this as a worst-case estimation based on very conservative measures and expect the voltage drop to be even lower in reality.Fig. 3 shows a simplified schematic of the four-channel LNA MMIC, with the single LNA 1 channels grouped in boxes.Fig. 4 shows the chip micrographs of [Fig.4(a)] the four-channel MMIC and [Fig.4(b)] the stand-alone LNA (LNA 1).Although the four-channel MMIC currently uses exactly four times the chip area of the stand-alone MMIC, integrating multiple channels in one MMIC helps to reduce the LNA footprint in an assembly.Furthermore, a second design generation could reduce the area per channel even further.Currently, the RF-to-RF pitch at input and output of the multichannel LNA MMIC is 930 µm.LNA 2 uses three stages, which has the advantage of higher amplifier gain even when the stages are driven with very low-dc-power consumption.However, a third stage will consume additional dc power compared with a two-stage design.An advantage of a three-stage design compared with a two-stage LNA is the better isolation between input and output.This eases the design, since the influence of the output stage on the input stage and vice versa is reduced.Furthermore, an additional degree of design freedom is obtained, which allows to use smaller gate width HEMTs per stage to reduce the dc power per stage.
The first-stage gate-width has been chosen to be W g = 4 × 27.5 µm for best noise performance, while stages 2 and 3 have W g,23 = 4 × 22.5 µm gate width.Inductive source degeneration has been applied in all stages for broadband matching.The power matching of LNA 2 is improved especially in the 6-9-GHz regime.Higher source inductance is chosen in the first stage to improve the input matching.A smaller first-stage device gate width keeps the dc-power consumption low in the three-stage setup.Consequently, the LNA 2 uses a slightly higher series inductor in the input matching network in order to achieve good noise performance with improved matching.The higher source degeneration in the first stage enables the extremely broad matching that allows it to use the circuit even between 4 and 9 GHz.The source inductances of the following stages have been realized by transmission lines in GCPW to achieve the broadband  performance.Since three stages are used, the requirements on the gain are even further relaxed, allowing to use lossier lines compared with spiral airbridge inductors, which eases fine-tuning for broadband operation.Input and output matching can be achieved both more easily in the three-stage circuit, since the isolation between input and output matching network is higher.This allows for optimizations at one network without a large influence on the matching at the other port.Fig. 5 shows a simplified schematic of LNA 2, and Fig. 6 shows a chip micrograph of the processed MMIC.
Both LNAs circuit parameters have been fine-tuned by setting up a cryogenic circuit simulation using the 50-nm mHEMT model published in [11], which combines a temperature-dependent small-signal model with an adapted Pospieszalski noise model [22].Besides unconditional stability from the k factor, an extended stability analysis has been performed.Different reflection coefficients, including coefficients with high magnitudes, have been provided at the input and output of the LNA, and the reflection coefficients at the active device input and output reference planes have been analyzed according to [23], [24], and [25] to ensure stability in any impedance setup presented to the LNA.

V. MEASUREMENT RESULTS
The LNA MMICs have been characterized both at room temperature and at cryogenic temperatures.Room temperature measurements have been performed on-wafer with a single probing contact per cell to obtain both S-parameter and noise temperature of the LNAs using a Keysight PNA-X vector network analyzer system with an integrated sensitive receiver and input tuner dedicated to noise measurements.The noise temperature has been measured using the vectorcorrected cold-source method [26].The noise receiver of the PNA-X is calibrated using a Keysight 346CK01 noise source, the one-port calibration at port 2 used to determine the tuner reflection coefficients has been done using a Keysight N4694A 1.85-mm electronic calibration kit, and the twoport S-parameter calibration on probe reference plane is done on a Cascade 101-190C impedance standard substrate using load standards with trimmed resistance.Fig. 7 shows the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.measured and modeled S-parameters and noise of LNA 1 at room temperature.
LNA 1 achieves an average in-band (4-8 GHz) small-signal gain of 31 dB and an average in-band noise temperature of 67.1 K at room temperature.Both stages are biased at V d = 0.5 V and I d = 100 mA/mm (40 mA), resulting in 28.4 mW of dc-power consumption at 297 K.The input matching is better than −9 dB, and the output matching is better than −11 dB over the whole C-band.
Fig. 8 shows the measured S-parameters and noise temperature of all channels of the four-channel MMIC at room temperature.At 297 K, the maximal channel difference in average gain is less than 1 dB, and the difference in average noise between the channels is less than 0.7 K.As in a real multichannel receiver scenario, all channels are operated in parallel during the measurement.The measured performance of the multichannel MMIC at room temperature is comparable to the stand-alone version.The channel-to-channel isolation has been measured at room temperature on-chip.In order to provide decent matching, attenuator MMICs have been glued to the inputs and outputs that are not probed and connected with wire bonds.The four-channel MMIC is operated at V d1,2 = 0.6 V and I d1,2 = 100 mA/mm (40 mA) during measurement.One input and one output have been contacted by the probe, and two-port S-parameter measurements have been raised.The worst-case in-band isolation has been measured for neighboring channels and is between −20 and −35 dB.Channels with one channel between have an in-band isolation of −41 to −46 dB, and the channels at the chip borders have an in-band isolation between −46 dB and less than −60 dB.The rise of the isolation in the neighboring channel scenario is at the lower band edge, indicating that this can be improved by increased on-chip MIM capacitances.
Fig. 9 shows the measured S-parameters and noise temperature of LNA 2 and the corresponding circuit simulation at 297 K.The MMIC achieves an average noise temperature of 60.5 K between 4 and 9 GHz with an average small-signal gain of 48.3 dB when operated at V d1-3 = 0.5 V and I d1-3 = 175 mA/mm (50.7 mA).The input is matched better than −10 dB between 4 and 9 GHz, and the output matching is better than −6 dB between 4 and 9 GHz and better than −10 dB from 5.1 to 9 GHz.The MMIC consumes 33.2 mW of dc power at 297 K.
Cryogenic measurements have been performed in a Lakeshore CRX-4K cryogenic probe station with a closed cycle helium refrigerator.Samples for testing are selected based on room temperature wafer mappings including dc,  S-parameter, and noise temperature measurements to find representative devices.After wafer dicing, the devices under test (DUTs) are glued on a gold-plated copper disk using silver epoxy, which is similar to the module assembly process.The sample holder is mounted to the cooling stage with Apiezon N grease for proper thermal connection.S-parameters have been measured using a Keysight PNA-X vector network analyzer similar to the one used for room temperature testing.The cryogenic calibration at probe tip reference plane has been performed using a line-reflect-reflect-match calibration [27], [28], where the match resistors have been dc measured in order to achieve a highly accurate calibration.The cryogenic noise temperature has been measured in a second measurement step using the well-established cold attenuator measurement principle [29].The principle has been adapted for cryogenic on-chip measurements with low measurement uncertainty using a 20-dB attenuator MMIC with integrated temperature sensor that is glued next to the DUT and connected via wire bonds according to [30], and a worst-case measurement uncertainty of ±1.4 K has been estimated.The cryogenic noise measurements have been performed using a Keysight N4000A noise source and an Agilent N8975A noise figure analyzer.Fig. 10 shows a micrograph of the assembled four-channel noise measurement setup.Fig. 11 shows the measured and simulated S-parameters and noise temperature of LNA 1 at 10 K. LNA 1 achieves an average small-signal gain of 31.5 dB and an average noise temperature of 3.2 K between 4 and 8 GHz at 10 K when operated at V d1 = 0.3 V and I d1 = 50 mA/mm (11 mA), and V d2 = 0.5 V and I d2 = 50 mA/mm (9 mA).This results in   9 mW of dc-power consumption.The input matching is better than −9 dB, and the output matching is better than −10 dB over the whole C-band.The agreement between circuit simulation and measurement is very good, indicating the validity of the circuit optimizations that have been performed.
Cryogenic S-parameter and noise temperature of all channels of the four-channel LNA MMIC when it is operated at best noise bias [V d1,2 = 0.3 V and I d1,2 = 50 mA/mm (4 × 20 mA)] are shown in Fig. 12.The MMIC channels achieve an average small-signal gain between 30.8 and 31 dB, which is a maximal channel-to-channel difference of 0.17 dB.The measured average noise temperature in the C-band is 2.7-2.8K, which results in a maximal channel difference of 0.1 K.At this optimal noise bias, 4 × 7.78 mW dc power is consumed by the MMIC.An investigation on how the power consumption of the four-channel MMIC can be further reduced has been made.Fig. 13 shows the measured S-parameters and noise of all channels of the multichannel LNA at 10 K when operated with an ultralow dc power of 4 × 0.77 mW.At this ultralowpower bias, the average in-band gain of the different channels is 23.2-23.7 dB (0.52-dB maximal channel difference), and an average noise temperature of 3.8-4.4K (0.6-K maximum channel difference) between 4 and 8 GHz is achieved.The increased channel difference in low-power mode is believed to be caused by minimal variations of the threshold voltage of the HEMTs.At low drain currents, the HEMTs exhibit a very steep transconductance increase with increasing drain current [10].Therefore, small changes of the drain current have an increased impact on gain and, consequently, noise temperature.At low-dc-power consumption, lower gain is achieved with two stages, resulting in higher measurement uncertainty.Based on the method of [30], a worst-case measurement uncertainty of ±2 K has been estimated between 4 and 8 GHz.An investigation on the crosstalk between the channels has not been done, since it would require an assembled setup of the MMIC, which is currently not available.Fig. 14 shows the measured and modeled S-parameters and noise temperature of LNA 2 at 10 K when biased for optimal noise.LNA 2 achieves an average noise temperature of 3.3 K between 4 and 9 GHz (2.9 K between 6 and 9 GHz) with an average small-signal gain of 44.5 dB between 4 and 9 GHz (43.3 dB between 6 and 9 GHz).The input matching is better than −9.5 dB from 4 to 9 GHz and better than −15 dB between 4.8 and 9 GHz.The output is matched better than −5 dB over the whole band, and between 5 and 9 GHz, matching is better than −10 dB.At optimal noise bias, 5.57 mW of dc power is consumed, which has been achieved by allowing a slightly higher bias current in the first stage and reduced bias currents in the remaining stages.It is believed that the higher first-stage drain current density and drain voltage needed in LNA 2 to achieve best noise is a consequence of the lower first-stage gate width in combination with the higher source inductance network.Higher source inductance is needed for broadband matching introducing higher loss, which is gainwise compensated by using a slightly higher current density.The absolute first-stage current and, consequently, the dc power are still low, since the first-stage device gate width is smaller than in LNA 1.
LNA 2 has been measured with an ultralow-power consumption of 1.34 mW at 10 K, and the corresponding noise and gain measurements are provided in Fig. 15.An average gain of 35.4 dB between 4 and 9 GHz (34.7 dB between 6 and 9 GHz) is achieved at low-power operation.The average noise between 4 and 9 GHz is 4.4 K (4.0 K between 6 and 9 GHz) at ultralow-power consumption.
LNA 1 achieves the lower noise temperature and also lower power consumption in low-power mode compared with LNA 2. However, LNA 2 offers higher gain, which is an advantage especially in low-power mode.The use of the three stages also helps to improve related circuit parameters as input and output matching.The noise performance and power consumption of LNA 2 are also very low in both biasing modes.The four-channel MMIC does not have any disadvantages compared with the stand-alone chip, which demonstrates that such a high integration level can be handled at cryogenic temperatures.The presented four-channel MMIC could easily be extended to eight channels by mirroring the layout of this chip at its south edge.

VI. STATE-OF-THE-ART COMPARISON
The proposed LNA MMICs are compared with the state of the art in Table I.The table is split into two groups: in the upper half, hybrid LNAs, which use external dedicated low-loss substrates for matching, are provided.The second part shows MMICs, and on the bottom, the results of this work (MMICs) are listed.
Hybrid LNAs still offer the best noise performance in C-band and can be operated with the lowest power consumption.However, MMICs have a smaller footprint compared with hybrids and have the opportunity to be integrated into multichannel chips, as it has been demonstrated in this article.Furthermore, multifunctional chips or hetero-integrated cryogenic implementations with a very small footprint could be possible in future work with MMICs.
To the best of the authors' knowledge, LNA 1 provides the lowest noise temperature among C-band MMIC LNAs reported in the literature, both when biased for optimal noise and for low power.In low-power mode, it has the lowest power consumption among monolithic C-band LNAs.Even though the gain is reduced, the MMIC still offers 23.7 dB at low-power bias.
LNA 2 uses a third stage to overcome the slight limitation in gain of LNA 1 when it is operated with low power.The average noise performance of LNA 2 is slightly higher, but it offers an even broader bandwidth with improved input and output matching.The power consumption in low-power mode is slightly higher compared with LNA 1, which is a consequence of the third stage.The average noise performance is still better than values of other MMICs reported in the literature both when operated for low power and optimal noise.In low-power mode, the power consumption is lower than the ones provided in the literature for LNA MMICs.A gain of 35.4 dB is achieved with ultralow-power consumption of 1.34 mW.

VII. CONCLUSION
In this article, monolithically integrated C-band LNAs in 50-nm mHEMT technology dedicated to cryogenic operation in large radio-astronomic receiver arrays or quantum computing readout have been presented.MMICs that do not use external matching networks offer a lower footprint compared with hybrids and the potential to be hetero-integrated with other electronic functionalities on the 4-K cooling stage.Furthermore, multichannel chips can be realized, which has been demonstrated by a four-channel LNA MMIC array (LNA 1).This shows that high integration levels, compared with commonly used hybrid single channel LNAs, can be achieved at cryogenic temperatures.
Circuit design strategies for monolithic LNAs at cryogenic temperatures have been discussed in order to improve the noise performance and power consumption of LNA MMICs in C-band.Based on this, two LNAs have been presented: a two-stage version (LNA 1) and a three-stage version (LNA 2).LNA 1 achieves an average in-band noise temperature of 2.7 K in C-band, which is, to the best of the authors' knowledge, the lowest noise temperature demonstrated by an LNA MMIC in C-band.When operated for low-power consumption, 0.77 mW of dc power is consumed (per channel), and 3.8-K average noise temperature is achieved, which is still lower than other MMICs reported in the literature.
LNA 2 achieves a broader bandwidth with improved matching, especially in the 5-9-GHz region, with 3.3-K average noise temperature and the highest gain (44.5 dB) among LNAs published in the literature.This is an advantage when LNA 2 is operated with 1.34 mW of dc power, since 35.4 dB of gain and 4.4-K noise temperature are still achieved.
Although the noise performance of hybrid HEMT LNAs in C-band has not been reached, a significant improvement compared with previously published MMIC LNAs has been achieved in this work.The MMICs can even compete with some hybrids.The good performance in combination with the ability to use the advantages of MMICs, such as smaller footprint and multichannel integration, is an important step to scale the number cryogenic LNAs in astronomical phased array receivers or qubit read out.

Manuscript received 2
May 2023; revised 17 July 2023, 18 September 2023, and 12 November 2023; accepted 2 December 2023.Date of publication 18 December 2023; date of current version 4 April 2024.This work was supported in part by the European Union's Horizon 2020 Research and Innovation Program through the Project SEQUENCE under Grant 871764 and in part by the German Federal Ministry of Education and Research through Projects MUNIQC-SC and QBriqs.An earlier version of this paper was presented at the IEEE MTT-S International Microwave Symposium (IMS), San Diego, CA, USA, June 2023 [DOI: 10.1109/IMS37964.2023.10188065].(Corresponding author: Felix Heinz.)

Fig. 1 .
Fig. 1.Simplified wafer cross section to sketch the backend of line of the 50-nm process (dimensions are not true to scale).

Fig. 2 .
Fig. 2. Simulated noise paraboloids at 6 GHz of 50-nm mHEMTs in common-source configuration operated at V d = 0.3 V and I d = 50 mA/mm at 10 K depicted as circles of constant noise temperature in the source-reflection plane [17].Circles of constant noise are shown in 0.2-K steps added to the T min value.(a) Four finger HEMTs with different unit gate widths.(b) W g = 4 × 60 µm HEMTs with 50-transmission lines of different lengths connected to the input.(c) W g = 4 × 60 µm HEMTs with ideal lossless lumped series inductors of different inductances connected to the input.(d) W g = 4 × 60 µm HEMTs with cryogenic 3-D EM-simulated spiral inductors in airbridge technology models connected to the input.The gray dashed trajectory highlights the 50-admittance circle in the upper half of the Smith chart on which an ideal shunt inductor would transform opt .

Fig. 6 .
Fig. 6.Chip micrograph of the three-stage extended C-band LNA MMIC.The chip occupies an area of 3 × 1.25 mm 2 including RF and dc pads.

Fig. 8 .
Fig. 8. On-wafer S-parameter and noise temperature and circuit simulation of the four-channel LNA MMIC at room temperature when operated at V d1,2 = 0.6 V and I d1,2 = 100 mA/mm (40 mA).Measured LNA A (red solid lines), measured LNA B (blue dashed lines), measured LNA C (black dotted lines), measured LNA D (green dashed-dotted lines), and the corresponding circuit simulation (orange dashed-dotted-dotted lines) are shown.

Fig.
Fig. Micrograph of the four-channel LNA MMIC assembly for on-chip noise temperature measurement.Four dedicated 20-dB attenuator MMICs (pink dashed boxes) are glued in front of the four-channel DUT (yellow dashed box) and connected to the four inputs with wire bonds (turquoise dashed box).Each attenuator MMIC occupies a chip area of 0.75 × 0.75 mm 2 , and the DUT size is 2.5 × 4 mm 2 .

Fig. 12 .
Fig. 12.(a) Measured and simulated S-parameters and noise temperature of the four-channel C-band LNA MMIC at 10 K when operated at V d1,2 = 0.3 V and I d1,2 = 50 mA/mm (4 × 20 mA) and (b) corresponding gain and noise temperature measurement.Measured LNA A (red solid lines), measured LNA B (blue dashed lines), measured LNA C (black dotted lines), measured LNA D (green dashed-dotted lines), and the corresponding circuit simulation (orange dashed-dotted-dotted lines) are shown [21].

TABLE I STATE
-OF-THE-ART CRYOGENIC C -BAND LNAS