A W -Band Transmitter for Automotive Radar Sensors in 28-nm FD-SOI CMOS

—This article presents a 77-GHz transmitter (TX) in a 28-nm fully depleted silicon-on-insulator CMOS technology for automotive radar applications. The circuit has been designed to simultaneously fulfill both short-/medium-range (S/MR) and long-range (LR) operations. It exploits an LO frequency doubling architecture, which allows preventing voltage-controlled oscillator (VCO) pulling effects for improved phase noise (PN) performance. The proposed TX comprises a 38-GHz VCO driving a frequency doubler and then a current-combining two-path power amplifier. The VCO takes advantage of a novel tank architecture to cope S/MR and LR requirements with an effective and silicon area-saving solution. The proposed TX also features a feedback loop that allows properly setting the power delivered to the output load. It exhibits a 5-GHz bandwidth, ranging from 76 to 81 GHz, with a PN performance as low as − 93 dBc/Hz at a 1-MHz offset frequency from a 77-GHz carrier. It is also able to deliver a maximum output power as high as 17.5 dBm with a dynamic control range of around 13 dB. The overall power consumption is 351 mW.


I. INTRODUCTION
A UTONOMOUS driving systems may drastically reduce car accidents, preventing injuries and ultimately saving human lives.Typically, such systems exploit different kinds of sensors (e.g., lidar, radar, video, infrared, and acoustic) as shown in Fig. 1, which are aimed at monitoring the environment surrounding the vehicle and hence properly control its motion [1].
The W -band radar sensor is an enabling technology for the implementation of effective self-driving systems due to its inherent robustness to environmental interference such as poor light, extreme temperature, and weather condition, which make it irreplaceable.According to the coverage area, radar sensors can be grouped into two categories, namely, short-/medium-range (S/MR) and long-range (LR) sensors.The former provides a detection range of a few meters but with a resolution of tens of centimeters, whereas the latter must provide a coverage area of more than 250 m but with a less stringent resolution requirement with respect to their S/MR counterpart.Recently, research efforts have been addressed to embed S/MR and LR functionalities into the same device to reduce size and costs.However, this translates into stringent requirements for both the receiver (RX) and transmitter (TX) side of the radar sensor.Specifically, S/MR sensors demand for a local oscillator (LO) with a wide tuning range (TR), besides very high linear RX.Conversely, addressing LR applications calls for both high transmitted power and very low phase noise (PN) [2].Commercial radars take advantage of advanced SiGe BiCMOS technology platforms that enable the integration on a single chip of radar sensors, including mm-wave radio front end, analog baseband, analog-to-digital converter (ADC), and digital interface [3].However, nanometer CMOS technologies are now able to provide also high-speed digital processing and nonvolatile memories, thus resulting in the best candidates for the system-on-chip (SoC) implementation of high-performance W -band sensors [4], [5], [6].Nevertheless, most of the recently reported CMOS radar implementations are targeted to S/MR applications and therefore are far from simultaneously addressing LR radar requirements [7], [8].
In this work, a 77-GHz TX in a 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology is presented, which can cope with both S/MR and LR applications.The TX includes a 38-GHz voltage-controlled oscillator (VCO), a frequency doubler, and a 77-GHz two-path power amplifier (PA).It also features a feedback loop that allows setting the power delivered to the output load according to the addressed application.This article is organized as follows.Section II deals with the description of the adopted architecture.A detailed circuit design is presented in Section III and  measurements are extensively discussed and compared with the state of the art in Section IV.Finally, conclusions are drawn in Section V.

II. SYSTEM DESCRIPTION
Automotive radar sensors usually exploit a frequencymodulated continuous-wave (FMCW) operating scheme.Therefore, they continuously transmit a linear frequencymodulated signal, whose detection is performed by receiving the echo reflected by the target.
As shown in Fig. 2, the time of flight of the transmitted signal, t (i.e., the time it takes to get the target) and ultimately the distance d between sensor and target, can be drawn by measuring the frequency difference, f , between the transmitted and echo signals.Specifically, the distance d can be expressed as where B and T m are the modulation bandwidth and period of the transmitted signal, respectively, and c is the speed of light.As apparent, the radar resolution, namely, the minimum detectable distance d min , is inversely proportional to the bandwidth B. Therefore, improving the radar resolution calls for a higher and higher modulation bandwidth.In modern automotive radar systems, T m and f min (i.e., the minimum detectable frequency difference) are typically set to 10 µs and 100 kHz, respectively.Consequently, the 10-cm resolution targeted by S/MR applications translates into a modulation bandwidth requirement, and ultimately a VCO TR, as high as 4 GHz.Conversely, LR applications demand for the extension of the maximum detectable distance, d max , which is basically set by the RX sensitivity, S RX , and the transmitted power, P T .Of course, at a given P T , the echo signal level at the RX input rapidly drops out, while the distance between the target and the radar sensor increases.Therefore, the lower is P T , the higher should be the RX sensitivity to extend the radar coverage area.For the next generation of automotive radar sensors, a sensitivity as low as −110 dBm has been targeted, which imposes a stringent requirement for both the RX noise figure (NF) and the VCO PN.Specifically, assuming an RX NF of around 11 dB, the targeted RX sensitivity demands a VCO PN lower than −90 dBc/Hz at a 1-MHz offset frequency from the 77-GHz carrier [1], [9].
As mentioned above, the radar coverage area also depends on the transmitted power.Indeed, as well known from the  radar theory [10], d max can be expressed as follows: where G T and G R are the gains of the transmitting and receiving antennas, respectively, λ is the signal wavelength, L ATM is the atmosphere propagation loss, and σ is the radar cross section of the target.The atmosphere loss at 77 GHz is around 0.3-0.5 dB/km, and the radar cross section for a mid-size car is assumed to be 30 m 2 , whereas the receiving and transmitting antenna gain are typically around 20 dBi [9].Fig. 3 reports d max as a function of P T for S RX set to −110 dBm.As apparent, a transmitted power as high as 13 dBm is required to achieve an operating range higher than 250 m.Unfortunately, since the PA output power is affected by the package insertion loss besides suffering from process, voltage and temperature (PVT) variations, the power constraint for the PA is much more severe than predicted from (2).Indeed, although radar sensors usually exploit custom advanced flipchip assembly techniques, a package insertion loss of around 1 dB must be considered in the PA power budget.Furthermore, the output power exhibits a typical 3-dB additional reduction due to PVT variations.Therefore, the output power should be higher than 17 dBm to cope with LR applications.As far as the architecture is concerned, W -band radar sensors usually adopt a direct conversion scheme that guarantees high integration level and low power consumption.However, because of the zero offset between the frequencies of the LO and the transmitted signal, the LO can be affected by the PA output signal.Actually, due to the limited substrate isolation, especially at mm-wave, the PA signal may leak into the VCO, thus corrupting the LO spectrum.
To overcome this limitation, a frequency-doubled architecture is used in this work, as shown in Fig. 4. Therefore, the LO provides a carrier at half of the operating frequency, i.e., around 38 GHz, and a frequency doubler is used to drive the PA with the 77-GHz carrier.This avoids the VCO frequency pulling, thus improving the PN performance.

III. CIRCUIT DESIGN
The proposed TX was designed in a 28-nm FD-SOI CMOS technology, which provides 1-V low-V t transistors and has a low-cost standard back end of line (BEOL) [11].The lack of dedicated thick-copper metal layers, typically available in mm-wave customized technologies, makes crucial passive component design and layout arrangements (e.g., signal paths, power supply, and ground interconnections), which greatly affects the TX performance.Therefore, extensive electromagnetic (EM) simulations were carried out to drive the design of passive networks while carefully considering undesired parasitic effects.

A. VCO Design
The VCO is the very bottleneck for the implementation of a radar sensor embedding S/MR and LR features.Indeed, simultaneously achieving low PN and wide TR is a nontrivial task, especially at mm-wave frequencies.Nevertheless, designing a VCO able to address both S/MR and LR applications is mandatory to reduce production costs.To this aim, a wideband VCO is typically used [12], [13], [14], which relies on a single varactor to cover both LR and S/MR subbands, as shown in the solid line in Fig 5 .Although this approach can guarantee the required TR, it is not suitable to fulfill the PN requirements of LR applications due to the high conversion gain of the varactor (k VCO ).Indeed, the higher k VCO , the worse the PN performance due to a higher AM-to-phase modulation (PM) conversion [15].Actually, wide TR and low PN are not to be simultaneously provided.Indeed, LR applications exploit a small band typically ranging from 76 to 77 GHz (i.e., low TR requirement), where stringent PN performance is to be achieved to guarantee an operating range up to 250 m.Conversely, S/MR applications use a wider band extending from 77 to 81 GHz to get a resolution of a few centimeters, but they have a relaxed PN requirement.Therefore, a dualband VCO would be the best option to cope with both S/MR and LR applications.The basic idea is to implement a dualband operation based on a couple of varactors to cover the two targeted subbands, being the size of such varactors as small as possible, as shown in Fig. 5 (dashed lines).Consequently, k VCO in the lower band would be considerably reduced, thus improving PN performance, while a wide TR in the upper band would be simultaneously achieved.
Nevertheless, at the state of the art, dual-band operation is typically achieved by means of LC VCOs with switched components, such as switched capacitor (SC) [16], switched inductor (SL) [17], or switched core [18], as schematically shown in Fig. 6(a)-(c), respectively.SC-and SL-based VCOs exploit a shunt switch, SW, to enable/disable either a capacitor or an inductor.This allows the tuning curve to be properly shifted to cover both the lower and upper bands, as shown in Fig. 5 (squared lines), but without a substantial reduction of k VCO between the two configurations.Indeed, such solutions adopt a varactor, C V , that is sized to cover the wider TR, namely, that one related to the upper band.Consequently, the varactor turns out to be oversized for the operation in the lower band (i.e., the LR band), which results in a high k VCO and hence poor PN performance.Moreover, the switch SW provides a nonnegligible contribution to both resistive losses and parasitic capacitance of the VCO tank, thus affecting PN besides limiting the maximum VCO operating frequency.Conversely, switched-core VCOs take advantage of two different VCOs with optimized LC tank.Therefore, the lower and upper bands are merely covered by enabling the related core, which relies on a dedicated properly sized varactor (C V 1 or C V 2 ).This allows fulfilling PN requirements of the lower band while guaranteeing a wide TR in the upper band, but at the cost of both a large silicon area occupation and higher system complexity.
To overcome these limitations, a novel dual-band VCO is proposed [19].It consists of a single-core cross-coupled VCO operated at 1-V supply voltage for reduced power consumption.It features an LC tank with a couple of varactors, C V 1 and C V 2 , which are alternatively enabled by means of switches, SW and S W , as shown in Fig. 6(d).The basic idea is to use the enabled varactor C V 1 (C V 2 ) to cover the lower (upper) band, whereas the disabled varactor C V 2 (C V 1 ) acts as a fixed capacitor, allowing the tuning curve to be properly shifted.For the sake of completeness, varactor and switch configurations for both S/MR and LR mode operation are shown in Fig. 7(a) and (b), respectively.Fig. 7(c) shows the varactor normalized equivalent capacitance as a function of the control voltage, V C .Note that, according to the selected subband, V C is applied to the varactor that must be operated as a variable capacitance, namely, C V 1 for LR mode or C V 2 for S/MR mode.At the same time, the varactor that must be acted as a fixed capacitance, namely, C V 2 for LR mode or C V 1 for S/MR mode, is connected to the dc voltages, V B2 or V B1 , respectively.Specifically, in the lower band, the fixed contribution, C V 2 , must provide a large capacitance, and consequently, V B2 is set to 150 mV.Conversely, in the upper band, C V 1 must provide a small capacitance, and hence, V B1 is set to 850 mV.Due to this approach, the tuning varactor, i.e., the varactor that sets the TR for each subband and, hence, the related capacitance variation, is as small as possible, as shown in Fig. 7(c).This translates into a substantial reduction of the k VCO in the lower band, which improves the PN performance, while still guaranteeing a  wide TR in the upper band.Furthermore, it is worth noting that the band-selection switches are located at the common-mode node of the VCO tank.Therefore, they have negligible impact on the PN performance and no impact on the VCO maximum operating frequency, and this ultimately greatly relaxes the switch design.The full schematic of the proposed VCO is sketched in Fig. 8(a).It is based on an nMOS topology with transformer-coupled tank.The transformer allows increasing the equivalent load provided to the VCO active core, thus reducing the current consumption while simultaneously lowering the parasitic capacitance coming from the secondary side [20].The VCO active core consists of a cross-coupled differential pair, M 1,2 , which is operated in D-class with the aim of improving PN performance by maximizing oscillation amplitude [21].Accordingly, transistors M 1,2 are large to be operated as switches and to reduce the corner of the flicker noise, thus improving VCO PN at low offset frequency.Their channel width and length were set to 28 µm and 45 nm, respectively.AC coupling was preferred to implement the feedback path in the VCO active core since it allows the bias voltage, V BIAS , of transistor M 1,2 to be set to trade off startup condition and power consumption.
As far as the tank transformer is concerned, a 3-D view along with the adopted metal stack and main electrical parameters is shown in Fig. 8(b).The transformer adopts single-turn octagonal windings with a stacked configuration, whose inner diameter is 46 µm, while the metal width for primary and secondary coils is 16 and 25 µm, respectively.The thicker and outermost metal layers of the BEOL were used to minimize both resistive losses and parasitic capacitances.Extensive EM simulations were carried out to design this transformer also including interconnections and supply/ground paths, with the aim of minimizing undesired parasitic effects.

B. Frequency Doubler Design
Frequency doubling is a core feature of the proposed 77-GHz TX since it allows preventing VCO pulling, thus improving the PN performance of the LO.Fig. 9 shows the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.main frequency doubler techniques at the state of the art.The injection-locked frequency doublers (ILFDs) exploit an auxiliary oscillator operating at a frequency, f RF , which is twice the oscillation frequency, f LO , of the main VCO, as shown in Fig. 9(a).Basically, frequency doubling is performed by injecting the main VCO output signal into the auxiliary oscillator to lock its oscillation frequency.Although effective, this technique calls for a very high signal level to be injected into the auxiliary oscillator to guarantee locking, which is a critical requirement, especially at mm-wave frequencies.Indeed, a power-consuming amplification chain is required between the VCO and the ILFD to guarantee robust operation [22].Similarly, the harmonic-extractor doubler in Fig. 9(b) needs a high-gain amplification chain, tuned at f RF , being f RF = 2 × f LO , to selectively amplify the second harmonic of the VCO output signal.This ultimately allows frequency doubling to be performed but again with a complex and power-hungry solution, especially at mm-wave [23].Self-mixing-based multipliers allow doubling the VCO oscillation frequency, f LO , by means of a double-balanced Gilbert cell [24], as shown in Fig. 9(c).Specifically, by supplying both the LO and RF input port of the mixer with the f LO signal, a differential doubled output signal is delivered at the IF port, but at the cost of very high silicon area occupation and power consumption.Conversely, the push-push frequency doubler in Fig. 10(a) can deliver a doubled high-level output signal with low power consumption.Therefore, this solution is widely used at mmwave frequencies [25], [26], [27].It basically consists of a transistor pair, M 1,2 , in a common-source (CS) configuration, whose drain terminals are connected together.Transistors M 1,2 are driven by the LO signal and provide a common-mode RF output current, i RF , whose fundamental frequency, f RF , is twice f LO .Finally, a transformer-based resonant load tuned at f RF simultaneously performs current-to-voltage and singleended-to-differential conversion, thus providing a frequencydoubled output voltage, V RF [28].Unfortunately, push-push frequency doublers are inherently single-ended circuits, and hence, they suffer from a high sensitivity to the impedance, Z S , of the supply paths, namely, the routing paths used to locally deliver V DD and GND to the circuit.The simulated amplitude of the output signal of the push-push frequency multiplier is shown in Fig. 10(b) as a function of f RF for different Z S .As apparent, the output signal is heavily affected by Z S .Indeed, an equivalent impedance as low as 20 , which is provided by a parasitic inductance of 40 pH, can drastically reduce the output signal amplitude at 77 GHz.Therefore, the supply path impedances should be carefully considered for a correct design of a conventional push-push frequency doubler.Unfortunately, keeping sufficiently low such impedances is a nontrivial task at mm-wave frequency,  and this issue is especially critical for high complex systems such as radar sensors, which typically feature multiple TX and RX on the same die.To overcome this limitation a novel push-push frequency doubler is proposed, which is almost insensitive to the impedance of the supply paths [29].The simplified schematic of the proposed frequency doubler is reported in Fig. 11(a).It uses a cascode push-push pair M 1−4 that drives the load resonant transformer.To prevent the output current, i RF , from being affected by the supply paths, shunt resonators, L SHUNT − C SHUNT , are effectively used to decouple the inner circuitry from the supply path.Specifically, these resonators operate as dc-feed tuned at f RF .Therefore, they provide the frequency multiplier with the supply voltages (i.e., GND and V DD ) while simultaneously offering a relatively high impedance path at f RF .Finally, the series resonant bypass, L 0 − C 0 , tuned at f RF performs a low-impedance path for i RF between the output load and the local GND, thus avoiding the current to flow through Z S .This ultimately prevents the output load from being affected by Z S .The simulated amplitude of the output signal for the proposed frequency multiplier is shown in Fig. 11(b) as a function of f RF for different Z S .As apparent, despite the inherent single-ended operation, the adopted solution is almost insensitive to Z S .This greatly improves the circuit robustness, thus ultimately reducing the design effort.Moreover, the adoption of a cascode push-push pair leads to a higher conversion gain besides avoiding Miller amplification of gate-drain capacitances at the input.
Note that, the proposed, frequency doubler is meant to be operated with a supply voltage of 2 V. Therefore, the bias voltage, V B , of the common-gate (CG) transistors, M 3,4 , is properly set to simultaneously guarantee optimized frequency response and safe operating condition for the cascode pair.This is achieved by equally sharing the supply voltage  between the drain and source voltages of the stacked transistors M 1,3 and M 2,4 .Incidentally, this also maximizes output voltage swing, thus allowing the PA to be properly driven.A minimum channel length was used for the implementation of the cascode pair for optimum frequency response, the channel width was set to 12 µm for a fair tradeoff between conversion gain and power consumption.As far as the load transformer T 1 is concerned, a stacked topology was preferred since it guarantees the highest magnetic coupling coefficient, k, between transformer windings, which provides maximum power transfer and better area occupation with respect to interleaved structures.Finally, the folded configuration was used for the design of the inductors of the shunt, L SHUNT , and series resonators, L 0 , to allow circuit floor plan optimization.Indeed, folded inductors are highly area-saving with respect to traditional spiral inductors.For the sake of completeness, Table I summarizes the geometrical and electrical parameters of the adopted inductive components.
Finally, Fig. 12 shows the 3-D-layout view of the passive circuitry of the proposed frequency doubler, which includes inductors, transformers, and interconnections among components.This layout was used as the entry of the EM simulator to accurately account for both layout parasitics and undesired coupling effects.

C. PA Design
The PA is a key building block of the radar sensor since it sets the maximum distance at which a target can be properly detected.As mentioned above, achieving an operating distance as high as 250 m calls for a PA output power as high as 17 dBm.Unfortunately, this power requirement cannot be attained with single-path CMOS PAs, especially in a lowvoltage scaled CMOS implementation [30], [31].To overcome this limitation, a current-combining 2-V PA is used for this design.As shown in Fig. 13(a), it consists of a variable gain amplifier (VGA) that drives the PA presented in [32], which comprises two PA units arranged in a current-combining configuration to boost the power delivered to the output load.A feedback loop is also implemented to properly set the PA output power according to the targeted application.
Each PA unit includes a driver and power stage.As shown in Fig. 13(b), the driver stages, based on transistors M 1,2 , adopt a CS topology and exploit a transformer-coupled current-reuse approach in which they share the same quiescent current, thus saving power and improving PA efficiency.Neutralization capacitors, C n , are used to compensate for gate-drain capacitances of M 1,2 .This results in a higher input and output isolation, which increases frequency stability and gain performance.The power stage of each PA unit, based on transistors M 3−6 , adopts an enhanced-cascode topology in which series inductors L N between the CS and CG stages are used to compensate for the overall parasitic capacitance in the interstage node.Moreover, inductors L N perform an upward transformation on the real part of the input impedance of the CG transistors M 5,6 , thus improving the output power transfer.
The two PA units are coupled to the external load through stacked transformers, T OUT , which perform a currentcombining structure, simultaneously providing impedance matching, power combining, biasing, and differential-tosingle-ended conversion.
The two PA units are driven by a 77-GHz VGA, which allows the PA input power to be properly controlled, thus setting the PA output power.The simplified schematic of the designed VGA is shown in Fig. 14.It exploits a cascode differential topology with the CG stage implemented by two pairs of source-coupled transistors M 3,4 and M 5,6 , whose drain terminals are connected to the supply voltage or to the output load.This allows delivering the output power either to the  two PA units or to the supply voltage according to the control signal, V CTRL , applied to the gate terminals of M 4,6 .
The VGA is loaded by a three-way transformer, T V −D , which allows equally splitting the output power to drive the two PA units with the same input signal level.The VGA control voltage, V CTRL , is properly set by the feedback loop shown in Fig. 13(a).It comprises a peak detector and an error amplifier (EA).The peak detector is made up of an ac-coupled common-drain stage [32], which provides a dc output voltage, V PEAK , proportional to the PA output power.The EA compares V PEAK with a reference voltage, V REF , and sets accordingly the VGA control voltage, V CTRL , which properly tunes the PA input power to deliver the desired power to the output load.Therefore, the PA output power can be set to address the specific S/MR and LR radar requirements by merely changing V REF .Loop stability is guaranteed by capacitance C C , which performs dominant pole compensation at the output of the EA.The simulated open-loop gain is around 50 dB with a 3-MHz bandwidth and a phase margin of around 70 • .
The proposed PA is operated with a 2-V power supply.The bias voltages of the CG stages in the cascode structures of both the VGA and power stages (i.e., V B1 and V B5 , respectively) are set to equally split the supply voltage between the drain and source voltages of CS and CG stages, as in the frequency doubler.
Finally, extensive EM simulations of the PA passive circuitry from the VGA transformer to the power stages were carried out to accurately account for both layout parasitics and undesired coupling effects.An s-parameter model of this circuitry was extracted from the EM simulations and embedded into the main schematic entry to finely tune transistor aspect ratios and matching networks for the optimum PA performance.Fig. 15 shows a 3-D-layout view of this passive circuitry, which includes inductors, transformers, and interconnections among components.The main simulated electrical parameters of the PA transformers are summarized in Table II.

IV. EXPERIMENTAL RESULTS
The proposed 77-GHz radar TX was fabricated in a 28-nm FD-SOI CMOS technology by STMicroelectronics, which features a standard low-cost BEOL with eight copper metal layers plus an aluminum top one, and metal-oxide-metal (MOM) capacitors with a 5 fF/µm 2 of specific capacitance.A chip microphotograph is shown in Fig. 16.The die area is pad limited for exhaustive testing purposes.The total area is 2.9 × 1.7 mm, whereas the core size is 1.1 × 0.3 mm, excluding testing circuitry (i.e., 20-GHz output buffer).A simplified block diagram and a photograph of the adopted measurement setup are shown in Fig. 17(a) and (b), respectively.The chip was assembled on an FR4 printed circuit board using the chip-on-board approach to allow wire bonding of low-frequency signals (i.e., bias terminals and control bits).Conversely, mm-wave signals are directly probed on die by means of a cascade probe station, using dedicated GSG on-chip pads, as shown in Fig. 17.Specifically, the TX provides two mm-wave outputs, namely, the 50-PA output at 77 GHz and a 50-output at 20 GHz, which is used for better VCO characterization.To this aim, the VCO was also embedded within an on-chip phase-locked loop (PLL) designed for testing purpose, which uses an off-chip 2nd-order low-pass filter (LPF).The integrated PLL is operated at 1-V supply voltage and adopts a frequency divider by 384 and a reference frequency of around 100 MHz.The measurement setup includes a spectrum analyzer and a signal generator as a PLL frequency reference.Fig. 18 shows the measured and simulated VCO TR and k VCO .As apparent, a good agreement between measurements and simulations was achieved.The oscillation frequency ranges from 37.7 to 38.6 GHz and from 38.3 to 40.7 GHz in the lower and upper bands, respectively, with the varactor control voltage swept from 0 to 1 V. Due to the adopted VCO tank architecture, the peak value of k VCO  As discussed, the VCO drives, through the frequency doubler, the two-path PA.The TX output power as a function of frequency is shown in Fig. 20.The TX can deliver a maximum saturated output power, P sat , of 17.5 dBm at 78 GHz.The output power curve is almost flat over a wide frequency range.Specifically, it exhibits a variation of around 2 dB in the band of interest, ranging from 76 to 81 GHz.Moreover, simulations give a reduction of the saturated output power of around 1 dB at 125 • C. The operation of the power control loop is shown in Fig. 21, which shows the TX output power as a function Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply. of the reference voltage, V REF , with the operating frequency of 78 GHz.An extended power range of around 13 dB is achieved, which allows properly addressing with the same device for both S/MR and LR applications that have very different requirements in terms of output power.Importantly, the power control loop is aimed at keeping the output power as flat as possible in the operating band, which is a challenging feature, especially for the S/MR applications.Fig. 22 shows the TX output power for both open-and closed-loop conditions for an output power level of 13 dBm.As apparent, the control loop allows quite flat output power over the operating band to be achieved.

TABLE IV PERFORMANCE COMPARISON WITH STATE-OF-THE-ART 77-GHz TXs
Table III gives supply voltages and power consumptions of main building blocks as well as of the whole TX.The overall TX power consumption is 351 mW.Finally, Table IV summarizes the TX experimental results while comparing them with the state of the art of 77-GHz CMOS works.The proposed TX exhibits the highest saturated output power along with an excellent PN performance.A similar PN performance is reported in [6], which adopts a 16-GHz VCO and, hence, a higher frequency-multiplication factor.This solution increases the TR but at the cost of higher silicon area, due to the higher inductor required by the VCO tank.Moreover, the more complex frequency multiplier to provide the 77-GHz carrier further increases silicon area besides power dissipation.Therefore, the adopted frequency-doubling architecture turns out to be the best solution to trade off TX performance and power/area consumption.As a proof of this, the proposed TX exhibits the best P dc /P sat ratio (i.e., the minimum power consumption per output power) while guaranteeing a 5-GHz bandwidth.

V. CONCLUSION
This article presents a 77-GHz radar TX implemented in a 28-nm FD-SOI CMOS technology.The circuit has been designed to simultaneously fulfill both S/MR and LR applications.Starting from an integrated 38-GHz VCO, a frequency doubler provides the 77-GHz carrier that drives the current combining two-path PA.Despite the standard BEOL of the adopted technology, the proposed TX achieves an excellent saturated output power as high as 17.5 dBm and a PN performance as low as −93 dBc/Hz at the 1-MHz offset frequency from the 77-GHz carrier while covering 5 GHz of operating bandwidth.

Fig. 3 .
Fig. 3. Operating distance, d max , as a function of the required transmitted power, P T , according to (2).

Fig. 7 .
Fig. 7. Switch configuration for (a) S/MR and (b) LR operation, and (c) varactor normalized equivalent capacitance as a function of the control voltage.

Fig. 8 .
Fig. 8. Proposed dual-band VCO.(a) Completed schematic.(b) 3-D view of the transformer with the adopted metal stack and its main parameters.

Fig. 10 .
Fig. 10.(a) Simplified schematic of a push-push frequency doubler.(b) Simulated output voltage as a function of fRF for different values of Z S .

Fig. 11 .
Fig. 11.(a) Simplified schematic of the proposed push-push frequency doubler.(b) Simulated output voltage for different values of Z S .

Fig. 12
Fig. 12. 3-D view of the passive circuitry of the frequency multiplier.

Fig. 13 .
Fig. 13.Proposed two-path PA: (a) simplified block diagram and (b) schematic of the PA units.

Fig. 15
Fig. 15.3-D view of the passive circuitry of the two-path PA.

Fig. 19 .
Fig. 19.Measured PN for S/MR and LR band at the 1-MHz offset frequency.

Fig. 20 .
Fig. 20.TX output power as a function of frequency.

Fig. 21 .
Fig. 21.TX output power as a function of the reference voltage.

TABLE I INDUCTIVE
COMPONENT GEOMETRICAL AND ELECTRICAL PARAMETERS

TABLE II ELECTRICAL
PARAMETERS OF TRANSFORMERS AT 77 GHz

TABLE III SUMMARIZED
POWER CONSUMPTION AND SUPPLY VOLTAGES